library IEEE;
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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-- Uncomment the following lines to use the declarations that are
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-- Uncomment the following lines to use the declarations that are
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-- provided for instantiating Xilinx primitive components.
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-- provided for instantiating Xilinx primitive components.
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--library UNISIM;
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--library UNISIM;
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--use UNISIM.VComponents.all;
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--use UNISIM.VComponents.all;
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entity output is
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entity output is
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Port ( clk : in std_logic;
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Port ( clk : in std_logic;
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rst : in std_logic;
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rst : in std_logic;
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Iout : in std_logic_vector(13 downto 0);
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Iout : in std_logic_vector(13 downto 0);
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Qout : in std_logic_vector(13 downto 0);
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Qout : in std_logic_vector(13 downto 0);
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Output_enable : in std_logic;
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Output_enable : in std_logic;
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addrout_out : out std_logic_vector(5 downto 0);
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addrout_out : out std_logic_vector(5 downto 0);
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txserial : out std_logic
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txserial : out std_logic
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);
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);
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end output;
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end output;
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architecture output of output is
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architecture output of output is
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type state is (s0,s1,s2,s3,s4,s5,s6,s7,s8);
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type state is (s0,s1,s2,s3,s4,s5,s6,s7,s8);
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signal st : state;
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signal st : state;
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signal addr : std_logic_vector(5 downto 0);
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signal addr : std_logic_vector(5 downto 0);
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begin
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begin
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addrout_out <= addr;
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addrout_out <= addr;
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acoes:process(clk,rst)
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acoes:process(clk,rst)
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begin
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begin
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if rst ='1' then
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if rst ='1' then
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addr <= conv_std_logic_vector(1,6);
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addr <= conv_std_logic_vector(1,6);
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txserial <= '1';
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txserial <= '1';
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elsif clk'event and clk='1' then
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elsif clk'event and clk='1' then
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case st is
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case st is
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when s0 => -- espera output_enable
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when s0 => -- espera output_enable
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txserial <= '1';
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txserial <= '1';
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addr <= conv_std_logic_vector(1,6);
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addr <= conv_std_logic_vector(1,6);
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when s1|s2|s3|s4 => -- qam decoder
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when s1|s2|s3|s4 => -- qam decoder
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txserial <= Iout(13);
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txserial <= Iout(13);
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when s5|s6|s8 =>
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when s5|s6|s8 =>
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txserial <= Qout(13);
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txserial <= Qout(13);
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when s7 =>
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when s7 =>
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txserial <= Qout(13);
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txserial <= Qout(13);
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if addr /= 31 then
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if addr /= 31 then
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addr <= addr+1;
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addr <= addr+1;
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else
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else
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addr <= conv_std_logic_vector(1,6);
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addr <= conv_std_logic_vector(1,6);
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end if;
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end if;
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end case;
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end case;
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end if;
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end if;
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end process;
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end process;
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estados:process(clk,rst)
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estados:process(clk,rst)
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begin
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begin
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if rst ='1' then
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if rst ='1' then
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st <= s0;
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st <= s0;
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elsif clk'event and clk='1' then
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elsif clk'event and clk='1' then
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case st is
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case st is
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when s0 =>
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when s0 =>
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if Output_enable = '1' then
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if Output_enable = '1' then
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st <= s1;
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st <= s1;
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else
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else
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st <= s0;
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st <= s0;
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end if;
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end if;
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when s1 =>
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when s1 =>
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st <= s2;
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st <= s2;
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when s2 =>
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when s2 =>
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st <= s3;
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st <= s3;
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when s3 =>
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when s3 =>
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st <= s4;
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st <= s4;
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when s4 =>
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when s4 =>
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st <= s5;
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st <= s5;
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when s5 =>
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when s5 =>
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st <= s6;
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st <= s6;
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when s6 =>
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when s6 =>
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st <= s7;
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st <= s7;
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when s7=>
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when s7=>
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st <= s8;
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st <= s8;
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when s8=>
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when s8=>
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st <= s1;
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st <= s1;
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end case;
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end case;
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end if;
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end if;
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end process;
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end process;
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