library IEEE;
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library IEEE;
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use IEEE.STD_LOGIC_1164.all;
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use IEEE.STD_LOGIC_1164.all;
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use IEEE.STD_LOGIC_ARITH.all;
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use IEEE.STD_LOGIC_ARITH.all;
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use IEEE.STD_LOGIC_UNSIGNED.all;
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use IEEE.STD_LOGIC_UNSIGNED.all;
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-- Uncomment the following lines to use the declarations that are
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-- Uncomment the following lines to use the declarations that are
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-- provided for instantiating Xilinx primitive components.
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-- provided for instantiating Xilinx primitive components.
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--library UNISIM;
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--library UNISIM;
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--use UNISIM.VComponents.all;
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--use UNISIM.VComponents.all;
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entity txmodem is
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entity txmodem is
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port ( clk : in std_logic;
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port ( clk : in std_logic;
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rst : in std_logic;
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rst : in std_logic;
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serial : in std_logic;
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serial : in std_logic;
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Iout : out std_logic_vector(13 downto 0);
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Iout : out std_logic_vector(13 downto 0);
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Output_enable : out std_logic;
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Output_enable : out std_logic;
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addrout_out : in std_logic_vector(5 downto 0)
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addrout_out : in std_logic_vector(5 downto 0)
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);
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);
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end txmodem;
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end txmodem;
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architecture txmodem of txmodem is
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architecture txmodem of txmodem is
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component input
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component input
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port (
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port (
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clk : in std_logic;
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clk : in std_logic;
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rst : in std_logic;
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rst : in std_logic;
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serial : in std_logic;
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serial : in std_logic;
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mem_block : in std_logic;
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mem_block : in std_logic;
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mem_ready : out std_logic;
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mem_ready : out std_logic;
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wen : out std_logic;
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wen : out std_logic;
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address : out std_logic_vector (5 downto 0);
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address : out std_logic_vector (5 downto 0);
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i : out std_logic_vector(11 downto 0);
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i : out std_logic_vector(11 downto 0);
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q : out std_logic_vector(11 downto 0)
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q : out std_logic_vector(11 downto 0)
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);
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);
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end component;
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end component;
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component ofdm
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component ofdm
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generic (
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generic (
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Tx_nRx : natural;
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Tx_nRx : natural;
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WIDTH : natural;
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WIDTH : natural;
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POINT : natural;
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POINT : natural;
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STAGE : natural);
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STAGE : natural);
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port (
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port (
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clk : in std_logic;
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clk : in std_logic;
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rst : in std_logic;
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rst : in std_logic;
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mem_ready : in std_logic;
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mem_ready : in std_logic;
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Iin : in std_logic_vector(WIDTH-1 downto 0);
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Iin : in std_logic_vector(WIDTH-1 downto 0);
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Qin : in std_logic_vector(WIDTH-1 downto 0);
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Qin : in std_logic_vector(WIDTH-1 downto 0);
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Iout : out std_logic_vector(WIDTH+1 downto 0);
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Iout : out std_logic_vector(WIDTH+1 downto 0);
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Qout : out std_logic_vector(WIDTH+1 downto 0);
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Qout : out std_logic_vector(WIDTH+1 downto 0);
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mem_block : out std_logic;
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mem_block : out std_logic;
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Output_enable : out std_logic;
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Output_enable : out std_logic;
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bank0_busy : out std_logic;
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bank0_busy : out std_logic;
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bank1_busy : out std_logic;
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bank1_busy : out std_logic;
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wen_in : in std_logic;
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wen_in : in std_logic;
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addrin_in : in std_logic_vector(2*stage-Tx_nRX downto 0);
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addrin_in : in std_logic_vector(2*stage-Tx_nRX downto 0);
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addrout_out : in std_logic_vector(2*stage-1 downto 0));
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addrout_out : in std_logic_vector(2*stage-1 downto 0));
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end component;
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end component;
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signal mem_block : std_logic;
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signal mem_block : std_logic;
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signal mem_ready : std_logic;
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signal mem_ready : std_logic;
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signal wen : std_logic;
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signal wen : std_logic;
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signal address : std_logic_vector (5 downto 0);
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signal address : std_logic_vector (5 downto 0);
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signal i : std_logic_vector(11 downto 0);
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signal i : std_logic_vector(11 downto 0);
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signal q : std_logic_vector(11 downto 0);
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signal q : std_logic_vector(11 downto 0);
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begin
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begin
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input_1 : input
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input_1 : input
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port map (
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port map (
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clk => clk,
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clk => clk,
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rst => rst,
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rst => rst,
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serial => serial,
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serial => serial,
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mem_block => mem_block,
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mem_block => mem_block,
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mem_ready => mem_ready,
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mem_ready => mem_ready,
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wen => wen,
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wen => wen,
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address => address,
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address => address,
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i => i,
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i => i,
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q => q
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q => q
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);
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);
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ofdm_1 : ofdm
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ofdm_1 : ofdm
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generic map (
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generic map (
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Tx_nRx => 1,
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Tx_nRx => 1,
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WIDTH => 12,
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WIDTH => 12,
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POINT => 64,
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POINT => 64,
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STAGE => 3)
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STAGE => 3)
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port map (
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port map (
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clk => clk,
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clk => clk,
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rst => rst,
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rst => rst,
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mem_ready => mem_ready,
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mem_ready => mem_ready,
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Iin => I,
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Iin => I,
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Qin => Q,
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Qin => Q,
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Iout => Iout,
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Iout => Iout,
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Qout => open,
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Qout => open,
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mem_block => mem_block,
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mem_block => mem_block,
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Output_enable => Output_enable,
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Output_enable => Output_enable,
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bank0_busy => open,
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bank0_busy => open,
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bank1_busy => open,
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bank1_busy => open,
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wen_in => wen,
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wen_in => wen,
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addrin_in => address,
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addrin_in => address,
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addrout_out => addrout_out);
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addrout_out => addrout_out);
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end txmodem;
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end txmodem;
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