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Rev 2 Rev 13
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--
--
-- Title       : div4limit
-- Title       : div4limit
-- Design      : cfft
-- Design      : cfft
-- Author      : ZHAO Ming
-- Author      : ZHAO Ming
-- email           : sradio@opencores.org
-- email           : sradio@opencores.org
--
--
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--
--
-- File        : div4limit.vhd
-- File        : div4limit.vhd
-- Generated   : Tue Jul 16 10:39:17 2002
-- Generated   : Tue Jul 16 10:39:17 2002
--
--
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--
--
-- Description : Div 4 Limit to 12 bit
-- Description : Div 4 Limit to 12 bit
--
--
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--
--
-- Revisions       :    0
-- Revisions       :    0
-- Revision Number :    1
-- Revision Number :    1
-- Version         :    1
-- Version         :    1
-- Date            :    Oct 17 2002
-- Date            :    Oct 17 2002
-- Modifier        :    ZHAO Ming 
-- Modifier        :    ZHAO Ming 
-- Desccription    :    Data width configurable 
-- Desccription    :    Data width configurable 
--
--
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library IEEE;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
 
 
entity div4limit is
entity div4limit is
        generic (
        generic (
                WIDTH : Natural
                WIDTH : Natural
        );
        );
        port(
        port(
                clk : in std_logic;
                clk : in std_logic;
                 D : in STD_LOGIC_VECTOR(WIDTH+3 downto 0);
                 D : in STD_LOGIC_VECTOR(WIDTH+3 downto 0);
                 Q : out STD_LOGIC_VECTOR(WIDTH-1 downto 0)
                 Q : out STD_LOGIC_VECTOR(WIDTH-1 downto 0)
             );
             );
end div4limit;
end div4limit;
 
 
architecture div4limit of div4limit is
architecture div4limit of div4limit is
begin
begin
 
 
process( clk )
process( clk )
variable Temp_D:std_logic_vector( WIDTH+1 downto 0 );
variable Temp_D:std_logic_vector( WIDTH+1 downto 0 );
begin
begin
        if clk'event and clk='1' then
        if clk'event and clk='1' then
                Temp_D:=D( WIDTH+3 downto 2 )+D(1);
                Temp_D:=D( WIDTH+3 downto 2 )+D(1);
                if Temp_D(WIDTH+1)='1' and Temp_D(WIDTH downto WIDTH-1)/="11" then
                if Temp_D(WIDTH+1)='1' and Temp_D(WIDTH downto WIDTH-1)/="11" then
                        Temp_D(WIDTH+1 downto WIDTH-1):="111";
                        Temp_D(WIDTH+1 downto WIDTH-1):="111";
                        Temp_D(WIDTH-2 downto 1):=( others=>'0' );
                        Temp_D(WIDTH-2 downto 1):=( others=>'0' );
                        Temp_D(0):='1';
                        Temp_D(0):='1';
                elsif Temp_D(WIDTH+1)='0' and Temp_D(WIDTH downto WIDTH-1)/="00" then
                elsif Temp_D(WIDTH+1)='0' and Temp_D(WIDTH downto WIDTH-1)/="00" then
                        Temp_D(WIDTH+1 downto WIDTH-1):="000";
                        Temp_D(WIDTH+1 downto WIDTH-1):="000";
                        Temp_D(WIDTH-2 downto 0):=( others=>'1' );
                        Temp_D(WIDTH-2 downto 0):=( others=>'1' );
                end if;
                end if;
                Q<=Temp_D(WIDTH-1 downto 0 );
                Q<=Temp_D(WIDTH-1 downto 0 );
        end if;
        end if;
end process;
end process;
 
 
end div4limit;
end div4limit;
 
 

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