library IEEE;
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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-- Uncomment the following lines to use the declarations that are
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-- Uncomment the following lines to use the declarations that are
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-- provided for instantiating Xilinx primitive components.
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-- provided for instantiating Xilinx primitive components.
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--library UNISIM;
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--library UNISIM;
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--use UNISIM.VComponents.all;
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--use UNISIM.VComponents.all;
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entity input is
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entity input is
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Port ( clk : in std_logic;
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Port ( clk : in std_logic;
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rst : in std_logic;
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rst : in std_logic;
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serial : in std_logic;
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serial : in std_logic;
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mem_block : in std_logic;
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mem_block : in std_logic;
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mem_ready : out std_logic;
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mem_ready : out std_logic;
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wen : out std_logic;
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wen : out std_logic;
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address : out std_logic_vector (5 downto 0);
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address : out std_logic_vector (5 downto 0);
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i : out std_logic_vector(11 downto 0);
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i : out std_logic_vector(11 downto 0);
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q : out std_logic_vector(11 downto 0);
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q : out std_logic_vector(11 downto 0)
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);
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);
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end input;
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end input;
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architecture input of input is
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architecture input of input is
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type state is (s0, s1, s2, s3, s4, s5, s6, s7);
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type state is (s0, s1, s2, s3, s4, s5, s6, s7);
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signal st: state;
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signal st: state;
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signal meta, sync : std_logic;
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signal meta, sync : std_logic;
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signal addr : std_logic_vector(5 downto 0);
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signal addr : std_logic_vector(5 downto 0);
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begin
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begin
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process(clk,rst)
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process(clk,rst)
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--constant mais1 : std_logic_vector(11 downto 0) := "001100000000";
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--constant mais1 : std_logic_vector(11 downto 0) := "001100000000";
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constant mais1 : std_logic_vector(11 downto 0) := x"080";
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constant mais1 : std_logic_vector(11 downto 0) := x"080";
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constant menos1 : std_logic_vector(11 downto 0) := "110100000000";
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constant menos1 : std_logic_vector(11 downto 0) := "110100000000";
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begin
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begin
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-- 0123.45678901 bits
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-- 0123.45678901 bits
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-- 0011.00000000 = +1
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-- 0011.00000000 = +1
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-- 1101.00000000 = -1
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-- 1101.00000000 = -1
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-- Q
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-- Q
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-- o | o
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-- o | o
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-- 01 | 00
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-- 01 | 00
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-- |
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-- |
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-- ----------------- I
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-- ----------------- I
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-- |
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-- |
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-- 11 | 10
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-- 11 | 10
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-- o | o
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-- o | o
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if rst = '1' then
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if rst = '1' then
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st <= s0;
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st <= s0;
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mem_ready <= '0';
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mem_ready <= '0';
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wen <= '0';
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wen <= '0';
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addr <= (others => '0');
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addr <= (others => '0');
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address <= (others => '0');
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address <= (others => '0');
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i <= mais1;
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i <= mais1;
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q <= mais1;
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q <= mais1;
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elsif clk'event and clk='1' then
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elsif clk'event and clk='1' then
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case st is
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case st is
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when s0 =>
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when s0 =>
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st <= s1;
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st <= s1;
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meta <= serial;
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meta <= serial;
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wen <= '0';
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wen <= '0';
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when s1 =>
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when s1 =>
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st <= s2;
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st <= s2;
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sync <= meta;
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sync <= meta;
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when s2 =>
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when s2 =>
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st <= s3;
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st <= s3;
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if sync='0' then
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if sync='0' then
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i <= mais1;
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i <= mais1;
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else
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else
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i <= menos1;
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i <= menos1;
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end if;
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end if;
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when s3 =>
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when s3 =>
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st <= s4;
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st <= s4;
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when s4 =>
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when s4 =>
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st <= s5;
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st <= s5;
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meta <= serial;
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meta <= serial;
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addr <= addr +1;
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addr <= addr +1;
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when s5 =>
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when s5 =>
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st <= s6;
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st <= s6;
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sync <= meta;
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sync <= meta;
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if unsigned(addr) = 32 then
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if unsigned(addr) = 32 then
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addr <= conv_std_logic_vector(1,6);
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addr <= conv_std_logic_vector(1,6);
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mem_ready <= '1';
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mem_ready <= '1';
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end if;
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end if;
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when s6 =>
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when s6 =>
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st <= s7;
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st <= s7;
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mem_ready <= '0';
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mem_ready <= '0';
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if sync='0' then
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if sync='0' then
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q <= mais1;
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q <= mais1;
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else
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else
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q <= menos1;
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q <= menos1;
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end if;
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end if;
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when s7 =>
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when s7 =>
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st <= s0;
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st <= s0;
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if mem_block = '0' then
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if mem_block = '0' then
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address <= addr+32;
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address <= addr+32;
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else
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else
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address <= addr;
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address <= addr;
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end if;
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end if;
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wen <= '1';
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wen <= '1';
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end case;
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end case;
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end if;
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end if;
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end process;
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end process;
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