library IEEE;
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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-- Uncomment the following lines to use the declarations that are
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-- Uncomment the following lines to use the declarations that are
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-- provided for instantiating Xilinx primitive components.
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-- provided for instantiating Xilinx primitive components.
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--library UNISIM;
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--library UNISIM;
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--use UNISIM.VComponents.all;
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--use UNISIM.VComponents.all;
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entity txrx is
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entity txrx is
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Port ( clk : in std_logic;
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Port ( clk : in std_logic;
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rst : in std_logic;
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rst : in std_logic;
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Output_enable : in std_logic;
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Output_enable : in std_logic;
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mem_block : in std_logic;
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mem_block : in std_logic;
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--mem_ready : out std_logic;
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--mem_ready : out std_logic;
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wen : out std_logic;
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wen : out std_logic;
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address : out std_logic_vector(6 downto 0)
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address : out std_logic_vector(6 downto 0)
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);
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);
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end txrx;
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end txrx;
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architecture interface of txrx is
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architecture interface of txrx is
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signal ifsel: boolean;
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signal ifsel: boolean;
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signal add : std_logic_vector(6 downto 0);
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signal add : std_logic_vector(6 downto 0);
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signal wen_aux : std_logic;
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signal wen_aux : std_logic;
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begin
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begin
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wen <= wen_aux;
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wen <= wen_aux;
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address <= add;
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address <= add;
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process (clk,rst)
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process (clk,rst)
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begin
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begin
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if rst = '1' then
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if rst = '1' then
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add <= (others => '0');
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add <= (others => '0');
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wen_aux <= '0';
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wen_aux <= '0';
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elsif clk'event and clk='1' then
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elsif clk'event and clk='1' then
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if Output_enable = '1' then
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if Output_enable = '1' then
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wen_aux <= '1';
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wen_aux <= '1';
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if mem_block = '0' then
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if mem_block = '0' then
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add <= (others => '0');
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add <= (others => '0');
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else
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else
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add <= conv_std_logic_vector(64,7);
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add <= conv_std_logic_vector(64,7);
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end if;
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end if;
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elsif wen_aux = '1' then
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elsif wen_aux = '1' then
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if (add(5 downto 0) /= 63) then
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if (add(5 downto 0) /= 63) then
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add <= add + 1;
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add <= add + 1;
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else
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else
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wen_aux <= '0';
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wen_aux <= '0';
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add <= add;
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add <= add;
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end if;
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end if;
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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