library IEEE;
|
library IEEE;
|
use IEEE.STD_LOGIC_1164.all;
|
use IEEE.STD_LOGIC_1164.all;
|
use IEEE.STD_LOGIC_ARITH.all;
|
use IEEE.STD_LOGIC_ARITH.all;
|
use IEEE.STD_LOGIC_UNSIGNED.all;
|
use IEEE.STD_LOGIC_UNSIGNED.all;
|
|
|
-- Uncomment the following lines to use the declarations that are
|
-- Uncomment the following lines to use the declarations that are
|
-- provided for instantiating Xilinx primitive components.
|
-- provided for instantiating Xilinx primitive components.
|
--library UNISIM;
|
--library UNISIM;
|
--use UNISIM.VComponents.all;
|
--use UNISIM.VComponents.all;
|
|
|
entity juntos is
|
entity juntos is
|
port(
|
port(
|
clk : in std_logic;
|
clk : in std_logic;
|
rst : in std_logic;
|
rst : in std_logic;
|
rx : in std_logic;
|
rx : in std_logic;
|
tx : out std_logic);
|
tx : out std_logic);
|
|
|
end juntos;
|
end juntos;
|
|
|
architecture Behavioral of juntos is
|
architecture Behavioral of juntos is
|
|
|
component parallel
|
component parallel
|
port (
|
port (
|
clk : in std_logic;
|
clk : in std_logic;
|
rst : in std_logic;
|
rst : in std_logic;
|
input : in std_logic;
|
input : in std_logic;
|
output : out std_logic_vector(1 downto 0));
|
output : out std_logic_vector(1 downto 0));
|
end component;
|
end component;
|
|
|
component qam
|
component qam
|
port (
|
port (
|
clk : in std_logic;
|
clk : in std_logic;
|
rst : in std_logic;
|
rst : in std_logic;
|
input : in std_logic_vector(1 downto 0);
|
input : in std_logic_vector(1 downto 0);
|
Iout : out std_logic_vector(11 downto 0);
|
Iout : out std_logic_vector(11 downto 0);
|
Qout : out std_logic_vector(11 downto 0));
|
Qout : out std_logic_vector(11 downto 0));
|
end component;
|
end component;
|
|
|
component qamdecoder
|
component qamdecoder
|
port (
|
port (
|
clk : in std_logic;
|
clk : in std_logic;
|
rst : in std_logic;
|
rst : in std_logic;
|
Iin : in std_logic_vector(11 downto 0);
|
Iin : in std_logic_vector(11 downto 0);
|
Qin : in std_logic_vector(11 downto 0);
|
Qin : in std_logic_vector(11 downto 0);
|
output : out std_logic_vector(1 downto 0));
|
output : out std_logic_vector(1 downto 0));
|
end component;
|
end component;
|
|
|
component serial
|
component serial
|
port (
|
port (
|
clk : in std_logic;
|
clk : in std_logic;
|
rst : in std_logic;
|
rst : in std_logic;
|
input : in std_logic_vector(1 downto 0);
|
input : in std_logic_vector(1 downto 0);
|
output : out std_logic);
|
output : out std_logic);
|
end component;
|
end component;
|
|
|
signal input : std_logic_vector(1 downto 0);
|
signal input : std_logic_vector(1 downto 0);
|
signal output : std_logic_vector(1 downto 0);
|
signal output : std_logic_vector(1 downto 0);
|
signal Iin : std_logic_vector(11 downto 0);
|
signal Iin : std_logic_vector(11 downto 0);
|
signal Qin : std_logic_vector(11 downto 0);
|
signal Qin : std_logic_vector(11 downto 0);
|
|
|
begin
|
begin
|
par_input : parallel
|
par_input : parallel
|
port map(
|
port map(
|
clk => clk,
|
clk => clk,
|
rst => rst,
|
rst => rst,
|
input => rx,
|
input => rx,
|
output => input);
|
output => input);
|
|
|
qam_1 : qam
|
qam_1 : qam
|
port map (
|
port map (
|
clk => clk,
|
clk => clk,
|
rst => rst,
|
rst => rst,
|
input => input,
|
input => input,
|
Iout => Iin,
|
Iout => Iin,
|
Qout => Qin);
|
Qout => Qin);
|
|
|
|
|
qamdecoder_1: qamdecoder
|
qamdecoder_1: qamdecoder
|
port map (
|
port map (
|
clk => clk,
|
clk => clk,
|
rst => rst,
|
rst => rst,
|
Iin => Iin,
|
Iin => Iin,
|
Qin => Qin,
|
Qin => Qin,
|
output => output);
|
output => output);
|
|
|
serial_1: serial
|
serial_1: serial
|
port map (
|
port map (
|
clk => clk,
|
clk => clk,
|
rst => rst,
|
rst => rst,
|
input => output,
|
input => output,
|
output => tx);
|
output => tx);
|
|
|
end Behavioral;
|
end Behavioral;
|
|
|