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library IEEE;
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library IEEE;
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use IEEE.STD_LOGIC_1164.all;
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use IEEE.STD_LOGIC_1164.all;
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use IEEE.STD_LOGIC_ARITH.all;
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use IEEE.STD_LOGIC_ARITH.all;
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use IEEE.STD_LOGIC_UNSIGNED.all;
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use IEEE.STD_LOGIC_UNSIGNED.all;
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-- Uncomment the following lines to use the declarations that are
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-- Uncomment the following lines to use the declarations that are
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-- provided for instantiating Xilinx primitive components.
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-- provided for instantiating Xilinx primitive components.
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--library UNISIM;
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--library UNISIM;
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--use UNISIM.VComponents.all;
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--use UNISIM.VComponents.all;
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entity qam is
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entity qam is
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port (
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port (
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clk : in std_logic;
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clk : in std_logic;
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rst : in std_logic;
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rst : in std_logic;
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input : in std_logic_vector(1 downto 0);
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input : in std_logic_vector(1 downto 0);
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Iout : out std_logic_vector(11 downto 0);
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Iout : out std_logic_vector(11 downto 0);
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Qout : out std_logic_vector(11 downto 0));
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Qout : out std_logic_vector(11 downto 0));
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end qam;
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end qam;
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architecture qam of qam is
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architecture qam of qam is
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begin
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begin
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process (clk, rst)
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process (clk, rst)
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constant mais1 : std_logic_vector(11 downto 0) := "001100000000";
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constant mais1 : std_logic_vector(11 downto 0) := "001100000000";
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constant menos1 : std_logic_vector(11 downto 0) := "110100000000";
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constant menos1 : std_logic_vector(11 downto 0) := "110100000000";
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begin
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begin
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if rst = '1' then
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if rst = '1' then
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Iout <= (others => '0');
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Iout <= (others => '0');
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Qout <= (others => '0');
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Qout <= (others => '0');
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elsif clk'event and clk = '1' then
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elsif clk'event and clk = '1' then
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-- 0123.45678901 bits
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-- 0123.45678901 bits
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-- 0011.00000000 = +1
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-- 0011.00000000 = +1
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-- 1101.00000000 = -1
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-- 1101.00000000 = -1
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-- Q
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-- Q
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-- o | o
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-- o | o
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-- 01 | 00
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-- 01 | 00
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-- |
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-- |
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-- ----------------- I
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-- ----------------- I
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-- |
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-- |
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-- 11 | 10
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-- 11 | 10
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-- o | o
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-- o | o
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case input is
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case input is
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when "00" =>
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when "00" =>
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Iout <= mais1;
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Iout <= mais1;
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Qout <= mais1;
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Qout <= mais1;
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when "01" =>
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when "01" =>
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Iout <= menos1;
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Iout <= menos1;
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Qout <= mais1;
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Qout <= mais1;
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when "10" =>
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when "10" =>
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Iout <= mais1;
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Iout <= mais1;
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Qout <= menos1;
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Qout <= menos1;
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when others =>
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when others =>
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Iout <= menos1;
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Iout <= menos1;
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Qout <= menos1;
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Qout <= menos1;
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end case;
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end case;
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end if;
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end if;
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end process;
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end process;
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end qam;
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end qam;
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