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[/] [ofdm/] [branches/] [avendor/] [vhdl/] [qamdecoder.vhd] - Diff between revs 2 and 13
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Rev 2 |
Rev 13 |
library IEEE;
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library IEEE;
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use IEEE.STD_LOGIC_1164.all;
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use IEEE.STD_LOGIC_1164.all;
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use IEEE.STD_LOGIC_ARITH.all;
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use IEEE.STD_LOGIC_ARITH.all;
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use IEEE.STD_LOGIC_SIGNED.all;
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use IEEE.STD_LOGIC_SIGNED.all;
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-- Uncomment the following lines to use the declarations that are
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-- Uncomment the following lines to use the declarations that are
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-- provided for instantiating Xilinx primitive components.
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-- provided for instantiating Xilinx primitive components.
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--library UNISIM;
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--library UNISIM;
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--use UNISIM.VComponents.all;
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--use UNISIM.VComponents.all;
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entity qamdecoder is
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entity qamdecoder is
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port (
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port (
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clk : in std_logic;
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clk : in std_logic;
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rst : in std_logic;
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rst : in std_logic;
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Iin : in std_logic;
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Iin : in std_logic;
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Qin : in std_logic;
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Qin : in std_logic;
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output : out std_logic_vector(1 downto 0));
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output : out std_logic_vector(1 downto 0));
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end qamdecoder;
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end qamdecoder;
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architecture qamdecoder of qamdecoder is
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architecture qamdecoder of qamdecoder is
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begin
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begin
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process(clk, rst)
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process(clk, rst)
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-- Q
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-- Q
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-- o | o
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-- o | o
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-- 01 | 00
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-- 01 | 00
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-- |
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-- |
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-- ----------------- I
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-- ----------------- I
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-- |
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-- |
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-- 11 | 10
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-- 11 | 10
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-- o | o
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-- o | o
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begin
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begin
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if rst = '1' then
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if rst = '1' then
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output <= (others => '0');
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output <= (others => '0');
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elsif clk'event and clk = '1' then
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elsif clk'event and clk = '1' then
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output <= Qin&Iin;
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output <= Qin&Iin;
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end if;
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end if;
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end process;
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end process;
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end qamdecoder;
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end qamdecoder;
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