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--
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--
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-- Title : rofactor
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-- Title : rofactor
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-- Design : cfft
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-- Design : cfft
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-- Author : ZHAO Ming
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-- Author : ZHAO Ming
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-- email : sradio@opencores.org
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-- email : sradio@opencores.org
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--
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--
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---------------------------------------------------------------------------------------------------
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---------------------------------------------------------------------------------------------------
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--
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--
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-- File : rofactor.vhd
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-- File : rofactor.vhd
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-- Generated : Thu Oct 3 00:12:16 2002
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-- Generated : Thu Oct 3 00:12:16 2002
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--
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--
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---------------------------------------------------------------------------------------------------
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---------------------------------------------------------------------------------------------------
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--
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--
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-- Description : Generate FFT rotation factor
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-- Description : Generate FFT rotation factor
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--
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--
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---------------------------------------------------------------------------------------------------
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---------------------------------------------------------------------------------------------------
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--
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--
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-- Revisions : 0
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-- Revisions : 0
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-- Revision Number : 1
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-- Revision Number : 1
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-- Version : 1.1.0
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-- Version : 1.1.0
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-- Date : Oct 17 2002
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-- Date : Oct 17 2002
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-- Modifier : ZHAO Ming
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-- Modifier : ZHAO Ming
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-- Desccription : Data width configurable
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-- Desccription : Data width configurable
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--
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--
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---------------------------------------------------------------------------------------------------
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---------------------------------------------------------------------------------------------------
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--
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--
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-- Revisions : 0
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-- Revisions : 0
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-- Revision Number : 2
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-- Revision Number : 2
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-- Version : 1.2.0
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-- Version : 1.2.0
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-- Date : Oct 18 2002
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-- Date : Oct 18 2002
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-- Modifier : ZHAO Ming
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-- Modifier : ZHAO Ming
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-- Desccription : Data width configurable
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-- Desccription : Data width configurable
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--
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--
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---------------------------------------------------------------------------------------------------
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library IEEE;
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library IEEE;
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use IEEE.STD_LOGIC_1164.all;
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use IEEE.STD_LOGIC_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_arith.all;
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--use ieee.std_logic_unsigned.all;
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--use ieee.std_logic_unsigned.all;
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--use ieee.std_logic_signed.all;
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--use ieee.std_logic_signed.all;
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entity rofactor is
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entity rofactor is
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generic (
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generic (
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POINT : Natural := 64;
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POINT : Natural := 64;
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STAGE : Natural := 3
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STAGE : Natural := 3
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);
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);
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port(
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port(
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clk : in STD_LOGIC;
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clk : in STD_LOGIC;
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rst : in STD_LOGIC;
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rst : in STD_LOGIC;
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start : in STD_LOGIC;
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start : in STD_LOGIC;
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invert : in std_logic;
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invert : in std_logic;
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-- step : in STD_LOGIC_VECTOR(2 downto 0);
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-- step : in STD_LOGIC_VECTOR(2 downto 0);
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angle : out STD_LOGIC_VECTOR(2*STAGE-1 downto 0)
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angle : out STD_LOGIC_VECTOR(2*STAGE-1 downto 0)
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);
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);
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end rofactor;
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end rofactor;
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architecture rofactor of rofactor is
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architecture rofactor of rofactor is
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signal counter : std_logic_vector( STAGE*2-1 downto 0 ):=( others=>'0' );
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signal counter : std_logic_vector( STAGE*2-1 downto 0 ):=( others=>'0' );
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signal inc,iinc,phase : std_logic_vector( STAGE*2-1 downto 0 ):=( others=>'0' );
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signal inc,iinc,phase : std_logic_vector( STAGE*2-1 downto 0 ):=( others=>'0' );
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signal mask : std_logic_vector( STAGE*2-1 downto 0 ):=( others=>'0' );
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signal mask : std_logic_vector( STAGE*2-1 downto 0 ):=( others=>'0' );
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signal comp : std_logic_vector( STAGE*2-1 downto 0 ):=( others=>'0' );
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signal comp : std_logic_vector( STAGE*2-1 downto 0 ):=( others=>'0' );
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begin
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begin
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angle<=phase;
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angle<=phase;
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count:process( clk,rst )
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count:process( clk,rst )
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begin
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begin
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if rst='1' then
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if rst='1' then
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counter<=( others=>'0' );
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counter<=( others=>'0' );
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inc<=( others=>'0' );
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inc<=( others=>'0' );
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mask<=( others=>'0' );
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mask<=( others=>'0' );
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elsif clk'event and clk='1' then
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elsif clk'event and clk='1' then
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if start='1' then
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if start='1' then
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counter<=( others=>'0' );
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counter<=( others=>'0' );
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mask<=( others=>'0' );
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mask<=( others=>'0' );
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-- state<="000";
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-- state<="000";
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if invert='1' then
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if invert='1' then
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inc<=CONV_STD_LOGIC_VECTOR(1,STAGE*2);
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inc<=CONV_STD_LOGIC_VECTOR(1,STAGE*2);
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else
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else
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inc<=CONV_STD_LOGIC_VECTOR(-1,STAGE*2);
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inc<=CONV_STD_LOGIC_VECTOR(-1,STAGE*2);
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end if;
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end if;
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else
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else
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counter<=unsigned(counter)+1;
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counter<=unsigned(counter)+1;
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if signed(counter)=-1 then
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if signed(counter)=-1 then
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inc<=inc(STAGE*2-3 downto 0 )&"00";
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inc<=inc(STAGE*2-3 downto 0 )&"00";
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mask<="11"&mask( STAGE*2-1 downto 2 );
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mask<="11"&mask( STAGE*2-1 downto 2 );
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-- if state/="100" then
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-- if state/="100" then
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-- state<=state+1;
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-- state<=state+1;
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-- end if;
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-- end if;
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end if;
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end if;
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end if;
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end if;
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end if;
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end if;
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end process count;
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end process count;
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output : process( clk, rst )
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output : process( clk, rst )
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begin
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begin
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if rst='1' then
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if rst='1' then
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phase<=( others=>'0' );
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phase<=( others=>'0' );
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iinc<=( others=>'0' );
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iinc<=( others=>'0' );
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elsif clk'event and clk='1' then
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elsif clk'event and clk='1' then
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if start='1' then
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if start='1' then
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iinc<=( others=>'0' );
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iinc<=( others=>'0' );
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phase<=( others=>'0' );
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phase<=( others=>'0' );
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else
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else
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if unsigned(counter( 1 downto 0 ))=3 then
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if unsigned(counter( 1 downto 0 ))=3 then
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phase<=( others=>'0' );
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phase<=( others=>'0' );
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else
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else
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phase<=unsigned(phase)+unsigned(iinc);
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phase<=unsigned(phase)+unsigned(iinc);
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end if;
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end if;
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-- if signed(counter or mask)=-1 then -- modified by Tonny Matos Siqueira
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-- if signed(counter or mask)=-1 then -- modified by Tonny Matos Siqueira
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if signed(comp)=-1 then
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if signed(comp)=-1 then
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iinc<=(others => '0');
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iinc<=(others => '0');
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elsif unsigned(counter( 1 downto 0 ))=3 then
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elsif unsigned(counter( 1 downto 0 ))=3 then
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iinc<=unsigned(iinc)+unsigned(inc);
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iinc<=unsigned(iinc)+unsigned(inc);
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end if;
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end if;
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end if;
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end if;
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end if;
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end if;
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end process output;
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end process output;
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comp <= counter or mask;
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comp <= counter or mask;
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end rofactor;
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end rofactor;
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