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https://opencores.org/ocsvn/ofdm/ofdm/trunk
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Rev 13 |
library IEEE;
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library IEEE;
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use IEEE.STD_LOGIC_1164.all;
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use IEEE.STD_LOGIC_1164.all;
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use IEEE.STD_LOGIC_ARITH.all;
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use IEEE.STD_LOGIC_ARITH.all;
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use IEEE.STD_LOGIC_UNSIGNED.all;
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use IEEE.STD_LOGIC_UNSIGNED.all;
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-- Uncomment the following lines to use the declarations that are
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-- Uncomment the following lines to use the declarations that are
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-- provided for instantiating Xilinx primitive components.
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-- provided for instantiating Xilinx primitive components.
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--library UNISIM;
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--library UNISIM;
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--use UNISIM.VComponents.all;
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--use UNISIM.VComponents.all;
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entity serial is
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entity serial is
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port (
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port (
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clk : in std_logic;
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clk : in std_logic;
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rst : in std_logic;
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rst : in std_logic;
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input : in std_logic_vector(1 downto 0);
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input : in std_logic_vector(1 downto 0);
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-- tbaux : out std_logic_vector(1 downto 0);
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-- tbaux : out std_logic_vector(1 downto 0);
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output : out std_logic);
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output : out std_logic);
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end serial;
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end serial;
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architecture serial of serial is
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architecture serial of serial is
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type states is (st0, st1);
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type states is (st0, st1);
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signal state : states;
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signal state : states;
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signal aux : std_logic_vector(1 downto 0);
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signal aux : std_logic_vector(1 downto 0);
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begin
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begin
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--tbaux <= aux;
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--tbaux <= aux;
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process(clk, rst)
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process(clk, rst)
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begin
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begin
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if rst = '1' then
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if rst = '1' then
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aux <= (others => '0');
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aux <= (others => '0');
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output <= '0';
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output <= '0';
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elsif clk'event and clk = '1' then
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elsif clk'event and clk = '1' then
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case state is
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case state is
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when st0 =>
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when st0 =>
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aux <= input;
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aux <= input;
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output <= aux(0);
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output <= aux(0);
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state <= st1;
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state <= st1;
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when st1 =>
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when st1 =>
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output <= aux(1);
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output <= aux(1);
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state <= st0;
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state <= st0;
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end case;
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end case;
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end if;
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end if;
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end process;
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end process;
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