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[/] [ofdm/] [branches/] [avendor/] [vhdl/] [serparser.vhd] - Diff between revs 2 and 13
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| Rev 2 |
Rev 13 |
library IEEE;
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library IEEE;
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use IEEE.STD_LOGIC_1164.all;
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use IEEE.STD_LOGIC_1164.all;
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use IEEE.STD_LOGIC_ARITH.all;
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use IEEE.STD_LOGIC_ARITH.all;
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use IEEE.STD_LOGIC_UNSIGNED.all;
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use IEEE.STD_LOGIC_UNSIGNED.all;
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-- Uncomment the following lines to use the declarations that are
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-- Uncomment the following lines to use the declarations that are
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-- provided for instantiating Xilinx primitive components.
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-- provided for instantiating Xilinx primitive components.
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--library UNISIM;
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--library UNISIM;
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--use UNISIM.VComponents.all;
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--use UNISIM.VComponents.all;
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entity serparser is
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entity serparser is
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port (
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port (
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clk : in std_logic;
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clk : in std_logic;
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rst : in std_logic;
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rst : in std_logic;
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a : in std_logic;
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a : in std_logic;
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b : out std_logic);
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b : out std_logic);
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end serparser;
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end serparser;
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architecture serparser of serparser is
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architecture serparser of serparser is
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component parallel
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component parallel
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port (
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port (
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clk : in std_logic;
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clk : in std_logic;
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rst : in std_logic;
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rst : in std_logic;
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input : in std_logic;
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input : in std_logic;
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output : out std_logic_vector(1 downto 0));
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output : out std_logic_vector(1 downto 0));
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end component;
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end component;
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component serial
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component serial
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port (
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port (
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clk : in std_logic;
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clk : in std_logic;
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rst : in std_logic;
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rst : in std_logic;
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input : in std_logic_vector(1 downto 0);
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input : in std_logic_vector(1 downto 0);
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output : out std_logic);
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output : out std_logic);
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end component;
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end component;
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signal aux : std_logic_vector(1 downto 0);
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signal aux : std_logic_vector(1 downto 0);
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begin
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begin
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parallel_1 : parallel
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parallel_1 : parallel
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port map (
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port map (
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clk => clk,
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clk => clk,
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rst => rst,
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rst => rst,
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input => a,
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input => a,
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output => aux);
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output => aux);
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serial_1 : serial
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serial_1 : serial
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port map (
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port map (
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clk => clk,
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clk => clk,
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rst => rst,
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rst => rst,
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input => aux,
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input => aux,
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output => b);
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output => b);
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end serparser;
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end serparser;
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