URL
https://opencores.org/ocsvn/ofdm/ofdm/trunk
[/] [ofdm/] [branches/] [avendor/] [vhdl/] [startup_timer.vhd] - Diff between revs 2 and 13
Only display areas with differences |
Details |
Blame |
View Log
| Rev 2 |
Rev 13 |
library IEEE;
|
library IEEE;
|
use IEEE.STD_LOGIC_1164.ALL;
|
use IEEE.STD_LOGIC_1164.ALL;
|
use IEEE.STD_LOGIC_ARITH.ALL;
|
use IEEE.STD_LOGIC_ARITH.ALL;
|
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
|
|
-- Uncomment the following lines to use the declarations that are
|
-- Uncomment the following lines to use the declarations that are
|
-- provided for instantiating Xilinx primitive components.
|
-- provided for instantiating Xilinx primitive components.
|
--library UNISIM;
|
--library UNISIM;
|
--use UNISIM.VComponents.all;
|
--use UNISIM.VComponents.all;
|
|
|
entity startup_timer is
|
entity startup_timer is
|
Port ( clk : in std_logic;
|
Port ( clk : in std_logic;
|
rst : in std_logic;
|
rst : in std_logic;
|
startup : out std_logic);
|
startup : out std_logic);
|
end startup_timer;
|
end startup_timer;
|
|
|
architecture startup_timer of startup_timer is
|
architecture startup_timer of startup_timer is
|
|
|
signal timer: integer range 0 to 3;
|
signal timer: integer range 0 to 3;
|
begin
|
begin
|
|
|
process (clk, rst)
|
process (clk, rst)
|
begin
|
begin
|
if rst = '1' then
|
if rst = '1' then
|
timer <= 0;
|
timer <= 0;
|
startup <= '1';
|
startup <= '1';
|
elsif clk'event and clk='1' then
|
elsif clk'event and clk='1' then
|
if timer /= 3 then
|
if timer /= 3 then
|
timer <= timer +1;
|
timer <= timer +1;
|
else
|
else
|
startup <='0';
|
startup <='0';
|
timer <= timer;
|
timer <= timer;
|
end if;
|
end if;
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
end startup_timer;
|
end startup_timer;
|
|
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.