library IEEE;
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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-- Uncomment the following lines to use the declarations that are
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-- Uncomment the following lines to use the declarations that are
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-- provided for instantiating Xilinx primitive components.
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-- provided for instantiating Xilinx primitive components.
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--library UNISIM;
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--library UNISIM;
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--use UNISIM.VComponents.all;
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--use UNISIM.VComponents.all;
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entity tx_control is
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entity tx_control is
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generic (
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generic (
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WIDTH : natural := 12;
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WIDTH : natural := 12;
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POINT : natural := 64;
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POINT : natural := 64;
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STAGE : natural := 3);
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STAGE : natural := 3);
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port (
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port (
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clk : in std_logic;
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clk : in std_logic;
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rst : in std_logic;
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rst : in std_logic;
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mem_ready : out std_logic;
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mem_ready : out std_logic;
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mem_block : in std_logic;
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mem_block : in std_logic;
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Output_enable : in std_logic;
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Output_enable : in std_logic;
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bank0_busy : in std_logic;
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bank0_busy : in std_logic;
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bank1_busy : in std_logic;
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bank1_busy : in std_logic;
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wen_in : out std_logic;
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wen_in : out std_logic;
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addrin_in : out std_logic_vector(2*stage-1 downto 0);
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addrin_in : out std_logic_vector(2*stage-1 downto 0);
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addrout_out : out std_logic_vector(2*stage-1 downto 0));
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addrout_out : out std_logic_vector(2*stage-1 downto 0));
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end tx_control;
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end tx_control;
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architecture tx_control of tx_control is
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architecture tx_control of tx_control is
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signal cont: std_logic_vector(2*stage-2 downto 0);
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signal cont: std_logic_vector(2*stage-2 downto 0);
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begin
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begin
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process (clk, rst)
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process (clk, rst)
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begin
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begin
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if rst ='1' then
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if rst ='1' then
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cont <= (others => '0');
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cont <= (others => '0');
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elsif clk'event and clk='1' then
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elsif clk'event and clk='1' then
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if unsigned(cont) /= 32 then
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if unsigned(cont) /= 32 then
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cont <= cont+1;
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cont <= cont+1;
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else
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else
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cont <= x'1';
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cont <= x'1';
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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end tx_control;
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end tx_control;
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