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https://opencores.org/ocsvn/ofdm/ofdm/trunk
[/] [ofdm/] [trunk/] [vhdl/] [starts.vhd] - Diff between revs 3 and 13
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| Rev 3 |
Rev 13 |
library IEEE;
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library IEEE;
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use IEEE.STD_LOGIC_1164.all;
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use IEEE.STD_LOGIC_1164.all;
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use IEEE.STD_LOGIC_ARITH.all;
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use IEEE.STD_LOGIC_ARITH.all;
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use IEEE.STD_LOGIC_SIGNED.all;
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use IEEE.STD_LOGIC_SIGNED.all;
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entity starts is
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entity starts is
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generic (
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generic (
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stage : natural);
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stage : natural);
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port (
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port (
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clk : in std_logic;
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clk : in std_logic;
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rst : in std_logic;
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rst : in std_logic;
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Gen_state : in std_logic_vector(2*stage+2 downto 0);
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Gen_state : in std_logic_vector(2*stage+2 downto 0);
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factorstart : out std_logic;
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factorstart : out std_logic;
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cfft4start : out std_logic);
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cfft4start : out std_logic);
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end starts;
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end starts;
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architecture starts of starts is
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architecture starts of starts is
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alias state : std_logic_vector(2 downto 0) is Gen_state(2*stage+2 downto 2*stage);
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alias state : std_logic_vector(2 downto 0) is Gen_state(2*stage+2 downto 2*stage);
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alias counter : std_logic_vector(2*stage-1 downto 0) is Gen_state(2*stage-1 downto 0);
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alias counter : std_logic_vector(2*stage-1 downto 0) is Gen_state(2*stage-1 downto 0);
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begin
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begin
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process( clk, rst )
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process( clk, rst )
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begin
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begin
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if rst = '1' then
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if rst = '1' then
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factorstart <= '0';
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factorstart <= '0';
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cfft4start <= '0';
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cfft4start <= '0';
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elsif clk'event and clk = '1' then
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elsif clk'event and clk = '1' then
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if unsigned(state) = 0 and unsigned(counter) = 2 then
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if unsigned(state) = 0 and unsigned(counter) = 2 then
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cfft4start <= '1';
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cfft4start <= '1';
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else
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else
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cfft4start <= '0';
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cfft4start <= '0';
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end if;
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end if;
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if unsigned(state) = 0 and unsigned(counter) = 8 then
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if unsigned(state) = 0 and unsigned(counter) = 8 then
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factorstart <= '1';
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factorstart <= '1';
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else
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else
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factorstart <= '0';
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factorstart <= '0';
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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end starts;
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end starts;
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