//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// OMS 8051 cores UART Interface Module ////
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//// OMS 8051 cores UART Interface Module ////
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//// ////
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//// ////
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//// This file is part of the OMS 8051 cores project ////
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//// This file is part of the OMS 8051 cores project ////
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//// http://www.opencores.org/cores/oms8051mini/ ////
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//// http://www.opencores.org/cores/oms8051mini/ ////
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//// ////
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//// ////
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//// Description ////
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//// Description ////
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//// OMS 8051 definitions. ////
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//// OMS 8051 definitions. ////
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//// ////
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//// ////
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//// To Do: ////
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//// To Do: ////
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//// nothing ////
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//// nothing ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// - Dinesh Annayya, dinesha@opencores.org ////
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//// - Dinesh Annayya, dinesha@opencores.org ////
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//// ////
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//// ////
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//// Revision : ////
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//////////////////////////////////////////////////////////////////////
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//// v-0.0 : NOV 26, 2016 ////
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//// Revision :
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//// 1. initial version picked from ////
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//// v-0.0 : NOV 26, 2016
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//// http://www.opencores.org/cores/turbo8051/ ////
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//// 1. initial version picked from
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//// v-0.1 : NOV 28, 2016 ////
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//// http://www.opencores.org/cores/turbo8051/
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//// 2. Register access correction ////
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//// v-0.1 : NOV 28, 2016
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//// ////
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//// 1. Register access correction
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//// v-0.2 : NOV 28, 2016
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//// 1. Register access changed from 32 bit to 8bit
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////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// later version. ////
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//// ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// details. ////
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//// ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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module uart_core
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module uart_core
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(
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(
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app_reset_n ,
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app_reset_n ,
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app_clk ,
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app_clk ,
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// Reg Bus Interface Signal
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// Reg Bus Interface Signal
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reg_cs,
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reg_cs,
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reg_wr,
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reg_wr,
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reg_addr,
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reg_addr,
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reg_wdata,
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reg_wdata,
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reg_be,
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reg_be,
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// Outputs
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// Outputs
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reg_rdata,
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reg_rdata,
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reg_ack,
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reg_ack,
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// Line Interface
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// Line Interface
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si,
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si,
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so
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so
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);
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);
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parameter W = 8'd8;
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parameter W = 8'd8;
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parameter DP = 8'd16;
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parameter DP = 8'd16;
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parameter AW = (DP == 2) ? 1 :
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parameter AW = (DP == 2) ? 1 :
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(DP == 4) ? 2 :
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(DP == 4) ? 2 :
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(DP == 8) ? 3 :
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(DP == 8) ? 3 :
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(DP == 16) ? 4 :
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(DP == 16) ? 4 :
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(DP == 32) ? 5 :
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(DP == 32) ? 5 :
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(DP == 64) ? 6 :
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(DP == 64) ? 6 :
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(DP == 128) ? 7 :
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(DP == 128) ? 7 :
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(DP == 256) ? 8 : 0;
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(DP == 256) ? 8 : 0;
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input app_reset_n ; // application reset
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input app_reset_n ; // application reset
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input app_clk ; // application clock
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input app_clk ; // application clock
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//---------------------------------
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//---------------------------------
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// Reg Bus Interface Signal
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// Reg Bus Interface Signal
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//---------------------------------
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//---------------------------------
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input reg_cs ;
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input reg_cs ;
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input reg_wr ;
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input reg_wr ;
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input [3:0] reg_addr ;
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input [3:0] reg_addr ;
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input [31:0] reg_wdata ;
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input [7:0] reg_wdata ;
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input [3:0] reg_be ;
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input reg_be ;
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// Outputs
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// Outputs
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output [31:0] reg_rdata ;
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output [7:0] reg_rdata ;
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output reg_ack ;
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output reg_ack ;
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// Line Interface
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// Line Interface
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input si ; // uart si
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input si ; // uart si
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output so ; // uart so
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output so ; // uart so
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// Wire Declaration
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// Wire Declaration
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wire [W-1: 0] tx_fifo_rd_data;
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wire [W-1: 0] tx_fifo_rd_data;
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wire [W-1: 0] rx_fifo_wr_data;
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wire [W-1: 0] rx_fifo_wr_data;
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wire [W-1: 0] app_rxfifo_data;
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wire [W-1: 0] app_rxfifo_data;
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wire [W-1: 0] app_txfifo_data;
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wire [W-1: 0] app_txfifo_data;
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wire [1 : 0] error_ind;
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wire [1 : 0] error_ind;
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// Wire
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// Wire
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wire cfg_tx_enable ; // Tx Enable
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wire cfg_tx_enable ; // Tx Enable
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wire cfg_rx_enable ; // Rx Enable
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wire cfg_rx_enable ; // Rx Enable
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wire cfg_stop_bit ; // 0 -> 1 Stop, 1 -> 2 Stop
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wire cfg_stop_bit ; // 0 -> 1 Stop, 1 -> 2 Stop
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wire [1:0] cfg_pri_mod ; // priority mode, 0 -> nop, 1 -> Even, 2 -> Odd
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wire [1:0] cfg_pri_mod ; // priority mode, 0 -> nop, 1 -> Even, 2 -> Odd
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wire frm_error_o ; // framing error
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wire frm_error_o ; // framing error
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wire par_error_o ; // par error
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wire par_error_o ; // par error
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wire rx_fifo_full_err_o ; // rx fifo full error
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wire rx_fifo_full_err_o ; // rx fifo full error
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wire [11:0] cfg_baud_16x ; // 16x Baud clock generation
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wire [11:0] cfg_baud_16x ; // 16x Baud clock generation
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wire rx_fifo_wr_full ;
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wire rx_fifo_wr_full ;
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wire app_rxfifo_empty ;
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wire app_rxfifo_empty ;
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uart_cfg u_cfg (
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uart_cfg u_cfg (
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. mclk (app_clk),
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. mclk (app_clk),
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. reset_n (app_reset_n),
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. reset_n (app_reset_n),
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// Reg Bus Interface Signal
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// Reg Bus Interface Signal
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. reg_cs (reg_cs),
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. reg_cs (reg_cs),
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. reg_wr (reg_wr),
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. reg_wr (reg_wr),
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. reg_addr (reg_addr),
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. reg_addr (reg_addr),
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. reg_wdata (reg_wdata),
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. reg_wdata (reg_wdata),
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. reg_be (reg_be),
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. reg_be (reg_be),
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// Outputs
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// Outputs
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. reg_rdata (reg_rdata),
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. reg_rdata (reg_rdata),
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. reg_ack (reg_ack),
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. reg_ack (reg_ack),
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// configuration
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// configuration
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. cfg_tx_enable (cfg_tx_enable),
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. cfg_tx_enable (cfg_tx_enable),
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. cfg_rx_enable (cfg_rx_enable),
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. cfg_rx_enable (cfg_rx_enable),
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. cfg_stop_bit (cfg_stop_bit),
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. cfg_stop_bit (cfg_stop_bit),
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. cfg_pri_mod (cfg_pri_mod),
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. cfg_pri_mod (cfg_pri_mod),
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. cfg_baud_16x (cfg_baud_16x),
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. cfg_baud_16x (cfg_baud_16x),
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. tx_fifo_full (app_tx_fifo_full),
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. tx_fifo_full (app_tx_fifo_full),
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. tx_fifo_wr_en (tx_fifo_wr_en),
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. tx_fifo_wr_en (tx_fifo_wr_en),
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. tx_fifo_data (app_txfifo_data),
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. tx_fifo_data (app_txfifo_data),
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. rx_fifo_empty (app_rxfifo_empty),
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. rx_fifo_empty (app_rxfifo_empty),
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. rx_fifo_rd_en (app_rxfifo_rd_en),
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. rx_fifo_rd_en (app_rxfifo_rd_en),
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. rx_fifo_data (app_rxfifo_data) ,
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. rx_fifo_data (app_rxfifo_data) ,
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. frm_error_o (frm_error_o),
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. frm_error_o (frm_error_o),
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. par_error_o (par_error_o),
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. par_error_o (par_error_o),
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. rx_fifo_full_err_o (rx_fifo_full_err_o)
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. rx_fifo_full_err_o (rx_fifo_full_err_o)
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);
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);
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// 16x Baud clock generation
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// 16x Baud clock generation
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// Example: to generate 19200 Baud clock from 50Mhz Link clock
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// Example: to generate 19200 Baud clock from 50Mhz Link clock
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// 50 * 1000 * 1000 / (2 + cfg_baud_16x) = 19200 * 16
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// 50 * 1000 * 1000 / (2 + cfg_baud_16x) = 19200 * 16
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// cfg_baud_16x = 0xA0 (160)
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// cfg_baud_16x = 0xA0 (160)
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wire line_clk_16x;
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wire line_clk_16x;
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clk_ctl #(11) u_clk_ctl (
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clk_ctl #(11) u_clk_ctl (
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// Outputs
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// Outputs
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.clk_o (line_clk_16x),
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.clk_o (line_clk_16x),
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// Inputs
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// Inputs
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.mclk (app_clk),
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.mclk (app_clk),
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.reset_n (app_reset_n),
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.reset_n (app_reset_n),
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.clk_div_ratio (cfg_baud_16x)
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.clk_div_ratio (cfg_baud_16x)
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);
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);
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wire line_reset_n = app_reset_n; // todo-> create synchronised reset w.r.t line clock
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wire line_reset_n = app_reset_n; // todo-> create synchronised reset w.r.t line clock
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uart_txfsm u_txfsm (
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uart_txfsm u_txfsm (
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. reset_n ( line_reset_n ),
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. reset_n ( line_reset_n ),
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. baud_clk_16x ( line_clk_16x ),
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. baud_clk_16x ( line_clk_16x ),
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. cfg_tx_enable ( cfg_tx_enable ),
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. cfg_tx_enable ( cfg_tx_enable ),
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. cfg_stop_bit ( cfg_stop_bit ),
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. cfg_stop_bit ( cfg_stop_bit ),
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. cfg_pri_mod ( cfg_pri_mod ),
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. cfg_pri_mod ( cfg_pri_mod ),
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// FIFO control signal
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// FIFO control signal
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. fifo_empty ( tx_fifo_rd_empty ),
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. fifo_empty ( tx_fifo_rd_empty ),
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. fifo_rd ( tx_fifo_rd ),
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. fifo_rd ( tx_fifo_rd ),
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. fifo_data ( tx_fifo_rd_data ),
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. fifo_data ( tx_fifo_rd_data ),
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// Line Interface
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// Line Interface
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. so ( so )
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. so ( so )
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);
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);
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uart_rxfsm u_rxfsm (
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uart_rxfsm u_rxfsm (
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. reset_n ( line_reset_n ),
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. reset_n ( line_reset_n ),
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. baud_clk_16x ( line_clk_16x ) ,
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. baud_clk_16x ( line_clk_16x ) ,
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. cfg_rx_enable ( cfg_rx_enable ),
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. cfg_rx_enable ( cfg_rx_enable ),
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. cfg_stop_bit ( cfg_stop_bit ),
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. cfg_stop_bit ( cfg_stop_bit ),
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. cfg_pri_mod ( cfg_pri_mod ),
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. cfg_pri_mod ( cfg_pri_mod ),
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. error_ind ( error_ind ),
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. error_ind ( error_ind ),
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// FIFO control signal
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// FIFO control signal
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. fifo_aval ( !rx_fifo_wr_full ),
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. fifo_aval ( !rx_fifo_wr_full ),
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. fifo_wr ( rx_fifo_wr ),
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. fifo_wr ( rx_fifo_wr ),
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. fifo_data ( rx_fifo_wr_data ),
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. fifo_data ( rx_fifo_wr_data ),
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// Line Interface
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// Line Interface
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. si (si_ss )
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. si (si_ss )
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);
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);
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async_fifo #(W,DP,0,0) u_rxfifo (
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async_fifo #(W,DP,0,0) u_rxfifo (
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.wr_clk (line_clk_16x ),
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.wr_clk (line_clk_16x ),
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.wr_reset_n (line_reset_n ),
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.wr_reset_n (line_reset_n ),
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.wr_en (rx_fifo_wr ),
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.wr_en (rx_fifo_wr ),
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.wr_data (rx_fifo_wr_data ),
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.wr_data (rx_fifo_wr_data ),
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.full (rx_fifo_wr_full ), // sync'ed to wr_clk
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.full (rx_fifo_wr_full ), // sync'ed to wr_clk
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.wr_total_free_space( ),
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.wr_total_free_space( ),
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.rd_clk (app_clk ),
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.rd_clk (app_clk ),
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.rd_reset_n (app_reset_n ),
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.rd_reset_n (app_reset_n ),
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.rd_en (app_rxfifo_rd_en ),
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.rd_en (app_rxfifo_rd_en ),
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.empty (app_rxfifo_empty ), // sync'ed to rd_clk
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.empty (app_rxfifo_empty ), // sync'ed to rd_clk
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.rd_total_aval ( ),
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.rd_total_aval ( ),
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.rd_data (app_rxfifo_data )
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.rd_data (app_rxfifo_data )
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);
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);
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async_fifo #(W,DP,0,0) u_txfifo (
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async_fifo #(W,DP,0,0) u_txfifo (
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.wr_clk (app_clk ),
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.wr_clk (app_clk ),
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.wr_reset_n (app_reset_n ),
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.wr_reset_n (app_reset_n ),
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.wr_en (tx_fifo_wr_en ),
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.wr_en (tx_fifo_wr_en ),
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.wr_data (app_txfifo_data ),
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.wr_data (app_txfifo_data ),
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.full (app_tx_fifo_full ), // sync'ed to wr_clk
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.full (app_tx_fifo_full ), // sync'ed to wr_clk
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.wr_total_free_space( ),
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.wr_total_free_space( ),
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.rd_clk (line_clk_16x ),
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.rd_clk (line_clk_16x ),
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.rd_reset_n (line_reset_n ),
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.rd_reset_n (line_reset_n ),
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.rd_en (tx_fifo_rd ),
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.rd_en (tx_fifo_rd ),
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.empty (tx_fifo_rd_empty ), // sync'ed to rd_clk
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.empty (tx_fifo_rd_empty ), // sync'ed to rd_clk
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.rd_total_aval ( ),
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.rd_total_aval ( ),
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.rd_data (tx_fifo_rd_data )
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.rd_data (tx_fifo_rd_data )
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);
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);
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double_sync_low u_si_sync (
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double_sync_low u_si_sync (
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. in_data ( si ),
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. in_data ( si ),
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. out_clk (line_clk_16x ),
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. out_clk (line_clk_16x ),
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. out_rst_n (line_reset_n ),
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. out_rst_n (line_reset_n ),
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. out_data (si_ss )
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. out_data (si_ss )
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);
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);
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|
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wire frm_error = (error_ind == 2'b01);
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wire frm_error = (error_ind == 2'b01);
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wire par_error = (error_ind == 2'b10);
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wire par_error = (error_ind == 2'b10);
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wire rx_fifo_full_err = (error_ind == 2'b11);
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wire rx_fifo_full_err = (error_ind == 2'b11);
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double_sync_low u_frm_err (
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double_sync_low u_frm_err (
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. in_data ( frm_error ),
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. in_data ( frm_error ),
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. out_clk ( app_clk ),
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. out_clk ( app_clk ),
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. out_rst_n ( app_reset_n ),
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. out_rst_n ( app_reset_n ),
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. out_data ( frm_error_o )
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. out_data ( frm_error_o )
|
);
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);
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double_sync_low u_par_err (
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double_sync_low u_par_err (
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. in_data ( par_error ),
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. in_data ( par_error ),
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. out_clk ( app_clk ),
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. out_clk ( app_clk ),
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. out_rst_n ( app_reset_n ),
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. out_rst_n ( app_reset_n ),
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. out_data ( par_error_o )
|
. out_data ( par_error_o )
|
);
|
);
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|
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double_sync_low u_rxfifo_err (
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double_sync_low u_rxfifo_err (
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. in_data ( rx_fifo_full_err ),
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. in_data ( rx_fifo_full_err ),
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. out_clk ( app_clk ),
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. out_clk ( app_clk ),
|
. out_rst_n ( app_reset_n ),
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. out_rst_n ( app_reset_n ),
|
. out_data ( rx_fifo_full_err_o )
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. out_data ( rx_fifo_full_err_o )
|
);
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);
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|
|
|
|
endmodule
|
endmodule
|
|
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