//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// 8051 external data ram ////
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//// OMS 8051 Digital core Module ////
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//// ////
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//// ////
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//// This file is part of the 8051 cores project ////
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//// This file is part of the OMS 8051 cores project ////
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//// http://www.opencores.org/cores/8051/ ////
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//// http://www.opencores.org/cores/oms8051mini/ ////
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//// ////
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//// ////
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//// Description ////
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//// Description ////
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//// external data ram ////
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//// 64K * 8 external data ram ////
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//// ////
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//// ////
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//// To Do: ////
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//// To Do: ////
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//// nothing ////
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//// nothing ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// - Simon Teran, simont@opencores.org ////
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//// - Simon Teran, simont@opencores.org ////
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//// - Dinesh Annayya, dinesha@opencores.org ////
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//// Revision : Nov 26, 2016 ////
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//////////////////////////////////////////////////////////////////////
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// v0.0 - Dinesh A, 8th Dec 2016,
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// 1. converted to 8bit RAM Mode
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// later version. ////
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//// ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// details. ////
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//// ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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// CVS Revision History
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//
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// $Log: not supported by cvs2svn $
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// Revision 1.4 2002/10/17 18:53:04 simont
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// added parameter DELAY
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//
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// Revision 1.3 2002/09/30 17:34:01 simont
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// prepared header
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//
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//
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module oc8051_xram (clk, rst, wr, be, addr, data_in, data_out, ack, stb);
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module oc8051_xram (clk, rst, wr, addr, data_in, data_out, ack, stb);
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//
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//
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// external data ram for simulation. part of oc8051_tb
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// external data ram for simulation. part of oc8051_tb
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// it's tehnology dependent
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// it's tehnology dependent
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//
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//
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// clk (in) clock
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// clk (in) clock
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// addr (in) addres
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// addr (in) addres
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// data_in (out) data input
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// data_in (out) data input
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// data_out (in) data output
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// data_out (in) data output
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// wr (in) write
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// wr (in) write
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// ack (out) acknowlage
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// ack (out) acknowlage
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// stb (in) strobe
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// stb (in) strobe
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//
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//
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parameter DELAY=1;
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parameter DELAY=1;
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input clk, wr, stb, rst;
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input clk, wr, stb, rst;
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input [3:0] be; // byte enable
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input [7:0] data_in;
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input [31:0] data_in;
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input [15:0] addr;
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input [15:0] addr;
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output [31:0] data_out;
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output [7:0] data_out;
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output ack;
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output ack;
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reg ackw, ackr;
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reg ackw, ackr;
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reg [31:0] data_out;
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reg [7:0] data_out;
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reg [2:0] cnt;
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reg [2:0] cnt;
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integer i;
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integer i;
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//
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//
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// buffer
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// buffer
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reg [7:0] buff [65535:0]; //64kb
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reg [7:0] buff [65535:0]; //64kb
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//reg [7:0] buff [8388607:0]; //8Mb
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//reg [7:0] buff [8388607:0]; //8Mb
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assign ack = ackw || ackr;
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assign ack = ackw || ackr;
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// Intialise the memory
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// Intialise the memory
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initial
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initial
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begin
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begin
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for (i=0; i<65536; i=i+1)
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for (i=0; i<65536; i=i+1)
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buff [i] = 8'h00;
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buff [i] = 8'h00;
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end
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end
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//
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//
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// writing to ram
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// writing to ram
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always @(posedge clk or posedge rst)
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always @(posedge clk or posedge rst)
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begin
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begin
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if (rst)
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if (rst)
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ackw <= #1 1'b0;
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ackw <= #1 1'b0;
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else if (wr && stb && ((DELAY==3'b000) || (cnt==3'b000))) begin
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else if (wr && stb && ((DELAY==3'b000) || (cnt==3'b000))) begin
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if(be[0]) buff[addr] <= #1 data_in[7:0];
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buff[addr] <= #1 data_in[7:0];
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if(be[1]) buff[addr+1] <= #1 data_in[15:8];
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if(be[2]) buff[addr+2] <= #1 data_in[23:16];
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if(be[3]) buff[addr+3] <= #1 data_in[31:24];
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ackw <= #1 1'b1;
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ackw <= #1 1'b1;
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end else ackw <= #1 1'b0;
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end else ackw <= #1 1'b0;
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end
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end
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always @(posedge clk or posedge rst)
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always @(posedge clk or posedge rst)
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if (rst)
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if (rst)
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ackr <= #1 1'b0;
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ackr <= #1 1'b0;
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else if (stb && !wr && ((DELAY==3'b000) || (cnt==3'b000))) begin
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else if (stb && !wr && ((DELAY==3'b000) || (cnt==3'b000))) begin
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data_out <= #1 {buff[addr+3], buff[addr+2], buff[addr+1], buff [addr]};
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data_out <= #1 buff [addr];
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ackr <= #1 1'b1;
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ackr <= #1 1'b1;
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end else begin
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end else begin
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ackr <= #1 1'b0;
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ackr <= #1 1'b0;
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data_out <= #1 8'h00;
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data_out <= #1 8'h00;
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end
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end
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always @(posedge clk or posedge rst)
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always @(posedge clk or posedge rst)
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begin
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begin
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if (rst)
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if (rst)
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cnt <= #1 DELAY;
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cnt <= #1 DELAY;
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else if (cnt==3'b000)
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else if (cnt==3'b000)
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cnt <= #1 DELAY;
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cnt <= #1 DELAY;
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else if (stb)
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else if (stb)
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cnt <= #1 cnt - 3'b001;
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cnt <= #1 cnt - 3'b001;
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else cnt <= #1 DELAY;
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else cnt <= #1 DELAY;
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end
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end
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endmodule
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endmodule
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