#--
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#--
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#-- opb_usblite - opb_uartlite replacement
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#-- opb_usblite - opb_uartlite replacement
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#--
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#--
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#-- opb_usblite is using components from Rudolf Usselmann see
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#-- opb_usblite is using components from Rudolf Usselmann see
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#-- http://www.opencores.org/cores/usb_phy/
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#-- http://www.opencores.org/cores/usb_phy/
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#-- and Joris van Rantwijk see http://www.xs4all.nl/~rjoris/fpga/usb.html
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#-- and Joris van Rantwijk see http://www.xs4all.nl/~rjoris/fpga/usb.html
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#--
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#--
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#-- Copyright (C) 2010 Ake Rehnman
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#-- Copyright (C) 2010 Ake Rehnman
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#--
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#--
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#-- This program is free software: you can redistribute it and/or modify
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#-- This program is free software: you can redistribute it and/or modify
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#-- it under the terms of the GNU General Public License as published by
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#-- it under the terms of the GNU Lesser General Public License as published by
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#-- the Free Software Foundation, either version 3 of the License, or
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#-- the Free Software Foundation, either version 3 of the License, or
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#-- (at your option) any later version.
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#-- (at your option) any later version.
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#--
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#--
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#-- This program is distributed in the hope that it will be useful,
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#-- This program is distributed in the hope that it will be useful,
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#-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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#-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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#-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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#-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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#-- GNU General Public License for more details.
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#-- GNU Lesser General Public License for more details.
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#--
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#--
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#-- You should have received a copy of the GNU General Public License
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#-- You should have received a copy of the GNU Lesser General Public License
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#-- along with this program. If not, see .
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#-- along with this program. If not, see .
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#--
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#--
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BEGIN opb_usblite
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BEGIN opb_usblite
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## Peripheral Options
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## Peripheral Options
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OPTION IPTYPE = PERIPHERAL
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OPTION IPTYPE = PERIPHERAL
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OPTION IMP_NETLIST = TRUE
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OPTION IMP_NETLIST = TRUE
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OPTION HDL = VHDL
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OPTION HDL = VHDL
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OPTION IP_GROUP = MICROBLAZE:PPC:USER
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OPTION IP_GROUP = MICROBLAZE:PPC:USER
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## Bus Interfaces
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## Bus Interfaces
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BUS_INTERFACE BUS = SOPB, BUS_STD = OPB, BUS_TYPE = SLAVE
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BUS_INTERFACE BUS = SOPB, BUS_STD = OPB, BUS_TYPE = SLAVE
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## Generics for VHDL or Parameters for Verilog
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## Generics for VHDL or Parameters for Verilog
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PARAMETER C_OPB_AWIDTH = 32, DT = INTEGER, BUS = SOPB
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PARAMETER C_OPB_AWIDTH = 32, DT = INTEGER, BUS = SOPB
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PARAMETER C_OPB_DWIDTH = 32, DT = INTEGER, BUS = SOPB
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PARAMETER C_OPB_DWIDTH = 32, DT = INTEGER, BUS = SOPB
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PARAMETER C_BASEADDR = 0xffff0000, DT = std_logic_vector(0 to 31), PAIR = C_HIGHADDR, ADDRESS = BASE, BUS = SOPB
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PARAMETER C_BASEADDR = 0xffff0000, DT = std_logic_vector(0 to 31), PAIR = C_HIGHADDR, ADDRESS = BASE, BUS = SOPB
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PARAMETER C_HIGHADDR = 0xffff00ff, DT = std_logic_vector, PAIR = C_BASEADDR, ADDRESS = HIGH, BUS = SOPB
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PARAMETER C_HIGHADDR = 0xffff00ff, DT = std_logic_vector, PAIR = C_BASEADDR, ADDRESS = HIGH, BUS = SOPB
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PARAMETER C_SYSRST = 1, DT = std_logic
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PARAMETER C_SYSRST = 1, DT = std_logic
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PARAMETER C_PHYMODE = 1, DT = std_logic
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PARAMETER C_PHYMODE = 1, DT = std_logic
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PARAMETER C_VENDORID = 0x1234, DT = std_logic_vector(15 downto 0)
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PARAMETER C_VENDORID = 0x1234, DT = std_logic_vector(15 downto 0)
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PARAMETER C_PRODUCTID = 0x5678, DT = std_logic_vector(15 downto 0)
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PARAMETER C_PRODUCTID = 0x5678, DT = std_logic_vector(15 downto 0)
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PARAMETER C_VERSIONBCD = 0x0200, DT = std_logic_vector(15 downto 0)
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PARAMETER C_VERSIONBCD = 0x0200, DT = std_logic_vector(15 downto 0)
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PARAMETER C_SELFPOWERED = false, DT = BOOLEAN
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PARAMETER C_SELFPOWERED = false, DT = BOOLEAN
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PARAMETER C_RXBUFSIZE_BITS = 10, DT = INTEGER
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PARAMETER C_RXBUFSIZE_BITS = 10, DT = INTEGER
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PARAMETER C_TXBUFSIZE_BITS = 10, DT = INTEGER
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PARAMETER C_TXBUFSIZE_BITS = 10, DT = INTEGER
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## Ports
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## Ports
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PORT OPB_Clk = "", DIR = I, SIGIS = CLK, BUS = SOPB
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PORT OPB_Clk = "", DIR = I, SIGIS = CLK, BUS = SOPB
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PORT OPB_Rst = OPB_Rst, DIR = I, SIGIS = RST, BUS = SOPB
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PORT OPB_Rst = OPB_Rst, DIR = I, SIGIS = RST, BUS = SOPB
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PORT SYS_Rst = "", DIR = I, SIGIS = RST
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PORT SYS_Rst = "", DIR = I, SIGIS = RST
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PORT USB_Clk = "", DIR = I, SIGIS = CLK
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PORT USB_Clk = "", DIR = I, SIGIS = CLK
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PORT OPB_ABus = OPB_ABus, DIR = I, VEC = [0:31], BUS = SOPB
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PORT OPB_ABus = OPB_ABus, DIR = I, VEC = [0:31], BUS = SOPB
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PORT OPB_BE = OPB_BE, DIR = I, VEC = [0:3], BUS = SOPB
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PORT OPB_BE = OPB_BE, DIR = I, VEC = [0:3], BUS = SOPB
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PORT OPB_RNW = OPB_RNW, DIR = I, BUS = SOPB
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PORT OPB_RNW = OPB_RNW, DIR = I, BUS = SOPB
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PORT OPB_select = OPB_select, DIR = I, BUS = SOPB
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PORT OPB_select = OPB_select, DIR = I, BUS = SOPB
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PORT OPB_seqAddr = OPB_seqAddr, DIR = I, BUS = SOPB
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PORT OPB_seqAddr = OPB_seqAddr, DIR = I, BUS = SOPB
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PORT OPB_DBus = OPB_DBus, DIR = I, VEC = [0:31], BUS = SOPB
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PORT OPB_DBus = OPB_DBus, DIR = I, VEC = [0:31], BUS = SOPB
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PORT Sl_DBus = Sl_DBus, DIR = O, VEC = [0:31], BUS = SOPB
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PORT Sl_DBus = Sl_DBus, DIR = O, VEC = [0:31], BUS = SOPB
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PORT Sl_errAck = Sl_errAck, DIR = O, BUS = SOPB
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PORT Sl_errAck = Sl_errAck, DIR = O, BUS = SOPB
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PORT Sl_retry = Sl_retry, DIR = O, BUS = SOPB
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PORT Sl_retry = Sl_retry, DIR = O, BUS = SOPB
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PORT Sl_toutSup = Sl_toutSup, DIR = O, BUS = SOPB
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PORT Sl_toutSup = Sl_toutSup, DIR = O, BUS = SOPB
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PORT Sl_xferAck = Sl_xferAck, DIR = O, BUS = SOPB
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PORT Sl_xferAck = Sl_xferAck, DIR = O, BUS = SOPB
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PORT Interrupt = "", DIR = O, LEVEL = HIGH, SIGIS = INTERRUPT, INTERRUPT_PRIORITY = LOW
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PORT Interrupt = "", DIR = O, LEVEL = HIGH, SIGIS = INTERRUPT, INTERRUPT_PRIORITY = LOW
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PORT txdp = "", DIR = O
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PORT txdp = "", DIR = O
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PORT txdn = "", DIR = O
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PORT txdn = "", DIR = O
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PORT txoe = "", DIR = O
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PORT txoe = "", DIR = O
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PORT rxd = "", DIR = I
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PORT rxd = "", DIR = I
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PORT rxdp = "", DIR = I
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PORT rxdp = "", DIR = I
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PORT rxdn = "", DIR = I
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PORT rxdn = "", DIR = I
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END
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END
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