--
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--
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-- opb_usblite - opb_uartlite replacement
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-- opb_usblite - opb_uartlite replacement
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--
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--
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-- opb_usblite is using components from Rudolf Usselmann see
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-- opb_usblite is using components from Rudolf Usselmann see
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-- http://www.opencores.org/cores/usb_phy/
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-- http://www.opencores.org/cores/usb_phy/
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-- and Joris van Rantwijk see http://www.xs4all.nl/~rjoris/fpga/usb.html
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-- and Joris van Rantwijk see http://www.xs4all.nl/~rjoris/fpga/usb.html
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--
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--
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-- Copyright (C) 2010 Ake Rehnman
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-- Copyright (C) 2010 Ake Rehnman
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--
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--
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-- This program is free software: you can redistribute it and/or modify
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-- This program is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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-- (at your option) any later version.
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--
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--
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-- This program is distributed in the hope that it will be useful,
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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-- GNU General Public License for more details.
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--
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--
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-- You should have received a copy of the GNU General Public License
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-- You should have received a copy of the GNU General Public License
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-- along with this program. If not, see <http://www.gnu.org/licenses/>.
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-- along with this program. If not, see <http://www.gnu.org/licenses/>.
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--
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--
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library IEEE;
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.std_logic_1164.all;
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entity OPB_USBLITE is
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entity OPB_USBLITE is
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generic (
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generic (
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C_OPB_AWIDTH : integer := 32;
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C_OPB_AWIDTH : integer := 32;
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C_OPB_DWIDTH : integer := 32;
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C_OPB_DWIDTH : integer := 32;
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C_BASEADDR : std_logic_vector(0 to 31) := X"FFFF_0000";
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C_BASEADDR : std_logic_vector(0 to 31) := X"FFFF_0000";
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C_HIGHADDR : std_logic_vector := X"FFFF_00FF";
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C_HIGHADDR : std_logic_vector := X"FFFF_00FF";
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C_SYSRST : std_logic := '1';
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C_SYSRST : std_logic := '1'; -- enable external reset
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C_PHYMODE : std_logic := '1';
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C_PHYMODE : std_logic := '1'; -- phy mode
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C_VENDORID : std_logic_vector(15 downto 0) := X"1234";
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C_VENDORID : std_logic_vector(15 downto 0) := X"1234"; -- VID
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C_PRODUCTID : std_logic_vector(15 downto 0) := X"5678";
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C_PRODUCTID : std_logic_vector(15 downto 0) := X"5678"; -- PID
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C_VERSIONBCD : std_logic_vector(15 downto 0) := X"0200";
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C_VERSIONBCD : std_logic_vector(15 downto 0) := X"0200"; -- device version
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C_SELFPOWERED : boolean := false;
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C_SELFPOWERED : boolean := false; -- self or bus powered
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C_RXBUFSIZE_BITS: integer range 7 to 12 := 10;
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C_RXBUFSIZE_BITS: integer range 7 to 12 := 10; -- size of rx buf (2^10 = 1024 bytes)
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C_TXBUFSIZE_BITS: integer range 7 to 12 := 10
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C_TXBUFSIZE_BITS: integer range 7 to 12 := 10 -- size of tx buf (2^10 = 1024 bytes)
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);
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);
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port (
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port (
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-- Global signals
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-- Global signals
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OPB_Clk : in std_logic;
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OPB_Clk : in std_logic;
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OPB_Rst : in std_logic;
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OPB_Rst : in std_logic;
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SYS_Rst : in std_logic;
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SYS_Rst : in std_logic;
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USB_Clk : in std_logic;
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USB_Clk : in std_logic;
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-- OPB signals
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-- OPB signals
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OPB_ABus : in std_logic_vector(0 to 31);
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OPB_ABus : in std_logic_vector(0 to 31);
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OPB_BE : in std_logic_vector(0 to 3);
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OPB_BE : in std_logic_vector(0 to 3);
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OPB_RNW : in std_logic;
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OPB_RNW : in std_logic;
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OPB_select : in std_logic;
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OPB_select : in std_logic;
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OPB_seqAddr : in std_logic;
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OPB_seqAddr : in std_logic;
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OPB_DBus : in std_logic_vector(0 to 31);
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OPB_DBus : in std_logic_vector(0 to 31);
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Sl_DBus : out std_logic_vector(0 to 31);
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Sl_DBus : out std_logic_vector(0 to 31);
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Sl_errAck : out std_logic;
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Sl_errAck : out std_logic;
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Sl_retry : out std_logic;
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Sl_retry : out std_logic;
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Sl_toutSup : out std_logic;
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Sl_toutSup : out std_logic;
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Sl_xferAck : out std_logic;
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Sl_xferAck : out std_logic;
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|
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-- Interrupt
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-- Interrupt
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Interrupt : out std_logic;
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Interrupt : out std_logic;
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-- USB signals
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-- USB signals
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txdp : out std_logic;
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txdp : out std_logic; -- connect to VPO
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txdn : out std_logic;
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txdn : out std_logic; -- connect to VMO/FSEO
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txoe : out std_logic;
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txoe : out std_logic; -- connect to OE
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rxd : in std_logic;
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rxd : in std_logic; -- connect to RCV
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rxdp : in std_logic;
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rxdp : in std_logic; -- connect to VP
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rxdn : in std_logic
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rxdn : in std_logic -- connect to VM
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);
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);
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end entity OPB_USBLITE;
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end entity OPB_USBLITE;
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library Common_v1_00_a;
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library Common_v1_00_a;
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use Common_v1_00_a.pselect;
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use Common_v1_00_a.pselect;
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|
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library unisim;
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library unisim;
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use unisim.all;
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use unisim.all;
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library opb_usblite_v1_00_a;
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library opb_usblite_v1_00_a;
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use opb_usblite_v1_00_a.opb_usblite_core;
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use opb_usblite_v1_00_a.opb_usblite_core;
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architecture akre of OPB_USBLITE is
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architecture akre of OPB_USBLITE is
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component pselect is
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component pselect is
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generic (
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generic (
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C_AB : integer;
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C_AB : integer;
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C_AW : integer;
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C_AW : integer;
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C_BAR : std_logic_vector);
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C_BAR : std_logic_vector);
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port (
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port (
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A : in std_logic_vector(0 to C_AW-1);
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A : in std_logic_vector(0 to C_AW-1);
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AValid : in std_logic;
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AValid : in std_logic;
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ps : out std_logic);
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ps : out std_logic);
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end component pselect;
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end component pselect;
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component OPB_USBLITE_Core is
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component OPB_USBLITE_Core is
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generic (
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generic (
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C_PHYMODE : std_logic := '1';
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C_PHYMODE : std_logic := '1';
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C_VENDORID : std_logic_vector(15 downto 0) := X"1234";
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C_VENDORID : std_logic_vector(15 downto 0) := X"1234";
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C_PRODUCTID : std_logic_vector(15 downto 0) := X"5678";
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C_PRODUCTID : std_logic_vector(15 downto 0) := X"5678";
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C_VERSIONBCD : std_logic_vector(15 downto 0) := X"0200";
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C_VERSIONBCD : std_logic_vector(15 downto 0) := X"0200";
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C_SELFPOWERED : boolean := false;
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C_SELFPOWERED : boolean := false;
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C_RXBUFSIZE_BITS: integer range 7 to 12 := 10;
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C_RXBUFSIZE_BITS: integer range 7 to 12 := 10;
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C_TXBUFSIZE_BITS: integer range 7 to 12 := 10
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C_TXBUFSIZE_BITS: integer range 7 to 12 := 10
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);
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);
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port (
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port (
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Clk : in std_logic;
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Clk : in std_logic;
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Reset : in std_logic;
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Reset : in std_logic;
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Usb_Clk : in std_logic;
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Usb_Clk : in std_logic;
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-- OPB signals
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-- OPB signals
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OPB_CS : in std_logic;
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OPB_CS : in std_logic;
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OPB_ABus : in std_logic_vector(0 to 1);
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OPB_ABus : in std_logic_vector(0 to 1);
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OPB_RNW : in std_logic;
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OPB_RNW : in std_logic;
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OPB_DBus : in std_logic_vector(7 downto 0);
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OPB_DBus : in std_logic_vector(7 downto 0);
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SIn_xferAck : out std_logic;
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SIn_xferAck : out std_logic;
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SIn_DBus : out std_logic_vector(7 downto 0);
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SIn_DBus : out std_logic_vector(7 downto 0);
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Interrupt : out std_logic;
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Interrupt : out std_logic;
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-- USB signals
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-- USB signals
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txdp : out std_logic;
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txdp : out std_logic;
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txdn : out std_logic;
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txdn : out std_logic;
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txoe : out std_logic;
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txoe : out std_logic;
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rxd : in std_logic;
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rxd : in std_logic;
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rxdp : in std_logic;
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rxdp : in std_logic;
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rxdn : in std_logic
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rxdn : in std_logic
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);
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);
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end component OPB_USBLITE_Core;
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end component OPB_USBLITE_Core;
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function nbits (x, y : std_logic_vector(0 to C_OPB_AWIDTH-1)) return integer is
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function nbits (x, y : std_logic_vector(0 to C_OPB_AWIDTH-1)) return integer is
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begin
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begin
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for i in 0 to C_OPB_AWIDTH-1 loop
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for i in 0 to C_OPB_AWIDTH-1 loop
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if x(i) /= y(i) then
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if x(i) /= y(i) then
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return i;
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return i;
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end if;
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end if;
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end loop;
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end loop;
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return(C_OPB_AWIDTH);
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return(C_OPB_AWIDTH);
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end function nbits;
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end function nbits;
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constant C_NBITS : integer := nbits(C_HIGHADDR, C_BASEADDR);
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constant C_NBITS : integer := nbits(C_HIGHADDR, C_BASEADDR);
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signal OPB_CS : std_logic;
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signal OPB_CS : std_logic;
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signal core_rst : std_logic;
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signal core_rst : std_logic;
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begin -- architecture akre
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begin -- architecture akre
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- OPB bus interface
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-- OPB bus interface
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- Do the OPB address decoding
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-- Do the OPB address decoding
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pselect_I : pselect
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pselect_I : pselect
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generic map (
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generic map (
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C_AB => C_NBITS,
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C_AB => C_NBITS,
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C_AW => C_OPB_AWIDTH,
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C_AW => C_OPB_AWIDTH,
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C_BAR => C_BASEADDR)
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C_BAR => C_BASEADDR)
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port map (
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port map (
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A => OPB_ABus,
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A => OPB_ABus,
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AValid => OPB_select,
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AValid => OPB_select,
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ps => OPB_CS);
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ps => OPB_CS);
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Sl_errAck <= '0';
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Sl_errAck <= '0';
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Sl_retry <= '0';
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Sl_retry <= '0';
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Sl_toutSup <= '0';
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Sl_toutSup <= '0';
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Sl_DBus(0 to 23) <= (others=>'0');
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Sl_DBus(0 to 23) <= (others=>'0');
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- Instanciating the USB core
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-- Instanciating the USB core
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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core_rst <= SYS_Rst when C_SYSRST='1' else OPB_Rst;
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core_rst <= SYS_Rst when C_SYSRST='1' else OPB_Rst;
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OPB_USBLITE_Core_inst : OPB_USBLITE_Core
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OPB_USBLITE_Core_inst : OPB_USBLITE_Core
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generic map (
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generic map (
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C_PHYMODE => C_PHYMODE,
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C_PHYMODE => C_PHYMODE,
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C_VENDORID => C_VENDORID,
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C_VENDORID => C_VENDORID,
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C_PRODUCTID => C_PRODUCTID,
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C_PRODUCTID => C_PRODUCTID,
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C_VERSIONBCD => C_VERSIONBCD,
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C_VERSIONBCD => C_VERSIONBCD,
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C_SELFPOWERED => C_SELFPOWERED,
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C_SELFPOWERED => C_SELFPOWERED,
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C_RXBUFSIZE_BITS => C_RXBUFSIZE_BITS,
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C_RXBUFSIZE_BITS => C_RXBUFSIZE_BITS,
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C_TXBUFSIZE_BITS => C_TXBUFSIZE_BITS
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C_TXBUFSIZE_BITS => C_TXBUFSIZE_BITS
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)
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)
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port map (
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port map (
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Clk => OPB_Clk,
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Clk => OPB_Clk,
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Reset => core_rst,
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Reset => core_rst,
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Usb_Clk => USB_Clk,
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Usb_Clk => USB_Clk,
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-- OPB signals
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-- OPB signals
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OPB_CS => OPB_CS,
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OPB_CS => OPB_CS,
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OPB_ABus => OPB_ABus(28 to 29),
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OPB_ABus => OPB_ABus(28 to 29),
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OPB_RNW => OPB_RNW,
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OPB_RNW => OPB_RNW,
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OPB_DBus => OPB_DBus(24 to 31),
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OPB_DBus => OPB_DBus(24 to 31),
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SIn_xferAck => Sl_xferAck,
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SIn_xferAck => Sl_xferAck,
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SIn_DBus => Sl_DBus(24 to 31),
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SIn_DBus => Sl_DBus(24 to 31),
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Interrupt => Interrupt,
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Interrupt => Interrupt,
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-- USB signals
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-- USB signals
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txdp => txdp,
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txdp => txdp,
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txdn => txdn,
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txdn => txdn,
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txoe => txoe,
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txoe => txoe,
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rxd => rxd,
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rxd => rxd,
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rxdp => rxdp,
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rxdp => rxdp,
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rxdn => rxdn
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rxdn => rxdn
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);
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);
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end architecture akre;
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end architecture akre;
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