-- Copyright (c)2006, 2016, 2019 Jeremy Seth Henry
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-- Copyright (c)2006, 2016, 2019 Jeremy Seth Henry
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-- All rights reserved.
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-- All rights reserved.
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--
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--
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-- Redistribution and use in source and binary forms, with or without
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-- Redistribution and use in source and binary forms, with or without
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-- modification, are permitted provided that the following conditions are met:
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-- modification, are permitted provided that the following conditions are met:
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-- * Redistributions of source code must retain the above copyright
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-- * Redistributions of source code must retain the above copyright
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-- notice, this list of conditions and the following disclaimer.
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-- notice, this list of conditions and the following disclaimer.
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-- * Redistributions in binary form must reproduce the above copyright
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-- * Redistributions in binary form must reproduce the above copyright
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-- notice, this list of conditions and the following disclaimer in the
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-- notice, this list of conditions and the following disclaimer in the
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-- documentation and/or other materials provided with the distribution,
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-- documentation and/or other materials provided with the distribution,
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-- where applicable (as part of a user interface, debugging port, etc.)
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-- where applicable (as part of a user interface, debugging port, etc.)
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--
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--
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-- THIS SOFTWARE IS PROVIDED BY JEREMY SETH HENRY ``AS IS'' AND ANY
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-- THIS SOFTWARE IS PROVIDED BY JEREMY SETH HENRY ``AS IS'' AND ANY
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-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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-- DISCLAIMED. IN NO EVENT SHALL JEREMY SETH HENRY BE LIABLE FOR ANY
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-- DISCLAIMED. IN NO EVENT SHALL JEREMY SETH HENRY BE LIABLE FOR ANY
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-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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--
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--
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-- VHDL Units : async_ser_tx
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-- VHDL Units : async_ser_tx
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-- Description: Asynchronous transmitter wired for 8[N/E/O]1 data. Parity mode
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-- Description: Asynchronous transmitter wired for 8[N/E/O]1 data. Parity mode
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-- and bit rate are set with generics.
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-- and bit rate are set with generics.
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_misc.all;
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use ieee.std_logic_misc.all;
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library work;
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use work.open8_pkg.all;
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entity async_ser_tx is
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entity async_ser_tx is
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generic(
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generic(
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Reset_Level : std_logic;
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Reset_Level : std_logic;
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Enable_Parity : boolean;
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Enable_Parity : boolean;
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Parity_Odd_Even_n : std_logic;
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Parity_Odd_Even_n : std_logic;
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Clock_Divider : integer
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Clock_Divider : integer
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);
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);
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port(
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port(
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Clock : in std_logic;
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Clock : in std_logic;
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Reset : in std_logic;
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Reset : in std_logic;
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--
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--
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Tx_Data : in std_logic_vector(7 downto 0);
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Tx_Data : in std_logic_vector(7 downto 0);
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Tx_Valid : in std_logic;
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Tx_Valid : in std_logic;
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--
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--
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Tx_Out : out std_logic;
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Tx_Out : out std_logic;
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Tx_Done : out std_logic
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Tx_Done : out std_logic
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);
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);
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end entity;
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end entity;
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architecture behave of async_ser_tx is
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architecture behave of async_ser_tx is
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-- The ceil_log2 function returns the minimum register width required to
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-- hold the supplied integer.
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function ceil_log2 (x : in natural) return natural is
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variable retval : natural;
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begin
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retval := 1;
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while ((2**retval) - 1) < x loop
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retval := retval + 1;
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end loop;
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return retval;
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end ceil_log2;
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constant Tick_Base : integer := Clock_Divider - 1;
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constant Tick_Base : integer := Clock_Divider - 1;
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constant Tick_Bits : integer := ceil_log2(Tick_Base);
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constant Tick_Bits : integer := ceil_log2(Tick_Base);
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constant TICK_DIV : std_logic_vector(Tick_Bits - 1 downto 0) :=
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constant TICK_DIV : std_logic_vector(Tick_Bits - 1 downto 0) :=
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conv_std_logic_vector(Tick_Base, Tick_Bits);
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conv_std_logic_vector(Tick_Base, Tick_Bits);
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signal Tick_Cntr : std_logic_vector(Tick_Bits - 1 downto 0);
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signal Tick_Cntr : std_logic_vector(Tick_Bits - 1 downto 0) :=
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signal Tick_Trig : std_logic;
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(others => '0');
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signal Tx_Enable : std_logic;
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signal Tx_Buffer : std_logic_vector(7 downto 0);
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signal Tx_Parity : std_logic;
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signal Tx_State : std_logic_vector(3 downto 0);
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signal Tick_Trig : std_logic := '0';
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signal Tx_Enable : std_logic := '0';
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signal Tx_Buffer : std_logic_vector(7 downto 0) := x"00";
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signal Tx_Parity : std_logic := '0';
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signal Tx_State : std_logic_vector(3 downto 0) := x"0";
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alias Tx_Bit_Sel is Tx_State(2 downto 0);
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alias Tx_Bit_Sel is Tx_State(2 downto 0);
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-- State machine definitions
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-- State machine definitions
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constant IO_RSV0 : std_logic_vector(3 downto 0) := "1011"; -- B
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constant IO_RSV0 : std_logic_vector(3 downto 0) := "1011"; -- B
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constant IO_RSV1 : std_logic_vector(3 downto 0) := "1100"; -- C
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constant IO_RSV1 : std_logic_vector(3 downto 0) := "1100"; -- C
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constant IO_RSV2 : std_logic_vector(3 downto 0) := "1101"; -- D
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constant IO_RSV2 : std_logic_vector(3 downto 0) := "1101"; -- D
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constant IO_IDLE : std_logic_vector(3 downto 0) := "1110"; -- E
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constant IO_IDLE : std_logic_vector(3 downto 0) := "1110"; -- E
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constant IO_STRT : std_logic_vector(3 downto 0) := "1111"; -- F
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constant IO_STRT : std_logic_vector(3 downto 0) := "1111"; -- F
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constant IO_BIT0 : std_logic_vector(3 downto 0) := "0000"; -- 0
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constant IO_BIT0 : std_logic_vector(3 downto 0) := "0000"; -- 0
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constant IO_BIT1 : std_logic_vector(3 downto 0) := "0001"; -- 1
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constant IO_BIT1 : std_logic_vector(3 downto 0) := "0001"; -- 1
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constant IO_BIT2 : std_logic_vector(3 downto 0) := "0010"; -- 2
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constant IO_BIT2 : std_logic_vector(3 downto 0) := "0010"; -- 2
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constant IO_BIT3 : std_logic_vector(3 downto 0) := "0011"; -- 3
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constant IO_BIT3 : std_logic_vector(3 downto 0) := "0011"; -- 3
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constant IO_BIT4 : std_logic_vector(3 downto 0) := "0100"; -- 4
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constant IO_BIT4 : std_logic_vector(3 downto 0) := "0100"; -- 4
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constant IO_BIT5 : std_logic_vector(3 downto 0) := "0101"; -- 5
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constant IO_BIT5 : std_logic_vector(3 downto 0) := "0101"; -- 5
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constant IO_BIT6 : std_logic_vector(3 downto 0) := "0110"; -- 6
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constant IO_BIT6 : std_logic_vector(3 downto 0) := "0110"; -- 6
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constant IO_BIT7 : std_logic_vector(3 downto 0) := "0111"; -- 7
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constant IO_BIT7 : std_logic_vector(3 downto 0) := "0111"; -- 7
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constant IO_PARI : std_logic_vector(3 downto 0) := "1000"; -- 8
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constant IO_PARI : std_logic_vector(3 downto 0) := "1000"; -- 8
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constant IO_STOP : std_logic_vector(3 downto 0) := "1001"; -- 9
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constant IO_STOP : std_logic_vector(3 downto 0) := "1001"; -- 9
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constant IO_DONE : std_logic_vector(3 downto 0) := "1010"; -- A
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constant IO_DONE : std_logic_vector(3 downto 0) := "1010"; -- A
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begin
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begin
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UART_Regs: process( Clock, Reset )
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UART_Regs: process( Clock, Reset )
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begin
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begin
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if( Reset = Reset_Level )then
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if( Reset = Reset_Level )then
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Tick_Cntr <= (others => '0');
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Tick_Cntr <= (others => '0');
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Tick_Trig <= '0';
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Tick_Trig <= '0';
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Tx_State <= IO_IDLE;
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Tx_State <= IO_IDLE;
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Tx_Enable <= '0';
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Tx_Enable <= '0';
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Tx_Buffer <= (others => '0');
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Tx_Buffer <= (others => '0');
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if( Enable_Parity )then
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if( Enable_Parity )then
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Tx_Parity <= '0';
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Tx_Parity <= '0';
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end if;
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end if;
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Tx_Out <= '1';
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Tx_Out <= '1';
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Tx_Done <= '0';
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Tx_Done <= '0';
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elsif( rising_edge(Clock) )then
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elsif( rising_edge(Clock) )then
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Tick_Cntr <= (others => '0');
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Tick_Cntr <= (others => '0');
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Tick_Trig <= '0';
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Tick_Trig <= '0';
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if( Tx_Enable = '1' )then
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if( Tx_Enable = '1' )then
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Tick_Cntr <= Tick_Cntr - 1;
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Tick_Cntr <= Tick_Cntr - 1;
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Tick_Trig <= '0';
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Tick_Trig <= '0';
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if( or_reduce(Tick_Cntr) = '0' )then
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if( or_reduce(Tick_Cntr) = '0' )then
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Tick_Cntr <= TICK_DIV;
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Tick_Cntr <= TICK_DIV;
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Tick_Trig <= '1';
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Tick_Trig <= '1';
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end if;
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end if;
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end if;
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end if;
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if( Tx_Valid = '1' )then
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if( Tx_Valid = '1' )then
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Tx_Buffer <= Tx_Data;
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Tx_Buffer <= Tx_Data;
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Tx_Enable <= '1';
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Tx_Enable <= '1';
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end if;
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end if;
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Tx_State <= Tx_State + Tick_Trig;
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Tx_State <= Tx_State + Tick_Trig;
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Tx_Done <= '0';
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Tx_Done <= '0';
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Tx_Out <= '1';
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Tx_Out <= '1';
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case( Tx_State )is
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case( Tx_State )is
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when IO_IDLE =>
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when IO_IDLE =>
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if( Enable_Parity )then
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if( Enable_Parity )then
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Tx_Parity <= Parity_Odd_Even_n;
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Tx_Parity <= Parity_Odd_Even_n;
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end if;
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end if;
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when IO_STRT =>
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when IO_STRT =>
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Tx_Out <= '0';
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Tx_Out <= '0';
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when IO_BIT0 | IO_BIT1 | IO_BIT2 | IO_BIT3 |
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when IO_BIT0 | IO_BIT1 | IO_BIT2 | IO_BIT3 |
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IO_BIT4 | IO_BIT5 | IO_BIT6 | IO_BIT7 =>
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IO_BIT4 | IO_BIT5 | IO_BIT6 | IO_BIT7 =>
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Tx_Out <= Tx_Buffer(conv_integer(Tx_Bit_Sel));
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Tx_Out <= Tx_Buffer(conv_integer(Tx_Bit_Sel));
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if( Tick_Trig = '1' and Enable_Parity )then
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if( Tick_Trig = '1' and Enable_Parity )then
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Tx_Parity <= Tx_Parity xor Tx_Buffer(conv_integer(Tx_Bit_Sel));
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Tx_Parity <= Tx_Parity xor Tx_Buffer(conv_integer(Tx_Bit_Sel));
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end if;
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end if;
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when IO_PARI =>
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when IO_PARI =>
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if( Enable_Parity )then
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if( Enable_Parity )then
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Tx_Out <= Tx_Parity;
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Tx_Out <= Tx_Parity;
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end if;
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end if;
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when IO_STOP =>
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when IO_STOP =>
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when IO_DONE =>
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when IO_DONE =>
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Tx_Done <= '1';
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Tx_Done <= '1';
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Tx_Enable <= '0';
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Tx_Enable <= '0';
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Tx_State <= IO_IDLE;
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Tx_State <= IO_IDLE;
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when others =>
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when others =>
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end case;
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end case;
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if( Tx_Enable = '0' )then
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if( Tx_Enable = '0' )then
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Tx_State <= IO_IDLE;
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Tx_State <= IO_IDLE;
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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