-- Copyright (c)2020 Jeremy Seth Henry
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-- Copyright (c)2020 Jeremy Seth Henry
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-- All rights reserved.
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-- All rights reserved.
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--
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--
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-- Redistribution and use in source and binary forms, with or without
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-- Redistribution and use in source and binary forms, with or without
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-- modification, are permitted provided that the following conditions are met:
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-- modification, are permitted provided that the following conditions are met:
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-- * Redistributions of source code must retain the above copyright
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-- * Redistributions of source code must retain the above copyright
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-- notice, this list of conditions and the following disclaimer.
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-- notice, this list of conditions and the following disclaimer.
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-- * Redistributions in binary form must reproduce the above copyright
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-- * Redistributions in binary form must reproduce the above copyright
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-- notice, this list of conditions and the following disclaimer in the
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-- notice, this list of conditions and the following disclaimer in the
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-- documentation and/or other materials provided with the distribution,
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-- documentation and/or other materials provided with the distribution,
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-- where applicable (as part of a user interface, debugging port, etc.)
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-- where applicable (as part of a user interface, debugging port, etc.)
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--
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--
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-- THIS SOFTWARE IS PROVIDED BY JEREMY SETH HENRY ``AS IS'' AND ANY
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-- THIS SOFTWARE IS PROVIDED BY JEREMY SETH HENRY ``AS IS'' AND ANY
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-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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-- DISCLAIMED. IN NO EVENT SHALL JEREMY SETH HENRY BE LIABLE FOR ANY
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-- DISCLAIMED. IN NO EVENT SHALL JEREMY SETH HENRY BE LIABLE FOR ANY
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-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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-- THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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-- THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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--
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--
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-- VHDL Units : o8_register
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-- VHDL Units : o8_7seg
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-- Description: Provides a single addressible 8-bit output register
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-- Description: Drives up to two 7-segment displays in either common cathode
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-- : or common anode mode with per-display PWM brightness.
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--
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--
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-- Register Map:
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-- Register Map:
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-- Offset Bitfield Description Read/Write
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-- Offset Bitfield Description Read/Write
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-- 0x00 ---AAAAA Display 1 value (RW)
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-- 0x00 ---AAAAA Display 1 value (RW)
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-- 0x01 ---AAAAA Display 2 value (RW)
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-- 0x01 ---AAAAA Display 2 value (RW)
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-- 0x02 AAAAAAAA Display 1 brightness (RW)
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-- 0x02 AAAAAAAA Display 1 brightness (RW)
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-- 0x03 AAAAAAAA Display 2 brightness (RW)
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-- 0x03 AAAAAAAA Display 2 brightness (RW)
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--
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--
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-- Revision History
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-- Revision History
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-- Author Date Change
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-- Author Date Change
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------------------ -------- ---------------------------------------------------
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------------------ -------- ---------------------------------------------------
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-- Seth Henry 05/08/19 Design Start
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-- Seth Henry 05/08/19 Design Start
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-- Seth Henry 05/18/20 Added write qualification input
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-- Seth Henry 05/18/20 Added write qualification input
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_misc.all;
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use ieee.std_logic_misc.all;
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library work;
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library work;
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use work.open8_pkg.all;
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use work.open8_pkg.all;
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entity o8_7seg is
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entity o8_7seg is
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generic(
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generic(
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Default_LED1_Value : std_logic_vector(4 downto 0);
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Default_LED1_Value : std_logic_vector(4 downto 0);
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Default_LED1_Bright : DATA_TYPE := x"FF";
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Default_LED1_Bright : DATA_TYPE := x"FF";
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Default_LED2_Value : std_logic_vector(4 downto 0);
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Default_LED2_Value : std_logic_vector(4 downto 0);
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Default_LED2_Bright : DATA_TYPE := x"FF";
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Default_LED2_Bright : DATA_TYPE := x"FF";
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Common_Cathode : boolean := TRUE;
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Common_Cathode : boolean := TRUE;
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Address : ADDRESS_TYPE
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Address : ADDRESS_TYPE
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);
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);
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port(
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port(
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Open8_Bus : in OPEN8_BUS_TYPE;
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Open8_Bus : in OPEN8_BUS_TYPE;
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Write_Qual : in std_logic := '1';
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Write_Qual : in std_logic := '1';
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Rd_Data : out DATA_TYPE;
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Rd_Data : out DATA_TYPE;
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--
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--
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SegLED1 : out std_logic_vector(6 downto 0);
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SegLED1 : out std_logic_vector(6 downto 0);
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SegLED2 : out std_logic_vector(6 downto 0)
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SegLED2 : out std_logic_vector(6 downto 0)
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);
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);
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end entity;
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end entity;
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architecture behave of o8_7seg is
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architecture behave of o8_7seg is
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alias Clock is Open8_Bus.Clock;
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alias Clock is Open8_Bus.Clock;
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alias Reset is Open8_Bus.Reset;
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alias Reset is Open8_Bus.Reset;
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constant User_Addr : std_logic_vector(15 downto 2)
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constant User_Addr : std_logic_vector(15 downto 2)
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:= Address(15 downto 2);
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:= Address(15 downto 2);
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alias Comp_Addr is Open8_Bus.Address(15 downto 2);
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alias Comp_Addr is Open8_Bus.Address(15 downto 2);
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signal Addr_Match : std_logic;
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signal Addr_Match : std_logic;
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alias Reg_Sel_d is Open8_Bus.Address(1 downto 0);
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alias Reg_Sel_d is Open8_Bus.Address(1 downto 0);
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signal Reg_Sel_q : std_logic_vector(1 downto 0) := "00";
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signal Reg_Sel_q : std_logic_vector(1 downto 0) := "00";
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signal Wr_En_d : std_logic := '0';
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signal Wr_En_d : std_logic := '0';
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signal Wr_En_q : std_logic := '0';
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signal Wr_En_q : std_logic := '0';
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alias Wr_Data_d is Open8_Bus.Wr_Data;
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alias Wr_Data_d is Open8_Bus.Wr_Data;
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signal Wr_Data_q : DATA_TYPE := x"00";
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signal Wr_Data_q : DATA_TYPE := x"00";
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signal Rd_En_d : std_logic := '0';
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signal Rd_En_d : std_logic := '0';
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signal Rd_En_q : std_logic := '0';
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signal Rd_En_q : std_logic := '0';
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signal LED1_Reg : std_logic_vector(4 downto 0);
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signal LED1_Reg : std_logic_vector(4 downto 0);
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signal LED1_Brt : DATA_TYPE;
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signal LED1_Brt : DATA_TYPE;
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signal LED2_Reg : std_logic_vector(4 downto 0);
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signal LED2_Reg : std_logic_vector(4 downto 0);
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signal LED2_Brt : DATA_TYPE;
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signal LED2_Brt : DATA_TYPE;
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signal LED1_PDM : std_logic;
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signal LED1_PDM : std_logic;
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signal LED1_Ext : std_logic_vector(6 downto 0);
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signal LED1_Ext : std_logic_vector(6 downto 0);
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signal LED2_PDM : std_logic;
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signal LED2_PDM : std_logic;
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signal LED2_Ext : std_logic_vector(6 downto 0);
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signal LED2_Ext : std_logic_vector(6 downto 0);
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signal SegLED1_Full : std_logic_vector(6 downto 0);
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signal SegLED1_Full : std_logic_vector(6 downto 0);
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signal SegLED2_Full : std_logic_vector(6 downto 0);
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signal SegLED2_Full : std_logic_vector(6 downto 0);
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-- Standard 7-Segment Numeric Display
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-- Standard 7-Segment Numeric Display
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--
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--
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-- -A-
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-- -A-
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-- | |
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-- | |
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-- F B
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-- F B
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-- | |
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-- | |
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-- -G-
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-- -G-
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-- | |
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-- | |
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-- E C
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-- E C
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-- | |
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-- | |
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-- -D- (DP)
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-- -D- (DP)
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type LED_DEFS_TYPE is array(0 to 31) of std_logic_vector(6 downto 0);
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type LED_DEFS_TYPE is array(0 to 31) of std_logic_vector(6 downto 0);
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constant CHAR_DEFINITIONS : LED_DEFS_TYPE := (
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constant CHAR_DEFINITIONS : LED_DEFS_TYPE := (
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-- GFEDCBA
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-- GFEDCBA
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"0111111", -- 00 -> 0
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"0111111", -- 00 -> 0
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"0000110", -- 01 -> 1
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"0000110", -- 01 -> 1
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"1011011", -- 02 -> 2
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"1011011", -- 02 -> 2
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"1001111", -- 03 -> 3
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"1001111", -- 03 -> 3
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"1100110", -- 04 -> 4
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"1100110", -- 04 -> 4
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"1101101", -- 05 -> 5
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"1101101", -- 05 -> 5
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"1111101", -- 06 -> 6
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"1111101", -- 06 -> 6
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"0000111", -- 07 -> 7
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"0000111", -- 07 -> 7
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"1111111", -- 08 -> 8
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"1111111", -- 08 -> 8
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"1101111", -- 09 -> 9
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"1101111", -- 09 -> 9
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"1110111", -- 10 -> A
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"1110111", -- 10 -> A
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"1111100", -- 11 -> B
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"1111100", -- 11 -> B
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"1011000", -- 12 -> C
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"1011000", -- 12 -> C
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"1011110", -- 13 -> D
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"1011110", -- 13 -> D
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"1111001", -- 14 -> E
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"1111001", -- 14 -> E
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"1110001", -- 15 -> F
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"1110001", -- 15 -> F
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"0111101", -- 16 -> G
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"0111101", -- 16 -> G
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"1110110", -- 17 -> H
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"1110110", -- 17 -> H
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"0000100", -- 18 -> i
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"0000100", -- 18 -> i
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"0001110", -- 19 -> J
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"0001110", -- 19 -> J
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"0111000", -- 20 -> L
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"0111000", -- 20 -> L
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"1010100", -- 21 -> n
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"1010100", -- 21 -> n
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"1011100", -- 22 -> o
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"1011100", -- 22 -> o
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"1110011", -- 23 -> P
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"1110011", -- 23 -> P
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"1010000", -- 24 -> r
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"1010000", -- 24 -> r
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"0011100", -- 25 -> u
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"0011100", -- 25 -> u
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"1101110", -- 26 -> y
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"1101110", -- 26 -> y
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"1000000", -- 27 -> -
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"1000000", -- 27 -> -
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"1001000", -- 28 -> =
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"1001000", -- 28 -> =
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"1100011", -- 29 -> DEG
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"1100011", -- 29 -> DEG
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"0000010", -- 30 -> '
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"0000010", -- 30 -> '
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"0000000" -- 31 -> " "
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"0000000" -- 31 -> " "
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);
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);
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begin
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begin
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Addr_Match <= '1' when Comp_Addr = User_Addr else '0';
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Addr_Match <= '1' when Comp_Addr = User_Addr else '0';
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Wr_En_d <= Addr_Match and Open8_Bus.Wr_En and Write_Qual;
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Wr_En_d <= Addr_Match and Open8_Bus.Wr_En and Write_Qual;
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Rd_En_d <= Addr_Match and Open8_Bus.Rd_En;
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Rd_En_d <= Addr_Match and Open8_Bus.Rd_En;
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io_reg: process( Clock, Reset )
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io_reg: process( Clock, Reset )
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begin
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begin
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if( Reset = Reset_Level )then
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if( Reset = Reset_Level )then
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Reg_Sel_q <= "00";
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Reg_Sel_q <= "00";
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Wr_En_q <= '0';
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Wr_En_q <= '0';
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Wr_Data_q <= x"00";
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Wr_Data_q <= x"00";
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Rd_En_q <= '0';
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Rd_En_q <= '0';
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Rd_Data <= OPEN8_NULLBUS;
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Rd_Data <= OPEN8_NULLBUS;
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LED1_Reg <= Default_LED1_Value;
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LED1_Reg <= Default_LED1_Value;
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LED2_Reg <= Default_LED2_Value;
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LED2_Reg <= Default_LED2_Value;
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LED1_Brt <= Default_LED1_Bright;
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LED1_Brt <= Default_LED1_Bright;
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LED2_Brt <= Default_LED2_Bright;
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LED2_Brt <= Default_LED2_Bright;
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elsif( rising_edge( Clock ) )then
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elsif( rising_edge( Clock ) )then
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Reg_Sel_q <= Reg_Sel_d;
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Reg_Sel_q <= Reg_Sel_d;
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Wr_En_q <= Wr_En_d;
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Wr_En_q <= Wr_En_d;
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Wr_Data_q <= Wr_Data_d;
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Wr_Data_q <= Wr_Data_d;
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if( Wr_En_q = '1' )then
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if( Wr_En_q = '1' )then
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case( Reg_Sel_q )is
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case( Reg_Sel_q )is
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when "00" =>
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when "00" =>
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LED1_Reg <= Wr_Data_q(4 downto 0);
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LED1_Reg <= Wr_Data_q(4 downto 0);
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when "01" =>
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when "01" =>
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LED2_Reg <= Wr_Data_q(4 downto 0);
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LED2_Reg <= Wr_Data_q(4 downto 0);
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when "10" =>
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when "10" =>
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LED1_Brt <= Wr_Data_q;
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LED1_Brt <= Wr_Data_q;
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when "11" =>
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when "11" =>
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LED2_Brt <= Wr_Data_q;
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LED2_Brt <= Wr_Data_q;
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when others =>
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when others =>
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null;
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null;
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end case;
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end case;
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end if;
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end if;
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Rd_En_q <= Rd_En_d;
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Rd_En_q <= Rd_En_d;
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Rd_Data <= OPEN8_NULLBUS;
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Rd_Data <= OPEN8_NULLBUS;
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if( Rd_En_q = '1' )then
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if( Rd_En_q = '1' )then
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case( Reg_Sel_q )is
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case( Reg_Sel_q )is
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when "00" =>
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when "00" =>
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Rd_Data <= "000" & LED1_Reg;
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Rd_Data <= "000" & LED1_Reg;
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when "01" =>
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when "01" =>
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Rd_Data <= "000" & LED2_Reg;
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Rd_Data <= "000" & LED2_Reg;
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when "10" =>
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when "10" =>
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Rd_Data <= LED1_Brt;
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Rd_Data <= LED1_Brt;
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when "11" =>
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when "11" =>
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Rd_Data <= LED2_Brt;
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Rd_Data <= LED2_Brt;
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when others =>
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when others =>
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null;
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null;
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end case;
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end case;
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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U_LED1_PWM : entity work.vdsm8
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U_LED1_PWM : entity work.vdsm8
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generic map(
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generic map(
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Reset_Level => Reset_Level
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Reset_Level => Reset_Level
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)
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)
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port map(
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port map(
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Clock => Clock,
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Clock => Clock,
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Reset => Reset,
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Reset => Reset,
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DACin => LED1_Brt,
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DACin => LED1_Brt,
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DACout => LED1_PDM
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DACout => LED1_PDM
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);
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);
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U_LED2_PWM : entity work.vdsm8
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U_LED2_PWM : entity work.vdsm8
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generic map(
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generic map(
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Reset_Level => Reset_Level
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Reset_Level => Reset_Level
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)
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)
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port map(
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port map(
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Clock => Clock,
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Clock => Clock,
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Reset => Reset,
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Reset => Reset,
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DACin => LED2_Brt,
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DACin => LED2_Brt,
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DACout => LED2_PDM
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DACout => LED2_PDM
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);
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);
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LED1_Ext <= (others => LED1_PDM);
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LED1_Ext <= (others => LED1_PDM);
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LED2_Ext <= (others => LED2_PDM);
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LED2_Ext <= (others => LED2_PDM);
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SegLED1_Full <= CHAR_DEFINITIONS(conv_integer(LED1_Reg));
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SegLED1_Full <= CHAR_DEFINITIONS(conv_integer(LED1_Reg));
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SegLED2_Full <= CHAR_DEFINITIONS(conv_integer(LED2_Reg));
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SegLED2_Full <= CHAR_DEFINITIONS(conv_integer(LED2_Reg));
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Common_Cathode_Mode : if( Common_Cathode )generate
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Common_Cathode_Mode : if( Common_Cathode )generate
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LUT_proc: process( Clock, Reset )
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LUT_proc: process( Clock, Reset )
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begin
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begin
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if( Reset = Reset_Level )then
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if( Reset = Reset_Level )then
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SegLED1 <= (others => '0');
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SegLED1 <= (others => '0');
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SegLED2 <= (others => '0');
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SegLED2 <= (others => '0');
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elsif( rising_edge(Clock) )then
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elsif( rising_edge(Clock) )then
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SegLED1 <= (SegLED1_Full and LED1_Ext) xor "1111111";
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SegLED1 <= (SegLED1_Full and LED1_Ext) xor "1111111";
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SegLED2 <= (SegLED2_Full and LED2_Ext) xor "1111111";
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SegLED2 <= (SegLED2_Full and LED2_Ext) xor "1111111";
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end if;
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end if;
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end process;
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end process;
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end generate;
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end generate;
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Common_Anode_Mode : if( not Common_Cathode )generate
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Common_Anode_Mode : if( not Common_Cathode )generate
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LUT_proc: process( Clock, Reset )
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LUT_proc: process( Clock, Reset )
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begin
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begin
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if( Reset = Reset_Level )then
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if( Reset = Reset_Level )then
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SegLED1 <= (others => '1');
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SegLED1 <= (others => '1');
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SegLED2 <= (others => '1');
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SegLED2 <= (others => '1');
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elsif( rising_edge(Clock) )then
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elsif( rising_edge(Clock) )then
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SegLED1 <= (SegLED1_Full and LED1_Ext);
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SegLED1 <= (SegLED1_Full and LED1_Ext);
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SegLED2 <= (SegLED2_Full and LED2_Ext);
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SegLED2 <= (SegLED2_Full and LED2_Ext);
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end if;
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end if;
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end process;
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end process;
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end generate;
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end generate;
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end architecture;
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end architecture;
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