-- Copyright (c)2020 Jeremy Seth Henry
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-- Copyright (c)2020 Jeremy Seth Henry
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-- All rights reserved.
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-- All rights reserved.
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--
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--
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-- Redistribution and use in source and binary forms, with or without
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-- Redistribution and use in source and binary forms, with or without
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-- modification, are permitted provided that the following conditions are met:
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-- modification, are permitted provided that the following conditions are met:
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-- * Redistributions of source code must retain the above copyright
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-- * Redistributions of source code must retain the above copyright
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-- notice, this list of conditions and the following disclaimer.
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-- notice, this list of conditions and the following disclaimer.
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-- * Redistributions in binary form must reproduce the above copyright
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-- * Redistributions in binary form must reproduce the above copyright
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-- notice, this list of conditions and the following disclaimer in the
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-- notice, this list of conditions and the following disclaimer in the
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-- documentation and/or other materials provided with the distribution,
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-- documentation and/or other materials provided with the distribution,
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-- where applicable (as part of a user interface, debugging port, etc.)
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-- where applicable (as part of a user interface, debugging port, etc.)
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--
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--
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-- THIS SOFTWARE IS PROVIDED BY JEREMY SETH HENRY ``AS IS'' AND ANY
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-- THIS SOFTWARE IS PROVIDED BY JEREMY SETH HENRY ``AS IS'' AND ANY
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-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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-- DISCLAIMED. IN NO EVENT SHALL JEREMY SETH HENRY BE LIABLE FOR ANY
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-- DISCLAIMED. IN NO EVENT SHALL JEREMY SETH HENRY BE LIABLE FOR ANY
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-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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-- THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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--
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--
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-- VHDL Units : o8_async_serial
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-- VHDL Units : o8_async_serial
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-- Description: Provides a single 8-bit, asynchronous transceiver. While the
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-- Description: Provides a single 8-bit, asynchronous transceiver. While the
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-- width is fixed at 8-bits, the bit rate and parity controls
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-- width is fixed at 8-bits, the bit rate and parity controls
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-- are settable via generics.
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-- are settable via generics.
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--
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--
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-- Register Map:
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-- Offset Bitfield Description Read/Write
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-- 0x00 AAAAAAAA TX Data (WR) RX Data (RD) (RW)
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-- 0x01 DCBA---- FIFO Status (RO)
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-- A: RX FIFO Empty
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-- B: RX FIFO almost full (922/1024)
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-- C: TX FIFO Empty
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-- D: TX FIFO almost full (922/1024)
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--
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-- Note: The baud rate generator will produce an approximate frequency. The
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-- Note: The baud rate generator will produce an approximate frequency. The
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-- final bit rate should be within +/- 1% of the true bit rate to
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-- final bit rate should be within +/- 1% of the true bit rate to
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-- ensure the receiver can successfully receive. With a sufficiently
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-- ensure the receiver can successfully receive. With a sufficiently
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-- high core clock, this is generally achievable for common PC serial
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-- high core clock, this is generally achievable for common PC serial
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-- data rates.
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-- data rates.
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--
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-- Revision History
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-- Author Date Change
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------------------ -------- ---------------------------------------------------
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-- Seth Henry 12/20/19 Design Start
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-- Seth Henry 04/10/20 Code cleanup and register documentation
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_misc.all;
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use ieee.std_logic_misc.all;
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library work;
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library work;
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use work.open8_pkg.all;
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use work.open8_pkg.all;
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entity o8_async_serial is
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entity o8_async_serial is
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generic(
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generic(
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Disable_Transmit : boolean := FALSE;
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Disable_Receive : boolean := FALSE;
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Bit_Rate : real;
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Bit_Rate : real;
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Enable_Parity : boolean;
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Enable_Parity : boolean;
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Parity_Odd_Even_n : std_logic;
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Parity_Odd_Even_n : std_logic;
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Sys_Freq : real;
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Sys_Freq : real;
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Reset_Level : std_logic;
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Reset_Level : std_logic;
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Address : ADDRESS_TYPE
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Address : ADDRESS_TYPE
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);
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);
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port(
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port(
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Clock : in std_logic;
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Clock : in std_logic;
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Reset : in std_logic;
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Reset : in std_logic;
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--
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--
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Bus_Address : in ADDRESS_TYPE;
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Bus_Address : in ADDRESS_TYPE;
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Wr_Enable : in std_logic;
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Wr_Enable : in std_logic;
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Wr_Data : in DATA_TYPE;
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Wr_Data : in DATA_TYPE;
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Rd_Enable : in std_logic;
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Rd_Enable : in std_logic;
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Rd_Data : out DATA_TYPE;
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Rd_Data : out DATA_TYPE;
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--
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--
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TX_Out : out std_logic;
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TX_Out : out std_logic;
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CTS_In : in std_logic;
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CTS_In : in std_logic;
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RX_In : in std_logic;
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RX_In : in std_logic;
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RTS_Out : out std_logic
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RTS_Out : out std_logic
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);
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);
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end entity;
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end entity;
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architecture behave of o8_async_serial is
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architecture behave of o8_async_serial is
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signal FIFO_Reset : std_logic := '0';
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signal FIFO_Reset : std_logic := '0';
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constant User_Addr : std_logic_vector(15 downto 1) :=
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constant User_Addr : std_logic_vector(15 downto 1) :=
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Address(15 downto 1);
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Address(15 downto 1);
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alias Comp_Addr is Bus_Address(15 downto 1);
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alias Comp_Addr is Bus_Address(15 downto 1);
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signal Addr_Match : std_logic := '0';
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signal Addr_Match : std_logic := '0';
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alias Reg_Addr is Bus_Address(0);
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alias Reg_Addr is Bus_Address(0);
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signal Reg_Sel : std_logic := '0';
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signal Reg_Sel : std_logic := '0';
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signal Rd_En : std_logic := '0';
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signal Rd_En : std_logic := '0';
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signal TX_FIFO_Wr_En : std_logic := '0';
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signal TX_FIFO_Wr_En : std_logic := '0';
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alias TX_FIFO_Wr_Data is Wr_Data;
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alias TX_FIFO_Wr_Data is Wr_Data;
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signal TX_FIFO_Rd_En : std_logic := '0';
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signal TX_FIFO_Rd_En : std_logic := '0';
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signal TX_FIFO_Empty : std_logic := '0';
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signal TX_FIFO_Empty : std_logic := '0';
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signal TX_FIFO_AFull : std_logic := '0';
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signal TX_FIFO_AFull : std_logic := '0';
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signal TX_FIFO_Rd_Data : DATA_TYPE := x"00";
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signal TX_FIFO_Rd_Data : DATA_TYPE := x"00";
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alias Tx_Data is TX_FIFO_Rd_Data;
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alias Tx_Data is TX_FIFO_Rd_Data;
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type TX_CTRL_STATES is (IDLE, TX_BYTE, TX_START, TX_WAIT );
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type TX_CTRL_STATES is (IDLE, TX_BYTE, TX_START, TX_WAIT );
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signal TX_Ctrl : TX_CTRL_STATES := IDLE;
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signal TX_Ctrl : TX_CTRL_STATES := IDLE;
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signal TX_Xmit : std_logic := '0';
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signal TX_Xmit : std_logic := '0';
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signal TX_Done : std_logic := '0';
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signal TX_Done : std_logic := '0';
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constant BAUD_RATE_DIV : integer := integer(Sys_Freq / Bit_Rate);
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constant BAUD_RATE_DIV : integer := integer(Sys_Freq / Bit_Rate);
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signal CTS_sr : std_logic_vector(3 downto 0) := "0000";
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signal CTS_sr : std_logic_vector(3 downto 0) := "0000";
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alias CTS_Okay is CTS_sr(3);
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alias CTS_Okay is CTS_sr(3);
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signal RX_FIFO_Wr_En : std_logic := '0';
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signal RX_FIFO_Wr_En : std_logic := '0';
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signal RX_FIFO_Wr_Data : DATA_TYPE := x"00";
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signal RX_FIFO_Wr_Data : DATA_TYPE := x"00";
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signal RX_FIFO_Rd_En : std_logic := '0';
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signal RX_FIFO_Rd_En : std_logic := '0';
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signal RX_FIFO_Empty : std_logic := '0';
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signal RX_FIFO_Empty : std_logic := '0';
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signal RX_FIFO_AFull : std_logic := '0';
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signal RX_FIFO_AFull : std_logic := '0';
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signal RX_FIFO_Rd_Data : DATA_TYPE := x"00";
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signal RX_FIFO_Rd_Data : DATA_TYPE := x"00";
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begin
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begin
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Addr_Match <= '1' when Comp_Addr = User_Addr else '0';
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Addr_Match <= '1' when Comp_Addr = User_Addr else '0';
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io_reg: process( Clock, Reset )
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io_reg: process( Clock, Reset )
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begin
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begin
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if( Reset = Reset_Level )then
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if( Reset = Reset_Level )then
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Rd_En <= '0';
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Rd_En <= '0';
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Rd_Data <= OPEN8_NULLBUS;
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Rd_Data <= OPEN8_NULLBUS;
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RTS_Out <= '0';
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RTS_Out <= '0';
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elsif( rising_edge( Clock ) )then
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elsif( rising_edge( Clock ) )then
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Rd_Data <= OPEN8_NULLBUS;
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Rd_Data <= OPEN8_NULLBUS;
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Rd_En <= Rd_Enable and Addr_Match;
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Rd_En <= Rd_Enable and Addr_Match;
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Reg_Sel <= Reg_Addr;
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Reg_Sel <= Reg_Addr;
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if( Rd_En = '1' and Reg_Sel = '1' )then
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if( Rd_En = '1' and Reg_Sel = '1' )then
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Rd_Data(4) <= RX_FIFO_Empty;
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Rd_Data(4) <= RX_FIFO_Empty;
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Rd_Data(5) <= RX_FIFO_AFull;
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Rd_Data(5) <= RX_FIFO_AFull;
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Rd_Data(6) <= TX_FIFO_Empty;
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Rd_Data(6) <= TX_FIFO_Empty;
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Rd_Data(7) <= TX_FIFO_AFull;
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Rd_Data(7) <= TX_FIFO_AFull;
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end if;
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end if;
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if( Rd_En = '1' and Reg_Sel = '0' )then
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if( Rd_En = '1' and Reg_Sel = '0' )then
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Rd_Data <= RX_FIFO_Rd_Data;
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Rd_Data <= RX_FIFO_Rd_Data;
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end if;
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end if;
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RTS_Out <= not RX_FIFO_AFull;
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RTS_Out <= not RX_FIFO_AFull;
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end if;
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end if;
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end process;
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end process;
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TX_Disabled : if( Disable_Transmit )generate
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TX_FIFO_Empty <= '1';
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TX_FIFO_AFull <= '0';
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TX_Out <= '1';
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end generate;
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TX_Enabled : if( not Disable_Transmit )generate
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TX_FIFO_Wr_En <= Wr_Enable and Addr_Match and not Reg_Addr;
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TX_FIFO_Wr_En <= Wr_Enable and Addr_Match and not Reg_Addr;
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FIFO_Reset <= '1' when Reset = Reset_Level else '0';
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FIFO_Reset <= '1' when Reset = Reset_Level else '0';
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U_TX_FIFO : entity work.fifo_1k_core
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U_TX_FIFO : entity work.fifo_1k_core
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port map(
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port map(
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aclr => FIFO_Reset,
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aclr => FIFO_Reset,
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clock => Clock,
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clock => Clock,
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data => TX_FIFO_Wr_Data,
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data => TX_FIFO_Wr_Data,
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rdreq => TX_FIFO_Rd_En,
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rdreq => TX_FIFO_Rd_En,
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wrreq => TX_FIFO_Wr_En,
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wrreq => TX_FIFO_Wr_En,
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empty => TX_FIFO_Empty,
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empty => TX_FIFO_Empty,
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almost_full => TX_FIFO_AFull,
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almost_full => TX_FIFO_AFull,
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q => TX_FIFO_Rd_Data
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q => TX_FIFO_Rd_Data
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);
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);
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tx_FSM: process( Clock, Reset )
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tx_FSM: process( Clock, Reset )
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begin
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begin
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if( Reset = Reset_Level )then
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if( Reset = Reset_Level )then
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TX_Ctrl <= IDLE;
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TX_Ctrl <= IDLE;
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TX_Xmit <= '0';
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TX_Xmit <= '0';
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TX_FIFO_Rd_En <= '0';
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TX_FIFO_Rd_En <= '0';
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CTS_sr <= (others => '0');
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CTS_sr <= (others => '0');
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elsif( rising_edge(Clock) )then
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elsif( rising_edge(Clock) )then
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TX_Xmit <= '0';
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TX_Xmit <= '0';
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TX_FIFO_Rd_En <= '0';
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TX_FIFO_Rd_En <= '0';
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CTS_sr <= CTS_sr(2 downto 0) & CTS_In;
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CTS_sr <= CTS_sr(2 downto 0) & CTS_In;
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case( TX_Ctrl )is
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case( TX_Ctrl )is
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when IDLE =>
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when IDLE =>
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if( TX_FIFO_Empty = '0' and CTS_Okay = '1' )then
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if( TX_FIFO_Empty = '0' and CTS_Okay = '1' )then
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TX_FIFO_Rd_En <= '1';
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TX_FIFO_Rd_En <= '1';
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TX_Ctrl <= TX_BYTE;
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TX_Ctrl <= TX_BYTE;
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end if;
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end if;
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when TX_BYTE =>
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when TX_BYTE =>
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TX_Xmit <= '1';
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TX_Xmit <= '1';
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TX_Ctrl <= TX_START;
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TX_Ctrl <= TX_START;
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when TX_START =>
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when TX_START =>
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if( Tx_Done = '0' )then
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if( Tx_Done = '0' )then
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TX_Ctrl <= TX_WAIT;
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TX_Ctrl <= TX_WAIT;
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end if;
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end if;
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when TX_WAIT =>
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when TX_WAIT =>
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if( Tx_Done = '1' )then
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if( Tx_Done = '1' )then
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TX_Ctrl <= IDLE;
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TX_Ctrl <= IDLE;
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end if;
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end if;
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when others => null;
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when others => null;
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end case;
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end case;
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end if;
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end if;
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end process;
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end process;
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U_TX : entity work.async_ser_tx
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U_TX : entity work.async_ser_tx
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generic map(
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generic map(
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Reset_Level => Reset_Level,
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Reset_Level => Reset_Level,
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Enable_Parity => Enable_Parity,
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Enable_Parity => Enable_Parity,
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Parity_Odd_Even_n => Parity_Odd_Even_n,
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Parity_Odd_Even_n => Parity_Odd_Even_n,
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Clock_Divider => BAUD_RATE_DIV
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Clock_Divider => BAUD_RATE_DIV
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)
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)
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port map(
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port map(
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Clock => Clock,
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Clock => Clock,
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Reset => Reset,
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Reset => Reset,
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--
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--
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Tx_Data => Tx_Data,
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Tx_Data => Tx_Data,
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Tx_Valid => TX_Xmit,
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Tx_Valid => TX_Xmit,
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--
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--
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Tx_Out => TX_Out,
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Tx_Out => TX_Out,
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Tx_Done => Tx_Done
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Tx_Done => Tx_Done
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);
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);
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end generate;
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RX_Disabled : if( Disable_Transmit )generate
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RX_FIFO_Empty <= '1';
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RX_FIFO_AFull <= '0';
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RX_FIFO_Rd_Data <= x"00";
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end generate;
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RX_Enabled : if( not Disable_Receive )generate
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U_RX : entity work.async_ser_rx
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U_RX : entity work.async_ser_rx
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generic map(
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generic map(
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Reset_Level => Reset_Level,
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Reset_Level => Reset_Level,
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Enable_Parity => Enable_Parity,
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Enable_Parity => Enable_Parity,
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Parity_Odd_Even_n => Parity_Odd_Even_n,
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Parity_Odd_Even_n => Parity_Odd_Even_n,
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Clock_Divider => BAUD_RATE_DIV
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Clock_Divider => BAUD_RATE_DIV
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)
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)
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port map(
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port map(
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Clock => Clock,
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Clock => Clock,
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Reset => Reset,
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Reset => Reset,
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--
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--
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Rx_In => RX_In,
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Rx_In => RX_In,
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--
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--
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Rx_Data => RX_FIFO_Wr_Data,
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Rx_Data => RX_FIFO_Wr_Data,
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Rx_Valid => RX_FIFO_Wr_En,
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Rx_Valid => RX_FIFO_Wr_En,
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Rx_PErr => open
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Rx_PErr => open
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);
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);
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RX_FIFO_Rd_En <= Rd_Enable and Addr_Match and not Reg_Addr;
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RX_FIFO_Rd_En <= Rd_Enable and Addr_Match and not Reg_Addr;
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U_RX_FIFO : entity work.fifo_1k_core
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U_RX_FIFO : entity work.fifo_1k_core
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port map(
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port map(
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aclr => FIFO_Reset,
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aclr => FIFO_Reset,
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clock => Clock,
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clock => Clock,
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data => RX_FIFO_Wr_Data,
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data => RX_FIFO_Wr_Data,
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rdreq => RX_FIFO_Rd_En,
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rdreq => RX_FIFO_Rd_En,
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wrreq => RX_FIFO_Wr_En,
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wrreq => RX_FIFO_Wr_En,
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empty => RX_FIFO_Empty,
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empty => RX_FIFO_Empty,
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almost_full => RX_FIFO_AFull,
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almost_full => RX_FIFO_AFull,
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q => RX_FIFO_Rd_Data
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q => RX_FIFO_Rd_Data
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);
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);
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end generate;
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end architecture;
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end architecture;
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No newline at end of file
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No newline at end of file
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