-- Copyright (c)2020 Jeremy Seth Henry
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-- Copyright (c)2020 Jeremy Seth Henry
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-- All rights reserved.
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-- All rights reserved.
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--
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--
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-- Redistribution and use in source and binary forms, with or without
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-- Redistribution and use in source and binary forms, with or without
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-- modification, are permitted provided that the following conditions are met:
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-- modification, are permitted provided that the following conditions are met:
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-- * Redistributions of source code must retain the above copyright
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-- * Redistributions of source code must retain the above copyright
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-- notice, this list of conditions and the following disclaimer.
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-- notice, this list of conditions and the following disclaimer.
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-- * Redistributions in binary form must reproduce the above copyright
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-- * Redistributions in binary form must reproduce the above copyright
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-- notice, this list of conditions and the following disclaimer in the
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-- notice, this list of conditions and the following disclaimer in the
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-- documentation and/or other materials provided with the distribution,
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-- documentation and/or other materials provided with the distribution,
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-- where applicable (as part of a user interface, debugging port, etc.)
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-- where applicable (as part of a user interface, debugging port, etc.)
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--
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--
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-- THIS SOFTWARE IS PROVIDED BY JEREMY SETH HENRY ``AS IS'' AND ANY
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-- THIS SOFTWARE IS PROVIDED BY JEREMY SETH HENRY ``AS IS'' AND ANY
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-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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-- DISCLAIMED. IN NO EVENT SHALL JEREMY SETH HENRY BE LIABLE FOR ANY
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-- DISCLAIMED. IN NO EVENT SHALL JEREMY SETH HENRY BE LIABLE FOR ANY
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-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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-- THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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-- THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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--
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--
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-- VHDL Units : o8_crc16_ccitt
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-- VHDL Units : o8_crc16_ccitt
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-- Description: Implements the 16-bit CCITT CRC on byte-wide data suitable for
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-- Description: Implements the 16-bit CCITT CRC on byte-wide data suitable for
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-- : use with the Open8 CPU. Logic equations were taken from
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-- : use with the Open8 CPU. Logic equations were taken from
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-- : Intel/Altera app note AN049.
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-- : Intel/Altera app note AN049.
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--
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--
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-- Notes : Writing to the byte counter will reset all registers, and to
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-- Notes : Writing to the byte counter will reset all registers, and to
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-- : should be used to clear the CRC accumulator/byte counter
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-- : should be used to clear the CRC accumulator/byte counter
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-- : between frames.
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-- : between frames.
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--
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--
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-- Register Map:
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-- Register Map:
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-- Offset Bitfield Description Read/Write
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-- Offset Bitfield Description Read/Write
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-- 0x0 AAAAAAAA Data Input register (calc on write)(R/W)
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-- 0x0 AAAAAAAA Data Input register (calc on write)(R/W)
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-- 0x1 AAAAAAAA Byte Counter (clear all on write) (R/W)
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-- 0x1 AAAAAAAA Byte Counter (clear all on write) (R/W)
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-- 0x2 AAAAAAAA B0 of calculated CRC (RO)
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-- 0x2 AAAAAAAA B0 of calculated CRC (RO)
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-- 0x3 AAAAAAAA B1 of calculated CRC (RO)
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-- 0x3 AAAAAAAA B1 of calculated CRC (RO)
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--
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--
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-- Revision History
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-- Revision History
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-- Author Date Change
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-- Author Date Change
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------------------ -------- ---------------------------------------------------
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------------------ -------- ---------------------------------------------------
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-- Seth Henry 12/19/19 Design Start
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-- Seth Henry 12/19/19 Design Start
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-- Seth Henry 04/16/20 Modified to use Open8 bus record
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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library work;
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library work;
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use work.open8_pkg.all;
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use work.open8_pkg.all;
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entity o8_crc16_ccitt is
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entity o8_crc16_ccitt is
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generic(
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generic(
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Reset_Level : std_logic := '1';
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Address : ADDRESS_TYPE
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Address : ADDRESS_TYPE
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);
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);
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port(
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port(
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Clock : in std_logic;
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Reset : in std_logic;
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--
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Open8_Bus : in OPEN8_BUS_TYPE;
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Open8_Bus : in OPEN8_BUS_TYPE;
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Rd_Data : out DATA_TYPE
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Rd_Data : out DATA_TYPE
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);
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);
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end entity;
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end entity;
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architecture behave of o8_crc16_ccitt is
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architecture behave of o8_crc16_ccitt is
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alias Clock is Open8_Bus.Clock;
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alias Reset is Open8_Bus.Reset;
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constant Poly_Init : std_logic_vector(15 downto 0) :=
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constant Poly_Init : std_logic_vector(15 downto 0) :=
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(others => '0');
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(others => '0');
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constant User_Addr : std_logic_vector(15 downto 2)
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constant User_Addr : std_logic_vector(15 downto 2)
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:= Address(15 downto 2);
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:= Address(15 downto 2);
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alias Comp_Addr is Open8_Bus.Address(15 downto 2);
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alias Comp_Addr is Open8_Bus.Address(15 downto 2);
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alias Reg_Addr is Open8_Bus.Address(1 downto 0);
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alias Reg_Addr is Open8_Bus.Address(1 downto 0);
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signal Reg_Sel : std_logic_vector(1 downto 0) :=
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signal Reg_Sel : std_logic_vector(1 downto 0) :=
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(others => '0');
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(others => '0');
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signal Addr_Match : std_logic;
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signal Addr_Match : std_logic;
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signal Wr_En : std_logic;
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signal Wr_En : std_logic;
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signal Wr_Data_q : DATA_TYPE := (others => '0');
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signal Wr_Data_q : DATA_TYPE := (others => '0');
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signal Rd_En : std_logic;
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signal Rd_En : std_logic;
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signal Next_Byte : DATA_TYPE := (others => '0');
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signal Next_Byte : DATA_TYPE := (others => '0');
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signal Byte_Count : DATA_TYPE := (others => '0');
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signal Byte_Count : DATA_TYPE := (others => '0');
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signal Calc_En : std_logic := '0';
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signal Calc_En : std_logic := '0';
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signal Buffer_En : std_logic := '0';
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signal Buffer_En : std_logic := '0';
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signal Data : DATA_TYPE := (others => '0');
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signal Data : DATA_TYPE := (others => '0');
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signal Exr : DATA_TYPE := (others => '0');
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signal Exr : DATA_TYPE := (others => '0');
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signal Reg : std_logic_vector(15 downto 0) :=
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signal Reg : std_logic_vector(15 downto 0) :=
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(others => '0');
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(others => '0');
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signal Comp_Data : std_logic_vector(15 downto 0) :=
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signal Comp_Data : std_logic_vector(15 downto 0) :=
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(others => '0');
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(others => '0');
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begin
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begin
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Addr_Match <= '1' when Comp_Addr = User_Addr else '0';
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Addr_Match <= '1' when Comp_Addr = User_Addr else '0';
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Exr(0) <= Reg(0) xor Data(0);
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Exr(0) <= Reg(0) xor Data(0);
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Exr(1) <= Reg(1) xor Data(1);
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Exr(1) <= Reg(1) xor Data(1);
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Exr(2) <= Reg(2) xor Data(2);
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Exr(2) <= Reg(2) xor Data(2);
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Exr(3) <= Reg(3) xor Data(3);
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Exr(3) <= Reg(3) xor Data(3);
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Exr(4) <= Reg(4) xor Data(4);
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Exr(4) <= Reg(4) xor Data(4);
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Exr(5) <= Reg(5) xor Data(5);
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Exr(5) <= Reg(5) xor Data(5);
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Exr(6) <= Reg(6) xor Data(6);
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Exr(6) <= Reg(6) xor Data(6);
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Exr(7) <= Reg(7) xor Data(7);
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Exr(7) <= Reg(7) xor Data(7);
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CRC16_Calc: process( Clock, Reset )
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CRC16_Calc: process( Clock, Reset )
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begin
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begin
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if( Reset = Reset_Level )then
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if( Reset = Reset_Level )then
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Reg_Sel <= "00";
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Reg_Sel <= "00";
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Wr_En <= '0';
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Wr_En <= '0';
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Wr_Data_q <= x"00";
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Wr_Data_q <= x"00";
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Rd_En <= '0';
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Rd_En <= '0';
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Rd_Data <= OPEN8_NULLBUS;
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Rd_Data <= OPEN8_NULLBUS;
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Byte_Count <= x"00";
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Byte_Count <= x"00";
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Calc_En <= '0';
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Calc_En <= '0';
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Buffer_En <= '0';
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Buffer_En <= '0';
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Data <= x"00";
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Data <= x"00";
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Reg <= x"0000";
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Reg <= x"0000";
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elsif( rising_edge(Clock) )then
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elsif( rising_edge(Clock) )then
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Reg_Sel <= Reg_Addr;
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Reg_Sel <= Reg_Addr;
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Wr_En <= Addr_Match and Open8_Bus.Wr_En;
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Wr_En <= Addr_Match and Open8_Bus.Wr_En;
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Wr_Data_q <= Open8_Bus.Wr_Data;
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Wr_Data_q <= Open8_Bus.Wr_Data;
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if( Wr_En = '1' )then
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if( Wr_En = '1' )then
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case( Reg_Sel )is
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case( Reg_Sel )is
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when "00" => -- Load next byte
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when "00" => -- Load next byte
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Data <= Wr_Data_q;
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Data <= Wr_Data_q;
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Calc_En <= '1';
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Calc_En <= '1';
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when "01" => -- Clear accumulator and byte counter
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when "01" => -- Clear accumulator and byte counter
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Byte_Count <= x"00";
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Byte_Count <= x"00";
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Reg <= Poly_Init;
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Reg <= Poly_Init;
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when others => null;
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when others => null;
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end case;
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end case;
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end if;
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end if;
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Rd_En <= Addr_Match and Open8_Bus.Rd_En;
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Rd_En <= Addr_Match and Open8_Bus.Rd_En;
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Rd_Data <= OPEN8_NULLBUS;
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Rd_Data <= OPEN8_NULLBUS;
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if( Rd_En = '1' )then
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if( Rd_En = '1' )then
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case( Reg_Sel )is
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case( Reg_Sel )is
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when "00" => -- Read last byte
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when "00" => -- Read last byte
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Rd_Data <= Data;
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Rd_Data <= Data;
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when "01" => -- Read the byte counter
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when "01" => -- Read the byte counter
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Rd_Data <= Byte_Count;
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Rd_Data <= Byte_Count;
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when "10" => -- Read the lower byte of the calculated CRC
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when "10" => -- Read the lower byte of the calculated CRC
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Rd_Data <= Comp_Data(7 downto 0);
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Rd_Data <= Comp_Data(7 downto 0);
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when "11" => -- Read the upper byte of the calculated CRC
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when "11" => -- Read the upper byte of the calculated CRC
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Rd_Data <= Comp_Data(15 downto 8);
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Rd_Data <= Comp_Data(15 downto 8);
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when others => null;
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when others => null;
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end case;
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end case;
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end if;
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end if;
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Calc_En <= '0';
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Calc_En <= '0';
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Buffer_En <= Calc_En;
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Buffer_En <= Calc_En;
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if( Calc_En = '1' )then
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if( Calc_En = '1' )then
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Reg(0) <= Reg(8) xor Exr(4) xor Exr(0);
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Reg(0) <= Reg(8) xor Exr(4) xor Exr(0);
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Reg(1) <= Reg(9) xor Exr(5) xor Exr(1);
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Reg(1) <= Reg(9) xor Exr(5) xor Exr(1);
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Reg(2) <= Reg(10) xor Exr(6) xor Exr(2);
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Reg(2) <= Reg(10) xor Exr(6) xor Exr(2);
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Reg(3) <= Reg(11) xor Exr(0) xor Exr(7) xor Exr(3);
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Reg(3) <= Reg(11) xor Exr(0) xor Exr(7) xor Exr(3);
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Reg(4) <= Reg(12) xor Exr(1) ;
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Reg(4) <= Reg(12) xor Exr(1) ;
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Reg(5) <= Reg(13) xor Exr(2) ;
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Reg(5) <= Reg(13) xor Exr(2) ;
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Reg(6) <= Reg(14) xor Exr(3) ;
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Reg(6) <= Reg(14) xor Exr(3) ;
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Reg(7) <= Reg(15) xor Exr(4) xor Exr(0);
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Reg(7) <= Reg(15) xor Exr(4) xor Exr(0);
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Reg(8) <= Exr(0) xor Exr(5) xor Exr(1);
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Reg(8) <= Exr(0) xor Exr(5) xor Exr(1);
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Reg(9) <= Exr(1) xor Exr(6) xor Exr(2);
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Reg(9) <= Exr(1) xor Exr(6) xor Exr(2);
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Reg(10) <= Exr(2) xor Exr(7) xor Exr(3);
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Reg(10) <= Exr(2) xor Exr(7) xor Exr(3);
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Reg(11) <= Exr(3) ;
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Reg(11) <= Exr(3) ;
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Reg(12) <= Exr(4) xor Exr(0);
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Reg(12) <= Exr(4) xor Exr(0);
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Reg(13) <= Exr(5) xor Exr(1);
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Reg(13) <= Exr(5) xor Exr(1);
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Reg(14) <= Exr(6) xor Exr(2);
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Reg(14) <= Exr(6) xor Exr(2);
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Reg(15) <= Exr(7) xor Exr(3);
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Reg(15) <= Exr(7) xor Exr(3);
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end if;
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end if;
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if( Buffer_En = '1' )then
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if( Buffer_En = '1' )then
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Byte_Count <= Byte_Count + 1;
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Byte_Count <= Byte_Count + 1;
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Comp_Data <= Reg xor x"FFFF";
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Comp_Data <= Reg xor x"FFFF";
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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end architecture;
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end architecture;
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