-- Copyright (c)2006, 2016, 2019, 2020 Jeremy Seth Henry
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-- Copyright (c)2006, 2016, 2019, 2020 Jeremy Seth Henry
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-- All rights reserved.
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-- All rights reserved.
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--
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--
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-- Redistribution and use in source and binary forms, with or without
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-- Redistribution and use in source and binary forms, with or without
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-- modification, are permitted provided that the following conditions are met:
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-- modification, are permitted provided that the following conditions are met:
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-- * Redistributions of source code must retain the above copyright
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-- * Redistributions of source code must retain the above copyright
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-- notice, this list of conditions and the following disclaimer.
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-- notice, this list of conditions and the following disclaimer.
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-- * Redistributions in binary form must reproduce the above copyright
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-- * Redistributions in binary form must reproduce the above copyright
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-- notice, this list of conditions and the following disclaimer in the
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-- notice, this list of conditions and the following disclaimer in the
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-- documentation and/or other materials provided with the distribution,
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-- documentation and/or other materials provided with the distribution,
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-- where applicable (as part of a user interface, debugging port, etc.)
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-- where applicable (as part of a user interface, debugging port, etc.)
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--
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--
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-- THIS SOFTWARE IS PROVIDED BY JEREMY SETH HENRY ``AS IS'' AND ANY
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-- THIS SOFTWARE IS PROVIDED BY JEREMY SETH HENRY ``AS IS'' AND ANY
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-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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-- DISCLAIMED. IN NO EVENT SHALL JEREMY SETH HENRY BE LIABLE FOR ANY
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-- DISCLAIMED. IN NO EVENT SHALL JEREMY SETH HENRY BE LIABLE FOR ANY
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-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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-- THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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-- THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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--
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--
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-- VHDL Units : o8_datalatch
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-- VHDL Units : o8_datalatch
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-- Description: Latches a byte of external data and issues an interrupt on
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-- Description: Latches a byte of external data and issues an interrupt on
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-- capture.
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-- capture.
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--
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--
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--
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--
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-- Register Map:
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-- Register Map:
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-- Offset Bitfield Description Read/Write
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-- Offset Bitfield Description Read/Write
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-- 0x00 AAAAAAAA Latched Value (RW)
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-- 0x00 AAAAAAAA Latched Value (RW)
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--
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--
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-- Note: Cut the path between LData_q1 and L_Data for timing analysis
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-- Note: Cut the path between LData_q1 and L_Data for timing analysis
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--
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--
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-- Revision History
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-- Revision History
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-- Author Date Change
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-- Author Date Change
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------------------ -------- ---------------------------------------------------
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------------------ -------- ---------------------------------------------------
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-- Seth Henry 01/22/20 Design Start
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-- Seth Henry 01/22/20 Design Start
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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library work;
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library work;
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use work.open8_pkg.all;
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use work.open8_pkg.all;
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entity o8_datalatch is
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entity o8_datalatch is
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generic(
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generic(
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Reset_Level : std_logic;
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Reset_Level : std_logic;
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Address : ADDRESS_TYPE
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Address : ADDRESS_TYPE
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);
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);
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port(
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port(
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Clock : in std_logic;
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Clock : in std_logic;
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Reset : in std_logic;
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Reset : in std_logic;
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--
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--
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Bus_Address : in ADDRESS_TYPE;
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Bus_Address : in ADDRESS_TYPE;
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Rd_Enable : in std_logic;
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Rd_Enable : in std_logic;
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Rd_Data : out DATA_TYPE;
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Rd_Data : out DATA_TYPE;
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Interrupt : out std_logic;
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Interrupt : out std_logic;
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--
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--
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L_Strobe : in std_logic;
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L_Strobe : in std_logic;
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L_Data : in DATA_TYPE
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L_Data : in DATA_TYPE
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);
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);
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end entity;
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end entity;
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architecture behave of o8_datalatch is
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architecture behave of o8_datalatch is
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constant User_Addr : std_logic_vector(15 downto 0) := Address;
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constant User_Addr : std_logic_vector(15 downto 0) := Address;
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alias Comp_Addr is Bus_Address(15 downto 0);
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alias Comp_Addr is Bus_Address(15 downto 0);
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signal Addr_Match : std_logic;
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signal Addr_Match : std_logic;
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signal Rd_En : std_logic;
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signal Rd_En : std_logic;
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signal Strobe_sr : std_logic_vector(3 downto 0);
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signal Strobe_sr : std_logic_vector(3 downto 0);
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signal Strobe_re : std_logic;
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signal Strobe_re : std_logic;
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signal LData_q1 : DATA_TYPE;
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signal LData_q1 : DATA_TYPE;
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signal LData_q2 : DATA_TYPE;
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signal LData_q2 : DATA_TYPE;
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signal LData_q3 : DATA_TYPE;
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signal LData_q3 : DATA_TYPE;
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begin
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begin
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Addr_Match <= Rd_Enable when Comp_Addr = User_Addr else '0';
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Addr_Match <= Rd_Enable when Comp_Addr = User_Addr else '0';
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Strobe_re <= Strobe_sr(2) and not Strobe_sr(3);
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Strobe_re <= Strobe_sr(2) and not Strobe_sr(3);
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io_reg: process( Clock, Reset )
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io_reg: process( Clock, Reset )
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begin
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begin
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if( Reset = Reset_Level )then
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if( Reset = Reset_Level )then
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Rd_En <= '0';
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Rd_En <= '0';
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Rd_Data <= OPEN8_NULLBUS;
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Rd_Data <= OPEN8_NULLBUS;
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Strobe_sr <= (others => '0');
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Strobe_sr <= (others => '0');
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Interrupt <= '0';
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Interrupt <= '0';
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LData_q1 <= x"00";
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LData_q1 <= x"00";
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LData_q2 <= x"00";
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LData_q2 <= x"00";
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LData_q3 <= x"00";
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LData_q3 <= x"00";
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elsif( rising_edge( Clock ) )then
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elsif( rising_edge( Clock ) )then
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Strobe_sr <= Strobe_sr(2 downto 0) & L_Strobe;
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Strobe_sr <= Strobe_sr(2 downto 0) & L_Strobe;
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LData_q1 <= L_Data;
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LData_q1 <= L_Data;
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LData_q2 <= LData_q1;
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LData_q2 <= LData_q1;
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Interrupt <= Strobe_re;
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Interrupt <= Strobe_re;
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if( Strobe_re = '1' )then
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if( Strobe_re = '1' )then
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LData_q3 <= LData_q2;
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LData_q3 <= LData_q2;
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end if;
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end if;
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Rd_Data <= OPEN8_NULLBUS;
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Rd_Data <= OPEN8_NULLBUS;
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Rd_En <= Addr_Match;
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Rd_En <= Addr_Match;
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if( Rd_En = '1' )then
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if( Rd_En = '1' )then
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Rd_Data <= LData_q3;
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Rd_Data <= LData_q3;
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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end architecture;
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end architecture;
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