-- Copyright (c)2023 Jeremy Seth Henry
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-- Copyright (c)2023 Jeremy Seth Henry
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-- All rights reserved.
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-- All rights reserved.
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--
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--
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-- Redistribution and use in source and binary forms, with or without
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-- Redistribution and use in source and binary forms, with or without
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-- modification, are permitted provided that the following conditions are met:
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-- modification, are permitted provided that the following conditions are met:
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-- * Redistributions of source code must retain the above copyright
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-- * Redistributions of source code must retain the above copyright
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-- notice, this list of conditions and the following disclaimer.
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-- notice, this list of conditions and the following disclaimer.
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-- * Redistributions in binary form must reproduce the above copyright
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-- * Redistributions in binary form must reproduce the above copyright
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-- notice, this list of conditions and the following disclaimer in the
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-- notice, this list of conditions and the following disclaimer in the
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-- documentation and/or other materials provided with the distribution,
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-- documentation and/or other materials provided with the distribution,
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-- where applicable (as part of a user interface, debugging port, etc.)
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-- where applicable (as part of a user interface, debugging port, etc.)
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--
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--
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-- THIS SOFTWARE IS PROVIDED BY JEREMY SETH HENRY ``AS IS'' AND ANY
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-- THIS SOFTWARE IS PROVIDED BY JEREMY SETH HENRY ``AS IS'' AND ANY
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-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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-- DISCLAIMED. IN NO EVENT SHALL JEREMY SETH HENRY BE LIABLE FOR ANY
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-- DISCLAIMED. IN NO EVENT SHALL JEREMY SETH HENRY BE LIABLE FOR ANY
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-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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-- THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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-- THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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--
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--
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-- VHDL units : o8_de0_nano_adc_if
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-- VHDL units : o8_de0_nano_adc_if
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-- Description: Stitches together all of the components needed to supply data
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-- Description: Stitches together all of the components needed to supply data
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-- from the DE0 nano's on-board ADC. Provides an interrupt output
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-- from the DE0 nano's on-board ADC. Provides an interrupt output
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-- when the 8th (last) input is written to the buffer.
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-- when the 8th (last) input is written to the buffer.
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--
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--
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-- Register Map:
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-- Register Map:
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-- Offset Bitfield Description Read/Write
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-- Offset Bitfield Description Read/Write
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-- 0x00 AAAAAAAA AFE 0, Channel 0, Lower Byte RO
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-- 0x00 AAAAAAAA AFE 0, Channel 0, Lower Byte RO
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-- 0x01 AAAAAAAA AFE 0, Channel 0, Upper Byte RO
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-- 0x01 AAAAAAAA AFE 0, Channel 0, Upper Byte RO
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-- 0x02 AAAAAAAA AFE 0, Channel 1, Lower Byte RO
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-- 0x02 AAAAAAAA AFE 0, Channel 1, Lower Byte RO
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-- 0x03 AAAAAAAA AFE 0, Channel 1, Upper Byte RO
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-- 0x03 AAAAAAAA AFE 0, Channel 1, Upper Byte RO
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-- 0x04 AAAAAAAA AFE 0, Channel 2, Lower Byte RO
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-- 0x04 AAAAAAAA AFE 0, Channel 2, Lower Byte RO
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-- 0x05 AAAAAAAA AFE 0, Channel 2, Upper Byte RO
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-- 0x05 AAAAAAAA AFE 0, Channel 2, Upper Byte RO
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-- 0x06 AAAAAAAA AFE 0, Channel 3, Lower Byte RO
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-- 0x06 AAAAAAAA AFE 0, Channel 3, Lower Byte RO
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-- 0x07 AAAAAAAA AFE 0, Channel 3, Upper Byte RO
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-- 0x07 AAAAAAAA AFE 0, Channel 3, Upper Byte RO
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-- 0x08 AAAAAAAA AFE 0, Channel 4, Lower Byte RO
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-- 0x08 AAAAAAAA AFE 0, Channel 4, Lower Byte RO
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-- 0x09 AAAAAAAA AFE 0, Channel 4, Upper Byte RO
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-- 0x09 AAAAAAAA AFE 0, Channel 4, Upper Byte RO
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-- 0x0A AAAAAAAA AFE 0, Channel 5, Lower Byte RO
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-- 0x0A AAAAAAAA AFE 0, Channel 5, Lower Byte RO
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-- 0x0B AAAAAAAA AFE 0, Channel 5, Upper Byte RO
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-- 0x0B AAAAAAAA AFE 0, Channel 5, Upper Byte RO
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-- 0x0C AAAAAAAA AFE 0, Channel 6, Lower Byte RO
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-- 0x0C AAAAAAAA AFE 0, Channel 6, Lower Byte RO
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-- 0x0D AAAAAAAA AFE 0, Channel 6, Upper Byte RO
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-- 0x0D AAAAAAAA AFE 0, Channel 6, Upper Byte RO
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-- 0x0E AAAAAAAA AFE 0, Channel 7, Lower Byte RO
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-- 0x0E AAAAAAAA AFE 0, Channel 7, Lower Byte RO
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-- 0x0F AAAAAAAA AFE 0, Channel 7, Upper Byte RO
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-- 0x0F AAAAAAAA AFE 0, Channel 7, Upper Byte RO
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--
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--
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-- Revision History
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-- Revision History
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-- Author Date Change
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-- Author Date Change
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------------------ -------- ---------------------------------------------------
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------------------ -------- ---------------------------------------------------
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-- Seth Henry 05/18/23 Initial Upload
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-- Seth Henry 05/18/23 Initial Upload
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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library work;
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library work;
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use work.open8_pkg.all;
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use work.open8_pkg.all;
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use work.open8_cfg.all;
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use work.open8_cfg.all;
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entity o8_de0_nano_adc_if is
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entity o8_de0_nano_adc_if is
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generic(
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generic(
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Address : ADDRESS_TYPE
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Address : ADDRESS_TYPE
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);
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);
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port(
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port(
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-- Bus IF Interface
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-- Bus IF Interface
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Open8_Bus : in OPEN8_BUS_TYPE;
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Open8_Bus : in OPEN8_BUS_TYPE;
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Rd_Data : out DATA_TYPE;
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Rd_Data : out DATA_TYPE;
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Interrupt : out std_logic;
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Interrupt : out std_logic;
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-- ADC IF
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-- ADC IF
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ADC_SDO : in std_logic;
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ADC_SDO : in std_logic;
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ADC_SDI : out std_logic;
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ADC_SDI : out std_logic;
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ADC_SCLK : out std_logic;
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ADC_SCLK : out std_logic;
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ADC_CSn : out std_logic
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ADC_CSn : out std_logic
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);
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);
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end entity;
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end entity;
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architecture behave of o8_de0_nano_adc_if is
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architecture behave of o8_de0_nano_adc_if is
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-- Bus Interface Signals
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-- Bus Interface Signals
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alias Clock is Open8_Bus.Clock;
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alias Clock is Open8_Bus.Clock;
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alias Reset is Open8_Bus.Reset;
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alias Reset is Open8_Bus.Reset;
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alias uSec_Tick is Open8_Bus.uSec_Tick;
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alias uSec_Tick is Open8_Bus.uSec_Tick;
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signal Reinit : std_logic := '0';
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signal RAW_Channel : std_logic_vector(2 downto 0) := (others => '0');
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signal RAW_Channel : std_logic_vector(2 downto 0) := (others => '0');
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signal RAW_Data : std_logic_vector(15 downto 0) := (others => '0');
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signal RAW_Data : std_logic_vector(15 downto 0) := (others => '0');
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signal RAW_Valid : std_logic := '0';
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signal RAW_Valid : std_logic := '0';
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signal AVG_Busy : std_logic := '0';
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signal AVG_Busy : std_logic := '0';
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signal AVG_Channel : std_logic_vector(2 downto 0) := (others => '0');
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signal AVG_Channel : std_logic_vector(2 downto 0) := (others => '0');
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signal AVG_Data : std_logic_vector(15 downto 0) := (others => '0');
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signal AVG_Data : std_logic_vector(15 downto 0) := (others => '0');
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signal AVG_Valid : std_logic := '0';
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signal AVG_Valid : std_logic := '0';
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alias Buf_Wr_Ptr is AVG_Channel;
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alias Buf_Wr_Ptr is AVG_Channel;
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alias Buf_Wr_Data is AVG_Data;
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alias Buf_Wr_Data is AVG_Data;
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alias Buf_Wr_Valid is AVG_Valid;
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alias Buf_Wr_Valid is AVG_Valid;
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alias Buf_Rd_Ptr is Open8_Bus.Address(3 downto 0);
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alias Buf_Rd_Ptr is Open8_Bus.Address(3 downto 0);
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signal Buf_Rd_Data : std_logic_vector(7 downto 0) := (others => '0');
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signal Buf_Rd_Data : std_logic_vector(7 downto 0) := (others => '0');
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constant LAST_ADDR : std_logic_vector(2 downto 0) := (others => '1');
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constant LAST_ADDR : std_logic_vector(2 downto 0) := (others => '1');
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signal Last_Sample : std_logic := '0';
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signal Last_Sample : std_logic := '0';
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constant User_Addr : std_logic_vector(15 downto 4) :=
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constant User_Addr : std_logic_vector(15 downto 4) :=
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Address(15 downto 4);
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Address(15 downto 4);
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alias Comp_Addr is Open8_Bus.Address(15 downto 4);
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alias Comp_Addr is Open8_Bus.Address(15 downto 4);
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signal Addr_Match : std_logic := '0';
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signal Addr_Match : std_logic := '0';
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signal Rd_En : std_logic := '0';
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signal Rd_En : std_logic := '0';
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begin
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begin
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- ADC0 - Interface
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-- ADC0 - Interface
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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U_ADC0 : entity work.adc12s022
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U_ADC0 : entity work.adc12s022
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generic map(
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generic map(
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Clock_Frequency => Clock_Frequency,
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Clock_Frequency => Clock_Frequency,
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Reset_Level => Reset_Level
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Reset_Level => Reset_Level
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)
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)
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port map(
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port map(
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Clock => Clock,
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Clock => Clock,
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Reset => Reset,
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Reset => Reset,
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--
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--
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Reinit => Reinit,
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--
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RAW_Channel => RAW_Channel,
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RAW_Channel => RAW_Channel,
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RAW_Data => RAW_Data,
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RAW_Data => RAW_Data,
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RAW_Valid => RAW_Valid,
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RAW_Valid => RAW_Valid,
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--
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--
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Busy_In => AVG_Busy,
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Busy_In => AVG_Busy,
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--
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--
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SDO => ADC_SDO,
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SDO => ADC_SDO,
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SDI => ADC_SDI,
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SDI => ADC_SDI,
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SCLK => ADC_SCLK,
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SCLK => ADC_SCLK,
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CSn => ADC_CSn
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CSn => ADC_CSn
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);
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);
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U_AVG0 : entity work.mavg_8ch_16b_64d
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U_AVG0 : entity work.mavg_8ch_16b_64d
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generic map(
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generic map(
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Reset_Level => Reset_Level
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Reset_Level => Reset_Level
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)
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)
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port map(
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port map(
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Clock => Clock,
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Clock => Clock,
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Reset => Reset,
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Reset => Reset,
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--
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--
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RAW_Channel => RAW_Channel,
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RAW_Channel => RAW_Channel,
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RAW_Data => RAW_Data,
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RAW_Data => RAW_Data,
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RAW_Valid => RAW_Valid,
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RAW_Valid => RAW_Valid,
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--
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--
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Busy_Out => AVG_Busy,
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Busy_Out => AVG_Busy,
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--
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--
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AVG_Channel => AVG_Channel,
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AVG_Channel => AVG_Channel,
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AVG_Out => AVG_Data,
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AVG_Out => AVG_Data,
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AVG_Valid => AVG_Valid,
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AVG_Valid => AVG_Valid,
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--
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--
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Busy_In => '0'
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Busy_In => '0'
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);
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);
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Buffer Storage
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-- Buffer Storage
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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U_DBUF : entity work.adc_buffer
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U_DBUF : entity work.adc_buffer
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port map(
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port map(
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clock => Clock,
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clock => Clock,
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data => Buf_Wr_Data,
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data => Buf_Wr_Data,
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rdaddress => Buf_Rd_Ptr,
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rdaddress => Buf_Rd_Ptr,
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wraddress => Buf_Wr_Ptr,
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wraddress => Buf_Wr_Ptr,
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wren => Buf_Wr_Valid,
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wren => Buf_Wr_Valid,
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q => Buf_Rd_Data
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q => Buf_Rd_Data
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);
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);
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U_DMON : entity work.adc_monitor
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U_DMON : entity work.adc_monitor
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port map(
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port map(
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address => Buf_Wr_Ptr,
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address => Buf_Wr_Ptr,
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clock => Clock,
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clock => Clock,
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data => Buf_Wr_Data,
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data => Buf_Wr_Data,
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wren => Buf_Wr_Valid,
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wren => Buf_Wr_Valid,
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q => open
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q => open
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);
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);
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Addr_Match <= Open8_Bus.Rd_En when Comp_Addr = User_Addr else
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Addr_Match <= Open8_Bus.Rd_En when Comp_Addr = User_Addr else
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'0';
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'0';
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Last_Sample <= Buf_Wr_Valid when Buf_Wr_Ptr = LAST_ADDR else '0';
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Last_Sample <= Buf_Wr_Valid when Buf_Wr_Ptr = LAST_ADDR else '0';
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RAM_proc: process( Reset, Clock )
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RAM_proc: process( Reset, Clock )
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begin
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begin
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if( Reset = Reset_Level )then
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if( Reset = Reset_Level )then
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Interrupt <= '0';
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Interrupt <= '0';
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Rd_En <= '0';
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Rd_En <= '0';
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Rd_Data <= OPEN8_NULLBUS;
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Rd_Data <= OPEN8_NULLBUS;
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elsif( rising_edge(Clock) )then
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elsif( rising_edge(Clock) )then
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Interrupt <= Last_Sample;
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Interrupt <= Last_Sample;
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Rd_En <= Addr_Match;
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Rd_En <= Addr_Match;
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Rd_Data <= OPEN8_NULLBUS;
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Rd_Data <= OPEN8_NULLBUS;
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if( Rd_En = '1' )then
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if( Rd_En = '1' )then
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Rd_Data <= Buf_Rd_Data;
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Rd_Data <= Buf_Rd_Data;
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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