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-- Copyright (c)2013, 2020 Jeremy Seth Henry
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-- All rights reserved.
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--
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-- Redistribution and use in source and binary forms, with or without
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-- modification, are permitted provided that the following conditions are met:
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-- * Redistributions of source code must retain the above copyright
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-- notice, this list of conditions and the following disclaimer.
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-- * Redistributions in binary form must reproduce the above copyright
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-- notice, this list of conditions and the following disclaimer in the
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-- documentation and/or other materials provided with the distribution,
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-- where applicable (as part of a user interface, debugging port, etc.)
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--
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-- THIS SOFTWARE IS PROVIDED BY JEREMY SETH HENRY ``AS IS'' AND ANY
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-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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-- DISCLAIMED. IN NO EVENT SHALL JEREMY SETH HENRY BE LIABLE FOR ANY
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-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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--
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-- VHDL Entity: o8_hd44780_8b
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-- VHDL Entity: o8_hd44780_8b
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-- Description: Provides low-level access to a "standard" character LCD using
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-- Description: Provides low-level access to a "standard" character LCD using
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-- the ST/HD44780(U) control ASIC wired in full (8-bit) mode.
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-- the ST/HD44780(U) control ASIC wired in full (8-bit) mode.
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-- All low-level timing of the control signals are handled by this
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-- All low-level timing of the control signals are handled by this
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-- module, allowing client firmware to use a simple register
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-- module, allowing client firmware to use a simple register
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-- interface to program the LCD panel.
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-- interface to program the LCD panel.
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-- Init routine initializes the display and displays a single
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-- Init routine initializes the display and displays a single
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-- character to demonstrate correct function, then listens for
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-- character to demonstrate correct function, then listens for
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-- user data on its external interface.
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-- user data on its external interface.
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_arith.all;
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library work;
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library work;
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use work.open8_pkg.all;
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use work.open8_pkg.all;
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entity o8_hd44780_8b is
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entity o8_hd44780_8b is
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generic(
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generic(
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Use_Contrast : boolean;
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Use_Contrast : boolean;
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Default_Contrast : std_logic_vector(7 downto 0);
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Default_Contrast : std_logic_vector(7 downto 0);
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Use_Backlight : boolean;
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Use_Backlight : boolean;
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Default_Brightness : std_logic_vector(7 downto 0);
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Default_Brightness : std_logic_vector(7 downto 0);
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Address : ADDRESS_TYPE;
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Address : ADDRESS_TYPE;
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Reset_Level : std_logic;
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Reset_Level : std_logic;
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Sys_Freq : real
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Sys_Freq : real
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);
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);
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port(
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port(
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Clock : in std_logic;
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Clock : in std_logic;
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Reset : in std_logic;
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Reset : in std_logic;
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uSec_Tick : in std_logic;
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uSec_Tick : in std_logic;
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--
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--
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Bus_Address : in ADDRESS_TYPE;
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Bus_Address : in ADDRESS_TYPE;
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Wr_Enable : in std_logic;
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Wr_Enable : in std_logic;
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Wr_Data : in DATA_TYPE;
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Wr_Data : in DATA_TYPE;
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Rd_Enable : in std_logic;
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Rd_Enable : in std_logic;
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Rd_Data : out DATA_TYPE;
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Rd_Data : out DATA_TYPE;
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Interrupt : out std_logic;
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Interrupt : out std_logic;
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--
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--
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LCD_E : out std_logic;
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LCD_E : out std_logic;
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LCD_RW : out std_logic;
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LCD_RW : out std_logic;
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LCD_RS : out std_logic;
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LCD_RS : out std_logic;
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LCD_D : out std_logic_vector(7 downto 0);
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LCD_D : out std_logic_vector(7 downto 0);
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LCD_CN : out std_logic;
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LCD_CN : out std_logic;
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LCD_BL : out std_logic
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LCD_BL : out std_logic
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);
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);
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end entity;
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end entity;
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architecture behave of o8_hd44780_8b is
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architecture behave of o8_hd44780_8b is
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constant User_Addr : std_logic_vector(15 downto 2)
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constant User_Addr : std_logic_vector(15 downto 2)
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:= Address(15 downto 2);
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:= Address(15 downto 2);
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alias Comp_Addr is Bus_Address(15 downto 2);
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alias Comp_Addr is Bus_Address(15 downto 2);
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signal Addr_Match : std_logic := '0';
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signal Addr_Match : std_logic := '0';
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alias Reg_Addr is Bus_Address(1 downto 0);
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alias Reg_Addr is Bus_Address(1 downto 0);
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signal Reg_Addr_q : std_logic_vector(1 downto 0) := (others => '0');
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signal Reg_Addr_q : std_logic_vector(1 downto 0) := (others => '0');
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signal Wr_En : std_logic := '0';
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signal Wr_En : std_logic := '0';
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signal Wr_Data_q : DATA_TYPE := x"00";
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signal Wr_Data_q : DATA_TYPE := x"00";
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signal Rd_En : std_logic := '0';
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signal Rd_En : std_logic := '0';
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signal Reg_Valid : std_logic := '0';
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signal Reg_Valid : std_logic := '0';
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signal Reg_Sel : std_logic := '0';
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signal Reg_Sel : std_logic := '0';
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signal Reg_Data : DATA_TYPE := x"00";
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signal Reg_Data : DATA_TYPE := x"00";
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signal Tx_Ready : std_logic;
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signal Tx_Ready : std_logic;
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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-- LCD Controller
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-- LCD Controller
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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-- Register Map
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-- Register Map
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-- Address Function
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-- Address Function
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-- Offset Bitfield Description Read/Write
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-- Offset Bitfield Description Read/Write
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-- 0x0 AAAAAAAA LCD Register Write (Write-only)
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-- 0x0 AAAAAAAA LCD Register Write (Write-only)
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-- 0x1 AAAAAAAA LCD Data Write (Write-only)
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-- 0x1 AAAAAAAA LCD Data Write (Write-only)
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-- 0x2 AAAAAAAA LCD Contrast (Read-Write)
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-- 0x2 AAAAAAAA LCD Contrast (Read-Write)
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-- 0x3 AAAAAAAA LCD Backlight (Read-Write)
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-- 0x3 AAAAAAAA LCD Backlight (Read-Write)
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-- LCD Instruction Set
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-- LCD Instruction Set
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-- Instruction RS RW D7 D6 D5 D4 D3 D2 D1 D0 Time
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-- Instruction RS RW D7 D6 D5 D4 D3 D2 D1 D0 Time
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------------------------------------------------------------------------
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------------------------------------------------------------------------
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-- Clear Display | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1.52mS
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-- Clear Display | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1.52mS
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-- Return Home | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | x | 1.52mS
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-- Return Home | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | x | 1.52mS
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-- Entry Mode | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | ID| S | 37uS
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-- Entry Mode | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | ID| S | 37uS
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-- Display Pwr | 0 | 0 | 0 | 0 | 0 | 0 | 1 | D | C | B | 37uS
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-- Display Pwr | 0 | 0 | 0 | 0 | 0 | 0 | 1 | D | C | B | 37uS
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-- Cursor/Display Shift | 0 | 0 | 0 | 0 | 0 | 1 | SC| RL| x | x | 37uS
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-- Cursor/Display Shift | 0 | 0 | 0 | 0 | 0 | 1 | SC| RL| x | x | 37uS
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-- Function Set | 0 | 0 | 0 | 0 | 1 | DL| N | F | x | x | 37uS
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-- Function Set | 0 | 0 | 0 | 0 | 1 | DL| N | F | x | x | 37uS
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-- Set CGRAM Address | 0 | 0 | 0 | 1 | A | A | A | A | A | A | 37uS
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-- Set CGRAM Address | 0 | 0 | 0 | 1 | A | A | A | A | A | A | 37uS
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-- Set DDRAM Address | 0 | 0 | 1 | A | A | A | A | A | A | A | 37uS
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-- Set DDRAM Address | 0 | 0 | 1 | A | A | A | A | A | A | A | 37uS
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-- Notes:
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-- Notes:
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-- ID = Increment/Decrement DDRAM Address (1 = increment, 0 = decrement)
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-- ID = Increment/Decrement DDRAM Address (1 = increment, 0 = decrement)
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-- S = Shift Enable (1 = Shift display according to ID, 0 = Don't shift)
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-- S = Shift Enable (1 = Shift display according to ID, 0 = Don't shift)
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-- D = Display On/Off (1 = on, 0 = off)
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-- D = Display On/Off (1 = on, 0 = off)
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-- C = Cursor On/Off (1 = on, 0 = off)
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-- C = Cursor On/Off (1 = on, 0 = off)
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-- B = Cursor Blink (1 = block cursor, 0 = underline cursor)
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-- B = Cursor Blink (1 = block cursor, 0 = underline cursor)
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-- SC / RL = Shift Cursor/Display Right/Left (see data sheet - not needed for init)
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-- SC / RL = Shift Cursor/Display Right/Left (see data sheet - not needed for init)
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-- F = Font (0 = 5x8, 1 = 5x11) Ignored on 2-line displays (N = 1)
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-- F = Font (0 = 5x8, 1 = 5x11) Ignored on 2-line displays (N = 1)
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-- N = Number of Lines (0 = 1 lines, 1 = 2 lines)
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-- N = Number of Lines (0 = 1 lines, 1 = 2 lines)
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-- DL = Data Length (0 = 4-bit bus, 1 = 8-bit bus) This is fixed at 1 in this module
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-- DL = Data Length (0 = 4-bit bus, 1 = 8-bit bus) This is fixed at 1 in this module
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-- A = Address (see data sheet for usage)
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-- A = Address (see data sheet for usage)
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constant LCD_CONFIG1 : std_logic_vector(7 downto 0) := x"38"; -- Set 4-bit, 2-line mode
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constant LCD_CONFIG1 : std_logic_vector(7 downto 0) := x"38"; -- Set 4-bit, 2-line mode
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constant LCD_CONFIG2 : std_logic_vector(7 downto 0) := x"0C"; -- Turn display on, no cursor
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constant LCD_CONFIG2 : std_logic_vector(7 downto 0) := x"0C"; -- Turn display on, no cursor
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constant LCD_CONFIG3 : std_logic_vector(7 downto 0) := x"01"; -- Clear display
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constant LCD_CONFIG3 : std_logic_vector(7 downto 0) := x"01"; -- Clear display
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constant LCD_CONFIG4 : std_logic_vector(7 downto 0) := x"06"; -- Positive increment, no shift
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constant LCD_CONFIG4 : std_logic_vector(7 downto 0) := x"06"; -- Positive increment, no shift
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constant LCD_CONFIG5 : std_logic_vector(7 downto 0) := x"2A"; -- Print a "*"
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constant LCD_CONFIG5 : std_logic_vector(7 downto 0) := x"2A"; -- Print a "*"
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constant LCD_CONFIG6 : std_logic_vector(7 downto 0) := x"02"; -- Reset the cursor
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constant LCD_CONFIG6 : std_logic_vector(7 downto 0) := x"02"; -- Reset the cursor
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signal init_count : std_logic_vector(2 downto 0) := (others => '0');
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signal init_count : std_logic_vector(2 downto 0) := (others => '0');
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constant INIT_40MS : integer := 40000;
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constant INIT_40MS : integer := 40000;
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constant INIT_BITS : integer := ceil_log2(INIT_40MS);
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constant INIT_BITS : integer := ceil_log2(INIT_40MS);
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constant INIT_DELAY : std_logic_vector(INIT_BITS-1 downto 0) :=
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constant INIT_DELAY : std_logic_vector(INIT_BITS-1 downto 0) :=
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conv_std_logic_vector(INIT_40MS,INIT_BITS);
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conv_std_logic_vector(INIT_40MS,INIT_BITS);
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-- For "long" instructions, such as clear display and return home, we need to wait for more
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-- For "long" instructions, such as clear display and return home, we need to wait for more
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-- than 1.52mS. Experimentally, 2mS seems to work ideally, and for init this isn't an issue
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-- than 1.52mS. Experimentally, 2mS seems to work ideally, and for init this isn't an issue
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constant CLDSP_2MS : integer := 2000;
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constant CLDSP_2MS : integer := 2000;
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constant CLDSP_DELAY : std_logic_vector(INIT_BITS-1 downto 0) :=
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constant CLDSP_DELAY : std_logic_vector(INIT_BITS-1 downto 0) :=
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conv_std_logic_vector(CLDSP_2MS,INIT_BITS);
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conv_std_logic_vector(CLDSP_2MS,INIT_BITS);
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-- For some reason, we are required to wait 80uS before checking the busy flag, despite
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-- For some reason, we are required to wait 80uS before checking the busy flag, despite
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-- most instructions completing in 37uS. No clue as to why, but it works
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-- most instructions completing in 37uS. No clue as to why, but it works
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constant BUSY_50US : integer := 50;
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constant BUSY_50US : integer := 50;
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constant BUSY_DELAY : std_logic_vector(INIT_BITS-1 downto 0) :=
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constant BUSY_DELAY : std_logic_vector(INIT_BITS-1 downto 0) :=
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conv_std_logic_vector(BUSY_50US-1, INIT_BITS);
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conv_std_logic_vector(BUSY_50US-1, INIT_BITS);
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signal busy_timer : std_logic_vector(INIT_BITS-1 downto 0) := (others => '0');
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signal busy_timer : std_logic_vector(INIT_BITS-1 downto 0) := (others => '0');
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constant SNH_600NS : integer := integer(Sys_Freq * 0.000000600);
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constant SNH_600NS : integer := integer(Sys_Freq * 0.000000600);
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constant SNH_BITS : integer := ceil_log2(SNH_600NS);
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constant SNH_BITS : integer := ceil_log2(SNH_600NS);
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constant SNH_DELAY : std_logic_vector(SNH_BITS-1 downto 0) :=
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constant SNH_DELAY : std_logic_vector(SNH_BITS-1 downto 0) :=
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conv_std_logic_vector(SNH_600NS-1, SNH_BITS);
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conv_std_logic_vector(SNH_600NS-1, SNH_BITS);
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signal io_timer : std_logic_vector(SNH_BITS - 1 downto 0) := (others => '0');
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signal io_timer : std_logic_vector(SNH_BITS - 1 downto 0) := (others => '0');
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type IO_STATES is (INIT, FN_JUMP, IDLE,
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type IO_STATES is (INIT, FN_JUMP, IDLE,
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WR_PREP, WR_SETUP, WR_HOLD,
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WR_PREP, WR_SETUP, WR_HOLD,
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BUSY_PREP, BUSY_WAIT,
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BUSY_PREP, BUSY_WAIT,
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ISSUE_INT );
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ISSUE_INT );
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signal io_state : IO_STATES;
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signal io_state : IO_STATES;
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signal LCD_Data : std_logic_vector(7 downto 0) := x"00";
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signal LCD_Data : std_logic_vector(7 downto 0) := x"00";
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signal LCD_Addr : std_logic := '0';
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signal LCD_Addr : std_logic := '0';
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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-- Backlight & Contrast signals
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-- Backlight & Contrast signals
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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-- Do not adjust alone! DELTA constants must be
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-- Do not adjust alone! DELTA constants must be
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-- changed as well.
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-- changed as well.
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constant DAC_Width : integer := 8;
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constant DAC_Width : integer := 8;
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constant DELTA_1_I : integer := 1;
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constant DELTA_1_I : integer := 1;
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constant DELTA_2_I : integer := 5;
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constant DELTA_2_I : integer := 5;
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constant DELTA_3_I : integer := 25;
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constant DELTA_3_I : integer := 25;
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constant DELTA_4_I : integer := 75;
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constant DELTA_4_I : integer := 75;
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constant DELTA_5_I : integer := 125;
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constant DELTA_5_I : integer := 125;
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constant DELTA_6_I : integer := 195;
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constant DELTA_6_I : integer := 195;
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constant DELTA_1 : std_logic_vector(DAC_Width-1 downto 0) :=
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constant DELTA_1 : std_logic_vector(DAC_Width-1 downto 0) :=
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conv_std_logic_vector(DELTA_1_I, DAC_Width);
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conv_std_logic_vector(DELTA_1_I, DAC_Width);
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constant DELTA_2 : std_logic_vector(DAC_Width-1 downto 0) :=
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constant DELTA_2 : std_logic_vector(DAC_Width-1 downto 0) :=
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conv_std_logic_vector(DELTA_2_I, DAC_Width);
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conv_std_logic_vector(DELTA_2_I, DAC_Width);
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constant DELTA_3 : std_logic_vector(DAC_Width-1 downto 0) :=
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constant DELTA_3 : std_logic_vector(DAC_Width-1 downto 0) :=
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conv_std_logic_vector(DELTA_3_I, DAC_Width);
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conv_std_logic_vector(DELTA_3_I, DAC_Width);
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constant DELTA_4 : std_logic_vector(DAC_Width-1 downto 0) :=
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constant DELTA_4 : std_logic_vector(DAC_Width-1 downto 0) :=
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conv_std_logic_vector(DELTA_4_I, DAC_Width);
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conv_std_logic_vector(DELTA_4_I, DAC_Width);
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constant DELTA_5 : std_logic_vector(DAC_Width-1 downto 0) :=
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constant DELTA_5 : std_logic_vector(DAC_Width-1 downto 0) :=
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conv_std_logic_vector(DELTA_5_I, DAC_Width);
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conv_std_logic_vector(DELTA_5_I, DAC_Width);
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constant DELTA_6 : std_logic_vector(DAC_Width-1 downto 0) :=
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constant DELTA_6 : std_logic_vector(DAC_Width-1 downto 0) :=
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conv_std_logic_vector(DELTA_6_I, DAC_Width);
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conv_std_logic_vector(DELTA_6_I, DAC_Width);
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constant MAX_PERIOD : integer := 2**DAC_Width;
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constant MAX_PERIOD : integer := 2**DAC_Width;
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constant DIV_WIDTH : integer := DAC_Width * 2;
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constant DIV_WIDTH : integer := DAC_Width * 2;
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constant PADJ_1_I : integer := DELTA_1_I * MAX_PERIOD;
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constant PADJ_1_I : integer := DELTA_1_I * MAX_PERIOD;
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constant PADJ_2_I : integer := DELTA_2_I * MAX_PERIOD;
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constant PADJ_2_I : integer := DELTA_2_I * MAX_PERIOD;
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constant PADJ_3_I : integer := DELTA_3_I * MAX_PERIOD;
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constant PADJ_3_I : integer := DELTA_3_I * MAX_PERIOD;
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constant PADJ_4_I : integer := DELTA_4_I * MAX_PERIOD;
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constant PADJ_4_I : integer := DELTA_4_I * MAX_PERIOD;
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constant PADJ_5_I : integer := DELTA_5_I * MAX_PERIOD;
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constant PADJ_5_I : integer := DELTA_5_I * MAX_PERIOD;
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constant PADJ_6_I : integer := DELTA_6_I * MAX_PERIOD;
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constant PADJ_6_I : integer := DELTA_6_I * MAX_PERIOD;
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constant PADJ_1 : std_logic_vector(DIV_WIDTH-1 downto 0) :=
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constant PADJ_1 : std_logic_vector(DIV_WIDTH-1 downto 0) :=
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conv_std_logic_vector(PADJ_1_I,DIV_WIDTH);
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conv_std_logic_vector(PADJ_1_I,DIV_WIDTH);
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constant PADJ_2 : std_logic_vector(DIV_WIDTH-1 downto 0) :=
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constant PADJ_2 : std_logic_vector(DIV_WIDTH-1 downto 0) :=
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conv_std_logic_vector(PADJ_2_I,DIV_WIDTH);
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conv_std_logic_vector(PADJ_2_I,DIV_WIDTH);
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constant PADJ_3 : std_logic_vector(DIV_WIDTH-1 downto 0) :=
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constant PADJ_3 : std_logic_vector(DIV_WIDTH-1 downto 0) :=
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conv_std_logic_vector(PADJ_3_I,DIV_WIDTH);
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conv_std_logic_vector(PADJ_3_I,DIV_WIDTH);
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constant PADJ_4 : std_logic_vector(DIV_WIDTH-1 downto 0) :=
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constant PADJ_4 : std_logic_vector(DIV_WIDTH-1 downto 0) :=
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conv_std_logic_vector(PADJ_4_I,DIV_WIDTH);
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conv_std_logic_vector(PADJ_4_I,DIV_WIDTH);
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constant PADJ_5 : std_logic_vector(DIV_WIDTH-1 downto 0) :=
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constant PADJ_5 : std_logic_vector(DIV_WIDTH-1 downto 0) :=
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conv_std_logic_vector(PADJ_5_I,DIV_WIDTH);
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conv_std_logic_vector(PADJ_5_I,DIV_WIDTH);
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constant PADJ_6 : std_logic_vector(DIV_WIDTH-1 downto 0) :=
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constant PADJ_6 : std_logic_vector(DIV_WIDTH-1 downto 0) :=
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conv_std_logic_vector(PADJ_6_I,DIV_WIDTH);
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conv_std_logic_vector(PADJ_6_I,DIV_WIDTH);
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constant CB : integer := ceil_log2(DIV_WIDTH);
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constant CB : integer := ceil_log2(DIV_WIDTH);
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signal LCD_Contrast : std_logic_vector(7 downto 0) := x"00";
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signal LCD_Contrast : std_logic_vector(7 downto 0) := x"00";
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signal CN_DACin_q : std_logic_vector(DAC_WIDTH-1 downto 0) := (others => '0');
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signal CN_DACin_q : std_logic_vector(DAC_WIDTH-1 downto 0) := (others => '0');
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signal CN_Divisor : std_logic_vector(DIV_WIDTH-1 downto 0) := (others => '0');
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signal CN_Divisor : std_logic_vector(DIV_WIDTH-1 downto 0) := (others => '0');
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signal CN_Dividend : std_logic_vector(DIV_WIDTH-1 downto 0) := (others => '0');
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signal CN_Dividend : std_logic_vector(DIV_WIDTH-1 downto 0) := (others => '0');
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signal CN_q : std_logic_vector(DIV_WIDTH*2-1 downto 0) := (others => '0');
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signal CN_q : std_logic_vector(DIV_WIDTH*2-1 downto 0) := (others => '0');
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signal CN_diff : std_logic_vector(DIV_WIDTH downto 0) := (others => '0');
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signal CN_diff : std_logic_vector(DIV_WIDTH downto 0) := (others => '0');
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signal CN_count : std_logic_vector(CB-1 downto 0) := (others => '0');
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signal CN_count : std_logic_vector(CB-1 downto 0) := (others => '0');
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signal CN_Next_Wdt : std_logic_vector(DAC_Width-1 downto 0) := (others => '0');
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signal CN_Next_Wdt : std_logic_vector(DAC_Width-1 downto 0) := (others => '0');
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signal CN_Next_Per : std_logic_vector(DAC_Width-1 downto 0) := (others => '0');
|
signal CN_Next_Per : std_logic_vector(DAC_Width-1 downto 0) := (others => '0');
|
|
|
signal CN_PWM_Wdt : std_logic_vector(DAC_Width-1 downto 0) := (others => '0');
|
signal CN_PWM_Wdt : std_logic_vector(DAC_Width-1 downto 0) := (others => '0');
|
signal CN_PWM_Per : std_logic_vector(DAC_Width-1 downto 0) := (others => '0');
|
signal CN_PWM_Per : std_logic_vector(DAC_Width-1 downto 0) := (others => '0');
|
|
|
signal CN_Wdt_Ctr : std_logic_vector(DAC_Width-1 downto 0) := (others => '0');
|
signal CN_Wdt_Ctr : std_logic_vector(DAC_Width-1 downto 0) := (others => '0');
|
signal CN_Per_Ctr : std_logic_vector(DAC_Width-1 downto 0) := (others => '0');
|
signal CN_Per_Ctr : std_logic_vector(DAC_Width-1 downto 0) := (others => '0');
|
|
|
signal LCD_Bright : std_logic_vector(7 downto 0) := (others => '0');
|
signal LCD_Bright : std_logic_vector(7 downto 0) := (others => '0');
|
|
|
signal BL_DACin_q : std_logic_vector(DAC_WIDTH-1 downto 0) := (others => '0');
|
signal BL_DACin_q : std_logic_vector(DAC_WIDTH-1 downto 0) := (others => '0');
|
|
|
signal BL_Divisor : std_logic_vector(DIV_WIDTH-1 downto 0) := (others => '0');
|
signal BL_Divisor : std_logic_vector(DIV_WIDTH-1 downto 0) := (others => '0');
|
signal BL_Dividend : std_logic_vector(DIV_WIDTH-1 downto 0) := (others => '0');
|
signal BL_Dividend : std_logic_vector(DIV_WIDTH-1 downto 0) := (others => '0');
|
|
|
signal BL_q : std_logic_vector(DIV_WIDTH*2-1 downto 0) := (others => '0');
|
signal BL_q : std_logic_vector(DIV_WIDTH*2-1 downto 0) := (others => '0');
|
signal BL_diff : std_logic_vector(DIV_WIDTH downto 0) := (others => '0');
|
signal BL_diff : std_logic_vector(DIV_WIDTH downto 0) := (others => '0');
|
|
|
signal BL_count : std_logic_vector(CB-1 downto 0) := (others => '0');
|
signal BL_count : std_logic_vector(CB-1 downto 0) := (others => '0');
|
|
|
signal BL_Next_Wdt : std_logic_vector(DAC_Width-1 downto 0) := (others => '0');
|
signal BL_Next_Wdt : std_logic_vector(DAC_Width-1 downto 0) := (others => '0');
|
signal BL_Next_Per : std_logic_vector(DAC_Width-1 downto 0) := (others => '0');
|
signal BL_Next_Per : std_logic_vector(DAC_Width-1 downto 0) := (others => '0');
|
|
|
signal BL_PWM_Wdt : std_logic_vector(DAC_Width-1 downto 0) := (others => '0');
|
signal BL_PWM_Wdt : std_logic_vector(DAC_Width-1 downto 0) := (others => '0');
|
signal BL_PWM_Per : std_logic_vector(DAC_Width-1 downto 0) := (others => '0');
|
signal BL_PWM_Per : std_logic_vector(DAC_Width-1 downto 0) := (others => '0');
|
|
|
signal BL_Wdt_Ctr : std_logic_vector(DAC_Width-1 downto 0) := (others => '0');
|
signal BL_Wdt_Ctr : std_logic_vector(DAC_Width-1 downto 0) := (others => '0');
|
signal BL_Per_Ctr : std_logic_vector(DAC_Width-1 downto 0) := (others => '0');
|
signal BL_Per_Ctr : std_logic_vector(DAC_Width-1 downto 0) := (others => '0');
|
|
|
begin
|
begin
|
|
|
--------------------------------------------------------------------------------
|
--------------------------------------------------------------------------------
|
-- Open8 Register interface
|
-- Open8 Register interface
|
--------------------------------------------------------------------------------
|
--------------------------------------------------------------------------------
|
|
|
Addr_Match <= '1' when Comp_Addr = User_Addr else '0';
|
Addr_Match <= '1' when Comp_Addr = User_Addr else '0';
|
|
|
io_reg: process( Clock, Reset )
|
io_reg: process( Clock, Reset )
|
begin
|
begin
|
if( Reset = Reset_Level )then
|
if( Reset = Reset_Level )then
|
Reg_Addr_q <= (others => '0');
|
Reg_Addr_q <= (others => '0');
|
Wr_Data_q <= (others => '0');
|
Wr_Data_q <= (others => '0');
|
Wr_En <= '0';
|
Wr_En <= '0';
|
Rd_En <= '0';
|
Rd_En <= '0';
|
Rd_Data <= OPEN8_NULLBUS;
|
Rd_Data <= OPEN8_NULLBUS;
|
|
|
Reg_Valid <= '0';
|
Reg_Valid <= '0';
|
Reg_Sel <= '0';
|
Reg_Sel <= '0';
|
Reg_Data <= x"00";
|
Reg_Data <= x"00";
|
|
|
LCD_Contrast <= Default_Contrast;
|
LCD_Contrast <= Default_Contrast;
|
LCD_Bright <= Default_Brightness;
|
LCD_Bright <= Default_Brightness;
|
elsif( rising_edge( Clock ) )then
|
elsif( rising_edge( Clock ) )then
|
Reg_Addr_q <= Reg_Addr;
|
Reg_Addr_q <= Reg_Addr;
|
|
|
Wr_Data_q <= Wr_Data;
|
Wr_Data_q <= Wr_Data;
|
Wr_En <= Addr_Match and Wr_Enable;
|
Wr_En <= Addr_Match and Wr_Enable;
|
|
|
Reg_Valid <= '0';
|
Reg_Valid <= '0';
|
|
|
if( Wr_En = '1' )then
|
if( Wr_En = '1' )then
|
case( Reg_Addr_q )is
|
case( Reg_Addr_q )is
|
when "00" | "01" =>
|
when "00" | "01" =>
|
Reg_Valid <= '1';
|
Reg_Valid <= '1';
|
Reg_Sel <= Reg_Addr_q(0);
|
Reg_Sel <= Reg_Addr_q(0);
|
Reg_Data <= Wr_Data_q;
|
Reg_Data <= Wr_Data_q;
|
when "10" =>
|
when "10" =>
|
LCD_Contrast<= Wr_Data_q;
|
LCD_Contrast<= Wr_Data_q;
|
when "11" =>
|
when "11" =>
|
LCD_Bright <= Wr_Data_q;
|
LCD_Bright <= Wr_Data_q;
|
when others => null;
|
when others => null;
|
end case;
|
end case;
|
end if;
|
end if;
|
|
|
Rd_Data <= OPEN8_NULLBUS;
|
Rd_Data <= OPEN8_NULLBUS;
|
Rd_En <= Addr_Match and Rd_Enable;
|
Rd_En <= Addr_Match and Rd_Enable;
|
if( Rd_En = '1' )then
|
if( Rd_En = '1' )then
|
case( Reg_Addr_q )is
|
case( Reg_Addr_q )is
|
when "00" | "01" =>
|
when "00" | "01" =>
|
Rd_Data(7) <= Tx_Ready;
|
Rd_Data(7) <= Tx_Ready;
|
when "10" =>
|
when "10" =>
|
Rd_Data <= LCD_Contrast;
|
Rd_Data <= LCD_Contrast;
|
when "11" =>
|
when "11" =>
|
Rd_Data <= LCD_Bright;
|
Rd_Data <= LCD_Bright;
|
when others => null;
|
when others => null;
|
end case;
|
end case;
|
end if;
|
end if;
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
--------------------------------------------------------------------------------
|
--------------------------------------------------------------------------------
|
-- LCD and Register logic
|
-- LCD and Register logic
|
--------------------------------------------------------------------------------
|
--------------------------------------------------------------------------------
|
|
|
LCD_RW <= '0'; -- Permanently wire the RW line low
|
LCD_RW <= '0'; -- Permanently wire the RW line low
|
|
|
LCD_IO: process( Clock, Reset )
|
LCD_IO: process( Clock, Reset )
|
begin
|
begin
|
if( Reset = Reset_Level )then
|
if( Reset = Reset_Level )then
|
io_state <= INIT;
|
io_state <= INIT;
|
init_count <= (others => '0');
|
init_count <= (others => '0');
|
io_timer <= (others => '0');
|
io_timer <= (others => '0');
|
busy_timer <= (others => '0');
|
busy_timer <= (others => '0');
|
LCD_Data <= (others => '0');
|
LCD_Data <= (others => '0');
|
LCD_Addr <= '0';
|
LCD_Addr <= '0';
|
LCD_E <= '0';
|
LCD_E <= '0';
|
LCD_RS <= '0';
|
LCD_RS <= '0';
|
LCD_D <= (others => '0');
|
LCD_D <= (others => '0');
|
Tx_Ready <= '0';
|
Tx_Ready <= '0';
|
Interrupt <= '0';
|
Interrupt <= '0';
|
elsif( rising_edge(Clock) )then
|
elsif( rising_edge(Clock) )then
|
LCD_E <= '0';
|
LCD_E <= '0';
|
LCD_RS <= '0';
|
LCD_RS <= '0';
|
LCD_D <= (others => '0');
|
LCD_D <= (others => '0');
|
Tx_Ready <= '0';
|
Tx_Ready <= '0';
|
Interrupt <= '0';
|
Interrupt <= '0';
|
io_timer <= io_timer - 1;
|
io_timer <= io_timer - 1;
|
busy_timer <= busy_timer - uSec_Tick;
|
busy_timer <= busy_timer - uSec_Tick;
|
case( io_state )is
|
case( io_state )is
|
|
|
when INIT =>
|
when INIT =>
|
busy_timer <= INIT_DELAY;
|
busy_timer <= INIT_DELAY;
|
init_count <= (others => '1');
|
init_count <= (others => '1');
|
io_state <= BUSY_WAIT;
|
io_state <= BUSY_WAIT;
|
|
|
when FN_JUMP =>
|
when FN_JUMP =>
|
io_state <= WR_PREP;
|
io_state <= WR_PREP;
|
case( init_count )is
|
case( init_count )is
|
when "000" =>
|
when "000" =>
|
io_state <= IDLE;
|
io_state <= IDLE;
|
when "001" =>
|
when "001" =>
|
LCD_Addr <= '0';
|
LCD_Addr <= '0';
|
LCD_Data <= LCD_CONFIG6; -- Reset the Cursor
|
LCD_Data <= LCD_CONFIG6; -- Reset the Cursor
|
when "010" =>
|
when "010" =>
|
LCD_Addr <= '1'; -- Print a "*", and
|
LCD_Addr <= '1'; -- Print a "*", and
|
LCD_Data <= LCD_CONFIG5; -- set RS to 1
|
LCD_Data <= LCD_CONFIG5; -- set RS to 1
|
when "011" =>
|
when "011" =>
|
LCD_Data <= LCD_CONFIG4; -- Entry mode
|
LCD_Data <= LCD_CONFIG4; -- Entry mode
|
when "100" =>
|
when "100" =>
|
LCD_Data <= LCD_CONFIG3; -- Clear Display
|
LCD_Data <= LCD_CONFIG3; -- Clear Display
|
when "101" =>
|
when "101" =>
|
LCD_Data <= LCD_CONFIG2; -- Display control
|
LCD_Data <= LCD_CONFIG2; -- Display control
|
when "110" | "111" =>
|
when "110" | "111" =>
|
LCD_Addr <= '0';
|
LCD_Addr <= '0';
|
LCD_Data <= LCD_CONFIG1; -- Function set
|
LCD_Data <= LCD_CONFIG1; -- Function set
|
when others => null;
|
when others => null;
|
end case;
|
end case;
|
|
|
when IDLE =>
|
when IDLE =>
|
Tx_Ready <= '1';
|
Tx_Ready <= '1';
|
if( Reg_Valid = '1' )then
|
if( Reg_Valid = '1' )then
|
LCD_Addr <= Reg_Sel;
|
LCD_Addr <= Reg_Sel;
|
LCD_Data <= Reg_Data;
|
LCD_Data <= Reg_Data;
|
io_state <= WR_PREP;
|
io_state <= WR_PREP;
|
end if;
|
end if;
|
|
|
when WR_PREP =>
|
when WR_PREP =>
|
io_timer <= SNH_DELAY;
|
io_timer <= SNH_DELAY;
|
io_state <= WR_SETUP;
|
io_state <= WR_SETUP;
|
|
|
when WR_SETUP =>
|
when WR_SETUP =>
|
LCD_RS <= LCD_Addr;
|
LCD_RS <= LCD_Addr;
|
LCD_D <= LCD_Data;
|
LCD_D <= LCD_Data;
|
LCD_E <= '1';
|
LCD_E <= '1';
|
if( io_timer = 0 )then
|
if( io_timer = 0 )then
|
io_timer <= SNH_DELAY;
|
io_timer <= SNH_DELAY;
|
io_state <= WR_HOLD;
|
io_state <= WR_HOLD;
|
end if;
|
end if;
|
|
|
when WR_HOLD =>
|
when WR_HOLD =>
|
LCD_RS <= LCD_Addr;
|
LCD_RS <= LCD_Addr;
|
LCD_D <= LCD_Data;
|
LCD_D <= LCD_Data;
|
if( io_timer = 0 )then
|
if( io_timer = 0 )then
|
LCD_E <= '0';
|
LCD_E <= '0';
|
io_state <= BUSY_PREP;
|
io_state <= BUSY_PREP;
|
end if;
|
end if;
|
|
|
when BUSY_PREP =>
|
when BUSY_PREP =>
|
busy_timer <= BUSY_DELAY;
|
busy_timer <= BUSY_DELAY;
|
if( LCD_Addr = '0' and LCD_Data < 4 )then
|
if( LCD_Addr = '0' and LCD_Data < 4 )then
|
busy_timer <= CLDSP_DELAY;
|
busy_timer <= CLDSP_DELAY;
|
end if;
|
end if;
|
io_state <= BUSY_WAIT;
|
io_state <= BUSY_WAIT;
|
|
|
when BUSY_WAIT =>
|
when BUSY_WAIT =>
|
if( busy_timer = 0 )then
|
if( busy_timer = 0 )then
|
io_state <= ISSUE_INT;
|
io_state <= ISSUE_INT;
|
if( init_count > 0 )then
|
if( init_count > 0 )then
|
init_count<= init_count - 1;
|
init_count<= init_count - 1;
|
io_state <= FN_JUMP;
|
io_state <= FN_JUMP;
|
end if;
|
end if;
|
end if;
|
end if;
|
|
|
when ISSUE_INT =>
|
when ISSUE_INT =>
|
Interrupt <= '1';
|
Interrupt <= '1';
|
io_state <= IDLE;
|
io_state <= IDLE;
|
|
|
when others => null;
|
when others => null;
|
|
|
end case;
|
end case;
|
|
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
--------------------------------------------------------------------------------
|
--------------------------------------------------------------------------------
|
-- Contrast control logic (optional)
|
-- Contrast control logic (optional)
|
--------------------------------------------------------------------------------
|
--------------------------------------------------------------------------------
|
|
|
Contrast_Disabled: if( not Use_Contrast )generate
|
Contrast_Disabled: if( not Use_Contrast )generate
|
LCD_CN <= '0';
|
LCD_CN <= '0';
|
end generate;
|
end generate;
|
|
|
Contrast_Enabled: if( Use_Contrast )generate
|
Contrast_Enabled: if( Use_Contrast )generate
|
|
|
CN_diff <= ('0' & CN_q(DIV_WIDTH*2-2 downto DIV_WIDTH-1)) -
|
CN_diff <= ('0' & CN_q(DIV_WIDTH*2-2 downto DIV_WIDTH-1)) -
|
('0' & CN_Divisor);
|
('0' & CN_Divisor);
|
|
|
CN_Dividend<= PADJ_2 when CN_DACin_q >= DELTA_2_I and CN_DACin_q < DELTA_3_I else
|
CN_Dividend<= PADJ_2 when CN_DACin_q >= DELTA_2_I and CN_DACin_q < DELTA_3_I else
|
PADJ_3 when CN_DACin_q >= DELTA_3_I and CN_DACin_q < DELTA_4_I else
|
PADJ_3 when CN_DACin_q >= DELTA_3_I and CN_DACin_q < DELTA_4_I else
|
PADJ_4 when CN_DACin_q >= DELTA_4_I and CN_DACin_q < DELTA_5_I else
|
PADJ_4 when CN_DACin_q >= DELTA_4_I and CN_DACin_q < DELTA_5_I else
|
PADJ_5 when CN_DACin_q >= DELTA_5_I and CN_DACin_q < DELTA_6_I else
|
PADJ_5 when CN_DACin_q >= DELTA_5_I and CN_DACin_q < DELTA_6_I else
|
PADJ_6 when CN_DACin_q >= DELTA_6_I else
|
PADJ_6 when CN_DACin_q >= DELTA_6_I else
|
PADJ_1;
|
PADJ_1;
|
|
|
CN_Next_Wdt<= DELTA_1 when CN_DACin_q >= DELTA_1_I and CN_DACin_q < DELTA_2_I else
|
CN_Next_Wdt<= DELTA_1 when CN_DACin_q >= DELTA_1_I and CN_DACin_q < DELTA_2_I else
|
DELTA_2 when CN_DACin_q >= DELTA_2_I and CN_DACin_q < DELTA_3_I else
|
DELTA_2 when CN_DACin_q >= DELTA_2_I and CN_DACin_q < DELTA_3_I else
|
DELTA_3 when CN_DACin_q >= DELTA_3_I and CN_DACin_q < DELTA_4_I else
|
DELTA_3 when CN_DACin_q >= DELTA_3_I and CN_DACin_q < DELTA_4_I else
|
DELTA_4 when CN_DACin_q >= DELTA_4_I and CN_DACin_q < DELTA_5_I else
|
DELTA_4 when CN_DACin_q >= DELTA_4_I and CN_DACin_q < DELTA_5_I else
|
DELTA_5 when CN_DACin_q >= DELTA_5_I and CN_DACin_q < DELTA_6_I else
|
DELTA_5 when CN_DACin_q >= DELTA_5_I and CN_DACin_q < DELTA_6_I else
|
DELTA_6 when CN_DACin_q >= DELTA_6_I else
|
DELTA_6 when CN_DACin_q >= DELTA_6_I else
|
(others => '0');
|
(others => '0');
|
|
|
CN_Next_Per <= BL_q(7 downto 0) - 1;
|
CN_Next_Per <= BL_q(7 downto 0) - 1;
|
|
|
CN_vDSM_proc: process( Clock, Reset )
|
CN_vDSM_proc: process( Clock, Reset )
|
begin
|
begin
|
if( Reset = Reset_Level )then
|
if( Reset = Reset_Level )then
|
CN_q <= (others => '0');
|
CN_q <= (others => '0');
|
CN_count <= (others => '1');
|
CN_count <= (others => '1');
|
CN_Divisor <= (others => '0');
|
CN_Divisor <= (others => '0');
|
CN_DACin_q <= (others => '0');
|
CN_DACin_q <= (others => '0');
|
CN_PWM_Wdt <= (others => '0');
|
CN_PWM_Wdt <= (others => '0');
|
CN_PWM_Per <= (others => '0');
|
CN_PWM_Per <= (others => '0');
|
CN_Per_Ctr <= (others => '0');
|
CN_Per_Ctr <= (others => '0');
|
CN_Wdt_Ctr <= (others => '0');
|
CN_Wdt_Ctr <= (others => '0');
|
LCD_CN <= '0';
|
LCD_CN <= '0';
|
elsif( rising_edge(Clock) )then
|
elsif( rising_edge(Clock) )then
|
CN_q <= CN_diff(DIV_WIDTH-1 downto 0) &
|
CN_q <= CN_diff(DIV_WIDTH-1 downto 0) &
|
CN_q(DIV_WIDTH-2 downto 0) & '1';
|
CN_q(DIV_WIDTH-2 downto 0) & '1';
|
if( CN_diff(DIV_WIDTH) = '1' )then
|
if( CN_diff(DIV_WIDTH) = '1' )then
|
CN_q <= CN_q(DIV_WIDTH*2-2 downto 0) & '0';
|
CN_q <= CN_q(DIV_WIDTH*2-2 downto 0) & '0';
|
end if;
|
end if;
|
|
|
CN_count <= CN_count + 1;
|
CN_count <= CN_count + 1;
|
if( CN_count = DIV_WIDTH )then
|
if( CN_count = DIV_WIDTH )then
|
CN_PWM_Wdt <= CN_Next_Wdt;
|
CN_PWM_Wdt <= CN_Next_Wdt;
|
CN_PWM_Per <= CN_Next_Per;
|
CN_PWM_Per <= CN_Next_Per;
|
CN_DACin_q <= LCD_Contrast;
|
CN_DACin_q <= LCD_Contrast;
|
CN_Divisor <= (others => '0');
|
CN_Divisor <= (others => '0');
|
CN_Divisor(DAC_Width-1 downto 0) <= CN_DACin_q;
|
CN_Divisor(DAC_Width-1 downto 0) <= CN_DACin_q;
|
CN_q <= conv_std_logic_vector(0,DIV_WIDTH) & CN_Dividend;
|
CN_q <= conv_std_logic_vector(0,DIV_WIDTH) & CN_Dividend;
|
CN_count <= (others => '0');
|
CN_count <= (others => '0');
|
end if;
|
end if;
|
|
|
CN_Per_Ctr <= CN_Per_Ctr - 1;
|
CN_Per_Ctr <= CN_Per_Ctr - 1;
|
CN_Wdt_Ctr <= CN_Wdt_Ctr - 1;
|
CN_Wdt_Ctr <= CN_Wdt_Ctr - 1;
|
|
|
LCD_CN <= '1';
|
LCD_CN <= '1';
|
if( CN_Wdt_Ctr = 0 )then
|
if( CN_Wdt_Ctr = 0 )then
|
LCD_CN <= '0';
|
LCD_CN <= '0';
|
CN_Wdt_Ctr <= (others => '0');
|
CN_Wdt_Ctr <= (others => '0');
|
end if;
|
end if;
|
|
|
if( CN_Per_Ctr = 0 )then
|
if( CN_Per_Ctr = 0 )then
|
CN_Per_Ctr <= CN_PWM_Per;
|
CN_Per_Ctr <= CN_PWM_Per;
|
CN_Wdt_Ctr <= CN_PWM_Wdt;
|
CN_Wdt_Ctr <= CN_PWM_Wdt;
|
end if;
|
end if;
|
|
|
end if;
|
end if;
|
end process;
|
end process;
|
end generate;
|
end generate;
|
|
|
--------------------------------------------------------------------------------
|
--------------------------------------------------------------------------------
|
-- Backlight control logic (optional)
|
-- Backlight control logic (optional)
|
--------------------------------------------------------------------------------
|
--------------------------------------------------------------------------------
|
|
|
Backlight_Disabled: if( not Use_Backlight )generate
|
Backlight_Disabled: if( not Use_Backlight )generate
|
LCD_BL <= '0';
|
LCD_BL <= '0';
|
end generate;
|
end generate;
|
|
|
Backlight_Enabled: if( Use_Backlight )generate
|
Backlight_Enabled: if( Use_Backlight )generate
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BL_diff <= ('0' & BL_q(DIV_WIDTH*2-2 downto DIV_WIDTH-1)) -
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BL_diff <= ('0' & BL_q(DIV_WIDTH*2-2 downto DIV_WIDTH-1)) -
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('0' & BL_Divisor);
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('0' & BL_Divisor);
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BL_Dividend<= PADJ_2 when BL_DACin_q >= DELTA_2_I and BL_DACin_q < DELTA_3_I else
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BL_Dividend<= PADJ_2 when BL_DACin_q >= DELTA_2_I and BL_DACin_q < DELTA_3_I else
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PADJ_3 when BL_DACin_q >= DELTA_3_I and BL_DACin_q < DELTA_4_I else
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PADJ_3 when BL_DACin_q >= DELTA_3_I and BL_DACin_q < DELTA_4_I else
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PADJ_4 when BL_DACin_q >= DELTA_4_I and BL_DACin_q < DELTA_5_I else
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PADJ_4 when BL_DACin_q >= DELTA_4_I and BL_DACin_q < DELTA_5_I else
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PADJ_5 when BL_DACin_q >= DELTA_5_I and BL_DACin_q < DELTA_6_I else
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PADJ_5 when BL_DACin_q >= DELTA_5_I and BL_DACin_q < DELTA_6_I else
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PADJ_6 when BL_DACin_q >= DELTA_6_I else
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PADJ_6 when BL_DACin_q >= DELTA_6_I else
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PADJ_1;
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PADJ_1;
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|
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BL_Next_Wdt<= DELTA_1 when BL_DACin_q >= DELTA_1_I and BL_DACin_q < DELTA_2_I else
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BL_Next_Wdt<= DELTA_1 when BL_DACin_q >= DELTA_1_I and BL_DACin_q < DELTA_2_I else
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DELTA_2 when BL_DACin_q >= DELTA_2_I and BL_DACin_q < DELTA_3_I else
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DELTA_2 when BL_DACin_q >= DELTA_2_I and BL_DACin_q < DELTA_3_I else
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DELTA_3 when BL_DACin_q >= DELTA_3_I and BL_DACin_q < DELTA_4_I else
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DELTA_3 when BL_DACin_q >= DELTA_3_I and BL_DACin_q < DELTA_4_I else
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DELTA_4 when BL_DACin_q >= DELTA_4_I and BL_DACin_q < DELTA_5_I else
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DELTA_4 when BL_DACin_q >= DELTA_4_I and BL_DACin_q < DELTA_5_I else
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DELTA_5 when BL_DACin_q >= DELTA_5_I and BL_DACin_q < DELTA_6_I else
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DELTA_5 when BL_DACin_q >= DELTA_5_I and BL_DACin_q < DELTA_6_I else
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DELTA_6 when BL_DACin_q >= DELTA_6_I else
|
DELTA_6 when BL_DACin_q >= DELTA_6_I else
|
(others => '0');
|
(others => '0');
|
|
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BL_Next_Per <= BL_q(7 downto 0) - 1;
|
BL_Next_Per <= BL_q(7 downto 0) - 1;
|
|
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BL_vDSM_proc: process( Clock, Reset )
|
BL_vDSM_proc: process( Clock, Reset )
|
begin
|
begin
|
if( Reset = Reset_Level )then
|
if( Reset = Reset_Level )then
|
BL_q <= (others => '0');
|
BL_q <= (others => '0');
|
BL_count <= (others => '1');
|
BL_count <= (others => '1');
|
BL_Divisor <= (others => '0');
|
BL_Divisor <= (others => '0');
|
BL_DACin_q <= (others => '0');
|
BL_DACin_q <= (others => '0');
|
BL_PWM_Wdt <= (others => '0');
|
BL_PWM_Wdt <= (others => '0');
|
BL_PWM_Per <= (others => '0');
|
BL_PWM_Per <= (others => '0');
|
BL_Per_Ctr <= (others => '0');
|
BL_Per_Ctr <= (others => '0');
|
BL_Wdt_Ctr <= (others => '0');
|
BL_Wdt_Ctr <= (others => '0');
|
LCD_BL <= '0';
|
LCD_BL <= '0';
|
elsif( rising_edge(Clock) )then
|
elsif( rising_edge(Clock) )then
|
BL_q <= BL_diff(DIV_WIDTH-1 downto 0) &
|
BL_q <= BL_diff(DIV_WIDTH-1 downto 0) &
|
BL_q(DIV_WIDTH-2 downto 0) & '1';
|
BL_q(DIV_WIDTH-2 downto 0) & '1';
|
if( BL_diff(DIV_WIDTH) = '1' )then
|
if( BL_diff(DIV_WIDTH) = '1' )then
|
BL_q <= BL_q(DIV_WIDTH*2-2 downto 0) & '0';
|
BL_q <= BL_q(DIV_WIDTH*2-2 downto 0) & '0';
|
end if;
|
end if;
|
|
|
BL_count <= BL_count + 1;
|
BL_count <= BL_count + 1;
|
if( BL_count = DIV_WIDTH )then
|
if( BL_count = DIV_WIDTH )then
|
BL_PWM_Wdt <= BL_Next_Wdt;
|
BL_PWM_Wdt <= BL_Next_Wdt;
|
BL_PWM_Per <= BL_Next_Per;
|
BL_PWM_Per <= BL_Next_Per;
|
BL_DACin_q <= LCD_Bright;
|
BL_DACin_q <= LCD_Bright;
|
BL_Divisor <= (others => '0');
|
BL_Divisor <= (others => '0');
|
BL_Divisor(DAC_Width-1 downto 0) <= BL_DACin_q;
|
BL_Divisor(DAC_Width-1 downto 0) <= BL_DACin_q;
|
BL_q <= conv_std_logic_vector(0,DIV_WIDTH) & BL_Dividend;
|
BL_q <= conv_std_logic_vector(0,DIV_WIDTH) & BL_Dividend;
|
BL_count <= (others => '0');
|
BL_count <= (others => '0');
|
end if;
|
end if;
|
|
|
BL_Per_Ctr <= BL_Per_Ctr - 1;
|
BL_Per_Ctr <= BL_Per_Ctr - 1;
|
BL_Wdt_Ctr <= BL_Wdt_Ctr - 1;
|
BL_Wdt_Ctr <= BL_Wdt_Ctr - 1;
|
|
|
LCD_BL <= '1';
|
LCD_BL <= '1';
|
if( BL_Wdt_Ctr = 0 )then
|
if( BL_Wdt_Ctr = 0 )then
|
LCD_BL <= '0';
|
LCD_BL <= '0';
|
BL_Wdt_Ctr <= (others => '0');
|
BL_Wdt_Ctr <= (others => '0');
|
end if;
|
end if;
|
|
|
if( BL_Per_Ctr = 0 )then
|
if( BL_Per_Ctr = 0 )then
|
BL_Per_Ctr <= BL_PWM_Per;
|
BL_Per_Ctr <= BL_PWM_Per;
|
BL_Wdt_Ctr <= BL_PWM_Wdt;
|
BL_Wdt_Ctr <= BL_PWM_Wdt;
|
end if;
|
end if;
|
|
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
end generate;
|
end generate;
|
|
|
end architecture;
|
end architecture;
|
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