-- Copyright (c)2013, 2020 Jeremy Seth Henry
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-- Copyright (c)2013, 2020 Jeremy Seth Henry
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-- All rights reserved.
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-- All rights reserved.
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--
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--
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-- Redistribution and use in source and binary forms, with or without
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-- Redistribution and use in source and binary forms, with or without
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-- modification, are permitted provided that the following conditions are met:
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-- modification, are permitted provided that the following conditions are met:
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-- * Redistributions of source code must retain the above copyright
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-- * Redistributions of source code must retain the above copyright
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-- notice, this list of conditions and the following disclaimer.
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-- notice, this list of conditions and the following disclaimer.
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-- * Redistributions in binary form must reproduce the above copyright
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-- * Redistributions in binary form must reproduce the above copyright
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-- notice, this list of conditions and the following disclaimer in the
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-- notice, this list of conditions and the following disclaimer in the
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-- documentation and/or other materials provided with the distribution,
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-- documentation and/or other materials provided with the distribution,
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-- where applicable (as part of a user interface, debugging port, etc.)
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-- where applicable (as part of a user interface, debugging port, etc.)
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--
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--
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-- THIS SOFTWARE IS PROVIDED BY JEREMY SETH HENRY ``AS IS'' AND ANY
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-- THIS SOFTWARE IS PROVIDED BY JEREMY SETH HENRY ``AS IS'' AND ANY
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-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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-- DISCLAIMED. IN NO EVENT SHALL JEREMY SETH HENRY BE LIABLE FOR ANY
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-- DISCLAIMED. IN NO EVENT SHALL JEREMY SETH HENRY BE LIABLE FOR ANY
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-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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-- THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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-- THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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--
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--
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-- VHDL Entity: o8_hd44780_if
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-- VHDL Entity: o8_hd44780_if
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-- Description: Provides low-level access to "standard" character LCDs using
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-- Description: Provides low-level access to "standard" character LCDs using
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-- the ST/HD44780(U) control ASIC wired in either 8-bit or
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-- the ST/HD44780(U) control ASIC wired in either 8-bit or
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-- reduced (4-bit) mode.
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-- reduced (4-bit) mode.
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-- All low-level timing of the control signals are handled by this
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-- All low-level timing of the control signals are handled by this
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-- module, allowing client firmware to use a simple register
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-- module, allowing client firmware to use a simple register
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-- interface to program the LCD panel.
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-- interface to program the LCD panel.
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--
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--
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-- Register Map
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-- Register Map
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-- Address Function
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-- Address Function
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-- Offset Bitfield Description Read/Write
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-- Offset Bitfield Description Read/Write
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-- 0x0 AAAAAAAA LCD Register Write (Read-Write*)
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-- 0x0 AAAAAAAA LCD Register Write (Read-Write*)
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-- 0x1 AAAAAAAA LCD Data Write (Read-Write*)
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-- 0x1 AAAAAAAA LCD Data Write (Read-Write*)
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-- 0x2 AAAAAAAA LCD Rearm Init Timer (Read-Write*)
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-- 0x2 AAAAAAAA LCD Rearm Init Timer (Read-Write*)
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-- 0x3 AAAAAAAA LCD Backlight (Read-Write)
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-- 0x3 AAAAAAAA LCD Backlight (Read-Write)
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--
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--
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-- Note: Reading 0x0, 0x1 or 0x2 will report whether the panel is ready or not
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-- Note: Reading 0x0, 0x1 or 0x2 will report whether the panel is ready or not
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-- in the MSB (bit 7). 0x00 = NOT READY / 0x80 = READY
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-- in the MSB (bit 7). 0x00 = NOT READY / 0x80 = READY
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--
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--
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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-- LCD Controller
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-- LCD Controller
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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--
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--
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-- LCD Instruction Set (Hitachi Compatible)
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-- LCD Instruction Set (Hitachi Compatible)
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-- Instruction RS RW D7 D6 D5 D4 D3 D2 D1 D0 Time
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-- Instruction RS RW D7 D6 D5 D4 D3 D2 D1 D0 Time
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------------------------------------------------------------------------
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------------------------------------------------------------------------
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-- Clear Display | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1.52mS
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-- Clear Display | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1.52mS
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-- Return Home | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | x | 1.52mS
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-- Return Home | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | x | 1.52mS
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-- Entry Mode | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | ID| S | 37uS
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-- Entry Mode | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | ID| S | 37uS
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-- Display Pwr | 0 | 0 | 0 | 0 | 0 | 0 | 1 | D | C | B | 37uS
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-- Display Pwr | 0 | 0 | 0 | 0 | 0 | 0 | 1 | D | C | B | 37uS
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-- Cursor/Display Shift | 0 | 0 | 0 | 0 | 0 | 1 | SC| RL| x | x | 37uS
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-- Cursor/Display Shift | 0 | 0 | 0 | 0 | 0 | 1 | SC| RL| x | x | 37uS
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-- Function Set | 0 | 0 | 0 | 0 | 1 | DL| N | F | x | x | 37uS
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-- Function Set | 0 | 0 | 0 | 0 | 1 | DL| N | F | x | x | 37uS
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-- Set CGRAM Address | 0 | 0 | 0 | 1 | A | A | A | A | A | A | 37uS
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-- Set CGRAM Address | 0 | 0 | 0 | 1 | A | A | A | A | A | A | 37uS
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-- Set DDRAM Address | 0 | 0 | 1 | A | A | A | A | A | A | A | 37uS
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-- Set DDRAM Address | 0 | 0 | 1 | A | A | A | A | A | A | A | 37uS
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-- LCD Instruction Set (New Haven)
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-- LCD Instruction Set (New Haven)
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-- Instruction RS RW D7 D6 D5 D4 D3 D2 D1 D0 Time
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-- Instruction RS RW D7 D6 D5 D4 D3 D2 D1 D0 Time
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------------------------------------------------------------------------
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------------------------------------------------------------------------
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-- Clear Display | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 2.00mS
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-- Clear Display | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 2.00mS
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-- Return Home | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | x | 600uS
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-- Return Home | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | x | 600uS
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-- Entry Mode | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | ID| S | 600uS
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-- Entry Mode | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | ID| S | 600uS
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-- Display Pwr | 0 | 0 | 0 | 0 | 0 | 0 | 1 | D | C | B | 600uS
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-- Display Pwr | 0 | 0 | 0 | 0 | 0 | 0 | 1 | D | C | B | 600uS
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-- Cursor/Display Shift | 0 | 0 | 0 | 0 | 0 | 1 | SC| RL| x | x | 600uS
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-- Cursor/Display Shift | 0 | 0 | 0 | 0 | 0 | 1 | SC| RL| x | x | 600uS
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-- Function Set | 0 | 0 | 0 | 0 | 1 | DL| N | F | T | T | 600uS
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-- Function Set | 0 | 0 | 0 | 0 | 1 | DL| N | F | T | T | 600uS
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-- Set CGRAM Address | 0 | 0 | 0 | 1 | A | A | A | A | A | A | 600uS
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-- Set CGRAM Address | 0 | 0 | 0 | 1 | A | A | A | A | A | A | 600uS
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-- Set DDRAM Address | 0 | 0 | 1 | A | A | A | A | A | A | A | 600uS
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-- Set DDRAM Address | 0 | 0 | 1 | A | A | A | A | A | A | A | 600uS
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--
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--
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-- Notes:
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-- Notes:
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-- ID = Increment/Decrement DDRAM Address (1 = increment, 0 = decrement)
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-- ID = Increment/Decrement DDRAM Address (1 = increment, 0 = decrement)
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-- S = Shift Enable (1 = Shift display according to ID, 0 = Don't shift)
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-- S = Shift Enable (1 = Shift display according to ID, 0 = Don't shift)
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-- D = Display On/Off (1 = on, 0 = off)
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-- D = Display On/Off (1 = on, 0 = off)
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-- C = Cursor On/Off (1 = on, 0 = off)
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-- C = Cursor On/Off (1 = on, 0 = off)
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-- B = Cursor Blink (1 = block cursor, 0 = underline cursor)
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-- B = Cursor Blink (1 = block cursor, 0 = underline cursor)
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-- SC / RL = Shift Cursor/Display Right/Left (see data sheet - not needed for init)
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-- SC / RL = Shift Cursor/Display Right/Left (see data sheet - not needed for init)
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-- F = Font (0 = 5x8, 1 = 5x11) Ignored on 2-line displays (N = 1)
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-- F = Font (0 = 5x8, 1 = 5x11) Ignored on 2-line displays (N = 1)
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-- N = Number of Lines (0 = 1 lines, 1 = 2 lines)
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-- N = Number of Lines (0 = 1 lines, 1 = 2 lines)
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-- DL = Data Length (0 = 4-bit bus, 1 = 8-bit bus) This is fixed at 1 in this module
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-- DL = Data Length (0 = 4-bit bus, 1 = 8-bit bus) This is fixed at 1 in this module
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-- A = Address (see data sheet for usage)
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-- A = Address (see data sheet for usage)
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-- T = New Haven Only - Changes the character set (see data sheet)
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-- T = New Haven Only - Changes the character set (see data sheet)
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--
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--
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-- Revision History
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-- Revision History
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-- Author Date Change
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-- Author Date Change
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------------------ -------- ---------------------------------------------------
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------------------ -------- ---------------------------------------------------
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-- Seth Henry 04/12/13 Design Start
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-- Seth Henry 04/12/21 Design Start
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_arith.all;
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library work;
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library work;
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use work.open8_pkg.all;
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use work.open8_pkg.all;
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entity o8_hd44780_if is
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entity o8_hd44780_if is
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generic(
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generic(
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Use_4Bit_IF : boolean := TRUE;
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Use_4Bit_IF : boolean := TRUE;
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-- Bus IF timing
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-- Bus IF timing
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Tsu : integer := 40; -- ns
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Tsu : integer := 40; -- ns
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Tpw : integer := 250; -- nS
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Tpw : integer := 250; -- nS
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Tcyc : integer := 500; -- nS
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Tcyc : integer := 500; -- nS
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-- Panel command timing
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-- Panel command timing
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Tpwrdly : integer := 40000; -- uS
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Tpwrdly : integer := 40000; -- uS
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Tcldsp : integer := 2000; -- uS
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Tcldsp : integer := 2000; -- uS
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Tbusy : integer := 50; -- uS
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Tbusy : integer := 50; -- uS
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-- Contrast/Backlight
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-- Contrast/Backlight
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Use_Backlight : boolean := FALSE;
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Use_Backlight : boolean := FALSE;
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Default_Brightness : std_logic_vector(7 downto 0) := x"00";
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Default_Brightness : std_logic_vector(7 downto 0) := x"00";
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Clock_Frequency : real;
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Clock_Frequency : real;
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Address : ADDRESS_TYPE
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Address : ADDRESS_TYPE
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);
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);
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port(
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port(
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Open8_Bus : in OPEN8_BUS_TYPE;
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Open8_Bus : in OPEN8_BUS_TYPE;
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Write_Qual : in std_logic := '1';
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Write_Qual : in std_logic := '1';
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Rd_Data : out DATA_TYPE;
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Rd_Data : out DATA_TYPE;
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Interrupt : out std_logic;
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Interrupt : out std_logic;
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--
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--
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LCD_E : out std_logic;
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LCD_E : out std_logic;
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LCD_RW : out std_logic;
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LCD_RW : out std_logic;
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LCD_RS : out std_logic;
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LCD_RS : out std_logic;
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LCD_DQ : out std_logic_vector(7 downto 0);
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LCD_DQ : out std_logic_vector(7 downto 0);
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LCD_BL : out std_logic
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LCD_BL : out std_logic
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);
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);
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end entity;
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end entity;
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architecture behave of o8_hd44780_if is
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architecture behave of o8_hd44780_if is
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alias Clock is Open8_Bus.Clock;
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alias Clock is Open8_Bus.Clock;
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alias Reset is Open8_Bus.Reset;
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alias Reset is Open8_Bus.Reset;
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alias uSec_Tick is Open8_Bus.uSec_Tick;
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alias uSec_Tick is Open8_Bus.uSec_Tick;
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constant User_Addr : std_logic_vector(15 downto 2)
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constant User_Addr : std_logic_vector(15 downto 2)
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:= Address(15 downto 2);
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:= Address(15 downto 2);
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alias Comp_Addr is Open8_Bus.Address(15 downto 2);
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alias Comp_Addr is Open8_Bus.Address(15 downto 2);
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signal Addr_Match : std_logic;
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signal Addr_Match : std_logic;
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alias Reg_Sel_d is Open8_Bus.Address(1 downto 0);
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alias Reg_Sel_d is Open8_Bus.Address(1 downto 0);
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signal Reg_Sel_q : std_logic_vector(1 downto 0) := "00";
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signal Reg_Sel_q : std_logic_vector(1 downto 0) := "00";
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signal Wr_En_d : std_logic := '0';
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signal Wr_En_d : std_logic := '0';
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signal Wr_En_q : std_logic := '0';
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signal Wr_En_q : std_logic := '0';
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alias Wr_Data_d is Open8_Bus.Wr_Data;
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alias Wr_Data_d is Open8_Bus.Wr_Data;
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signal Wr_Data_q : DATA_TYPE := x"00";
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signal Wr_Data_q : DATA_TYPE := x"00";
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signal Rd_En_d : std_logic := '0';
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signal Rd_En_d : std_logic := '0';
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signal Rd_En_q : std_logic := '0';
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signal Rd_En_q : std_logic := '0';
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signal Rearm_Init : std_logic := '0';
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signal Rearm_Init : std_logic := '0';
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signal Reg_Valid : std_logic := '0';
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signal Reg_Valid : std_logic := '0';
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signal Reg_Sel : std_logic := '0';
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signal Reg_Sel : std_logic := '0';
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signal Reg_Data : std_logic_vector(7 downto 0) := x"00";
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signal Reg_Data : std_logic_vector(7 downto 0) := x"00";
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signal Tx_Ready : std_logic := '0';
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signal Tx_Ready : std_logic := '0';
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constant HW_TMR_BITS : integer := ceil_log2(Tpwrdly);
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constant HW_TMR_BITS : integer := ceil_log2(Tpwrdly);
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constant TPWR_DELAY : std_logic_vector(HW_TMR_BITS-1 downto 0) :=
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constant TPWR_DELAY : std_logic_vector(HW_TMR_BITS-1 downto 0) :=
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conv_std_logic_vector(Tpwrdly,HW_TMR_BITS);
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conv_std_logic_vector(Tpwrdly,HW_TMR_BITS);
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constant CLDSP_DELAY : std_logic_vector(HW_TMR_BITS-1 downto 0) :=
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constant CLDSP_DELAY : std_logic_vector(HW_TMR_BITS-1 downto 0) :=
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conv_std_logic_vector(Tcldsp,HW_TMR_BITS);
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conv_std_logic_vector(Tcldsp,HW_TMR_BITS);
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constant BUSY_DELAY : std_logic_vector(HW_TMR_BITS-1 downto 0) :=
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constant BUSY_DELAY : std_logic_vector(HW_TMR_BITS-1 downto 0) :=
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conv_std_logic_vector(Tbusy, HW_TMR_BITS);
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conv_std_logic_vector(Tbusy, HW_TMR_BITS);
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signal hw_timer : std_logic_vector(HW_TMR_BITS-1 downto 0);
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signal hw_timer : std_logic_vector(HW_TMR_BITS-1 downto 0);
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type CTRL_STATES is (INIT, PWR_WAIT, IDLE, PREP_WR, ISSUE_WR, WR_WAIT,
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type CTRL_STATES is (INIT, PWR_WAIT, IDLE, PREP_WR, ISSUE_WR, WR_WAIT,
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BUSY_WAIT, ISSUE_INT );
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BUSY_WAIT, ISSUE_INT );
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signal ctrl_state : CTRL_STATES := INIT;
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signal ctrl_state : CTRL_STATES := INIT;
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signal Wr_Fnset : std_logic := '0';
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signal Wr_Fnset : std_logic := '0';
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signal Wr_Data : DATA_TYPE := x"00";
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signal Wr_Data : DATA_TYPE := x"00";
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signal Wr_Reg : std_logic := '0';
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signal Wr_Reg : std_logic := '0';
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signal Wr_En : std_logic := '0';
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signal Wr_En : std_logic := '0';
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signal IO_Done : std_logic := '0';
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signal IO_Done : std_logic := '0';
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signal LCD_Data : DATA_TYPE := x"00";
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signal LCD_Data : DATA_TYPE := x"00";
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signal LCD_Addr : std_logic := '0';
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signal LCD_Addr : std_logic := '0';
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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-- Backlight signals
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-- Backlight signals
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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signal LCD_Bright : DATA_TYPE := x"00";
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signal LCD_Bright : DATA_TYPE := x"00";
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begin
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begin
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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-- Open8 Register interface
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-- Open8 Register interface
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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Addr_Match <= '1' when Comp_Addr = User_Addr else '0';
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Addr_Match <= '1' when Comp_Addr = User_Addr else '0';
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Wr_En_d <= Addr_Match and Open8_Bus.Wr_En and Write_Qual;
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Wr_En_d <= Addr_Match and Open8_Bus.Wr_En and Write_Qual;
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Rd_En_d <= Addr_Match and Open8_Bus.Rd_En;
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Rd_En_d <= Addr_Match and Open8_Bus.Rd_En;
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io_reg: process( Clock, Reset )
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io_reg: process( Clock, Reset )
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begin
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begin
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if( Reset = Reset_Level )then
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if( Reset = Reset_Level )then
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Reg_Sel_q <= "00";
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Reg_Sel_q <= "00";
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Wr_En_q <= '0';
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Wr_En_q <= '0';
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Wr_Data_q <= x"00";
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Wr_Data_q <= x"00";
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Rd_En_q <= '0';
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Rd_En_q <= '0';
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Rd_Data <= OPEN8_NULLBUS;
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Rd_Data <= OPEN8_NULLBUS;
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Rearm_Init <= '0';
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Rearm_Init <= '0';
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Reg_Valid <= '0';
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Reg_Valid <= '0';
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Reg_Sel <= '0';
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Reg_Sel <= '0';
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Reg_Data <= x"00";
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Reg_Data <= x"00";
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LCD_Bright <= Default_Brightness;
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LCD_Bright <= Default_Brightness;
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elsif( rising_edge( Clock ) )then
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elsif( rising_edge( Clock ) )then
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Reg_Sel_q <= Reg_Sel_d;
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Reg_Sel_q <= Reg_Sel_d;
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Rearm_Init <= '0';
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Rearm_Init <= '0';
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Wr_En_q <= Wr_En_d;
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Wr_En_q <= Wr_En_d;
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Wr_Data_q <= Wr_Data_d;
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Wr_Data_q <= Wr_Data_d;
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Reg_Valid <= '0';
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Reg_Valid <= '0';
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if( Wr_En_q = '1' )then
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if( Wr_En_q = '1' )then
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case( Reg_Sel_q )is
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case( Reg_Sel_q )is
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when "00" | "01" =>
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when "00" | "01" =>
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Reg_Valid <= '1';
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Reg_Valid <= '1';
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Reg_Sel <= Reg_Sel_q(0);
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Reg_Sel <= Reg_Sel_q(0);
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Reg_Data <= Wr_Data_q;
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Reg_Data <= Wr_Data_q;
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when "10" =>
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when "10" =>
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Rearm_Init <= '1';
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Rearm_Init <= '1';
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when "11" =>
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when "11" =>
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LCD_Bright <= Wr_Data_q;
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LCD_Bright <= Wr_Data_q;
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when others => null;
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when others => null;
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end case;
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end case;
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end if;
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end if;
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Rd_En_q <= Rd_En_d;
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Rd_En_q <= Rd_En_d;
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Rd_Data <= OPEN8_NULLBUS;
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Rd_Data <= OPEN8_NULLBUS;
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if( Rd_En_q = '1' )then
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if( Rd_En_q = '1' )then
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case( Reg_Sel_q )is
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case( Reg_Sel_q )is
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when "00" | "01" | "10" =>
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when "00" | "01" | "10" =>
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Rd_Data(7) <= Tx_Ready;
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Rd_Data(7) <= Tx_Ready;
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when "11" =>
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when "11" =>
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Rd_Data <= LCD_Bright;
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Rd_Data <= LCD_Bright;
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when others => null;
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when others => null;
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end case;
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end case;
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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-- LCD and Register logic
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-- LCD and Register logic
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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LCD_RW <= '0'; -- Permanently wire the RW line low
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LCD_RW <= '0'; -- Permanently wire the RW line low
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LCD_Ctrl_proc: process( Clock, Reset )
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LCD_Ctrl_proc: process( Clock, Reset )
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begin
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begin
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if( Reset = Reset_Level )then
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if( Reset = Reset_Level )then
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ctrl_state <= INIT;
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ctrl_state <= INIT;
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hw_timer <= (others => '0');
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hw_timer <= (others => '0');
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Wr_Fnset <= '0';
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Wr_Fnset <= '0';
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Wr_Data <= x"00";
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Wr_Data <= x"00";
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Wr_Reg <= '0';
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Wr_Reg <= '0';
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Wr_En <= '0';
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Wr_En <= '0';
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Tx_Ready <= '0';
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Tx_Ready <= '0';
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Interrupt <= '0';
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Interrupt <= '0';
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elsif( rising_edge(Clock) )then
|
elsif( rising_edge(Clock) )then
|
Wr_En <= '0';
|
Wr_En <= '0';
|
Tx_Ready <= '0';
|
Tx_Ready <= '0';
|
Interrupt <= '0';
|
Interrupt <= '0';
|
hw_timer <= hw_timer - uSec_Tick;
|
hw_timer <= hw_timer - uSec_Tick;
|
case( ctrl_state )is
|
case( ctrl_state )is
|
|
|
when INIT =>
|
when INIT =>
|
hw_timer <= TPWR_DELAY;
|
hw_timer <= TPWR_DELAY;
|
ctrl_state <= PWR_WAIT;
|
ctrl_state <= PWR_WAIT;
|
|
|
when PWR_WAIT =>
|
when PWR_WAIT =>
|
if( hw_timer = 0 )then
|
if( hw_timer = 0 )then
|
ctrl_state <= IDLE;
|
ctrl_state <= IDLE;
|
end if;
|
end if;
|
|
|
when IDLE =>
|
when IDLE =>
|
Tx_Ready <= '1';
|
Tx_Ready <= '1';
|
if( Rearm_Init = '1' )then
|
if( Rearm_Init = '1' )then
|
ctrl_state <= INIT;
|
ctrl_state <= INIT;
|
elsif( Reg_Valid = '1' )then
|
elsif( Reg_Valid = '1' )then
|
Wr_Reg <= Reg_Sel;
|
Wr_Reg <= Reg_Sel;
|
Wr_Data <= Reg_Data;
|
Wr_Data <= Reg_Data;
|
ctrl_state <= PREP_WR;
|
ctrl_state <= PREP_WR;
|
end if;
|
end if;
|
|
|
when PREP_WR =>
|
when PREP_WR =>
|
Wr_Fnset <= '0';
|
Wr_Fnset <= '0';
|
-- Trap on Function Set if we are in 4-bit mode, so that we can issue
|
-- Trap on Function Set if we are in 4-bit mode, so that we can issue
|
-- the first nibble twice.
|
-- the first nibble twice.
|
if( Use_4Bit_IF and
|
if( Use_4Bit_IF and
|
Wr_Reg = '0' and
|
Wr_Reg = '0' and
|
Wr_Data(7 downto 4) = "0010" )then
|
Wr_Data(7 downto 4) = "0010" )then
|
Wr_Fnset <= '1';
|
Wr_Fnset <= '1';
|
end if;
|
end if;
|
ctrl_state <= ISSUE_WR;
|
ctrl_state <= ISSUE_WR;
|
|
|
when ISSUE_WR =>
|
when ISSUE_WR =>
|
Wr_En <= '1';
|
Wr_En <= '1';
|
hw_timer <= BUSY_DELAY;
|
hw_timer <= BUSY_DELAY;
|
if( Wr_Reg = '0' and Wr_Data = x"01" )then
|
if( Wr_Reg = '0' and Wr_Data = x"01" )then
|
hw_timer <= CLDSP_DELAY;
|
hw_timer <= CLDSP_DELAY;
|
end if;
|
end if;
|
ctrl_state <= WR_WAIT;
|
ctrl_state <= WR_WAIT;
|
|
|
when WR_WAIT =>
|
when WR_WAIT =>
|
if( IO_Done = '1' )then
|
if( IO_Done = '1' )then
|
ctrl_state <= BUSY_WAIT;
|
ctrl_state <= BUSY_WAIT;
|
end if;
|
end if;
|
|
|
when BUSY_WAIT =>
|
when BUSY_WAIT =>
|
if( hw_timer = 0 )then
|
if( hw_timer = 0 )then
|
ctrl_state <= ISSUE_INT;
|
ctrl_state <= ISSUE_INT;
|
end if;
|
end if;
|
|
|
when ISSUE_INT =>
|
when ISSUE_INT =>
|
Interrupt <= '1';
|
Interrupt <= '1';
|
ctrl_state <= IDLE;
|
ctrl_state <= IDLE;
|
|
|
when others => null;
|
when others => null;
|
|
|
end case;
|
end case;
|
|
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
--------------------------------------------------------------------------------
|
--------------------------------------------------------------------------------
|
-- Low-level I/O drivers
|
-- Low-level I/O drivers
|
--------------------------------------------------------------------------------
|
--------------------------------------------------------------------------------
|
|
|
IF_Type_4bit: if( Use_4Bit_IF )generate
|
IF_Type_4bit: if( Use_4Bit_IF )generate
|
|
|
U_IO : entity work.hd44780_4b
|
U_IO : entity work.hd44780_4b
|
generic map(
|
generic map(
|
Tsu => Tsu,
|
Tsu => Tsu,
|
Tpw => Tpw,
|
Tpw => Tpw,
|
Tcyc => Tcyc,
|
Tcyc => Tcyc,
|
Clock_Frequency => Clock_Frequency,
|
Clock_Frequency => Clock_Frequency,
|
Reset_Level => Reset_Level
|
Reset_Level => Reset_Level
|
)
|
)
|
port map(
|
port map(
|
Clock => Clock,
|
Clock => Clock,
|
Reset => Reset,
|
Reset => Reset,
|
--
|
--
|
Wr_Fnset => Wr_Fnset,
|
Wr_Fnset => Wr_Fnset,
|
Wr_Data => Wr_Data,
|
Wr_Data => Wr_Data,
|
Wr_Reg => Wr_Reg,
|
Wr_Reg => Wr_Reg,
|
Wr_En => Wr_En,
|
Wr_En => Wr_En,
|
--
|
--
|
IO_Done => IO_Done,
|
IO_Done => IO_Done,
|
--
|
--
|
LCD_RS => LCD_RS,
|
LCD_RS => LCD_RS,
|
LCD_E => LCD_E,
|
LCD_E => LCD_E,
|
LCD_DQ => LCD_DQ
|
LCD_DQ => LCD_DQ
|
);
|
);
|
|
|
end generate;
|
end generate;
|
|
|
IF_Type_8bit: if( not Use_4Bit_IF )generate
|
IF_Type_8bit: if( not Use_4Bit_IF )generate
|
|
|
U_IO : entity work.hd44780_8b
|
U_IO : entity work.hd44780_8b
|
generic map(
|
generic map(
|
Tsu => Tsu,
|
Tsu => Tsu,
|
Tpw => Tpw,
|
Tpw => Tpw,
|
Tcyc => Tcyc,
|
Tcyc => Tcyc,
|
Clock_Frequency => Clock_Frequency,
|
Clock_Frequency => Clock_Frequency,
|
Reset_Level => Reset_Level
|
Reset_Level => Reset_Level
|
)
|
)
|
port map(
|
port map(
|
Clock => Clock,
|
Clock => Clock,
|
Reset => Reset,
|
Reset => Reset,
|
--
|
--
|
Wr_Data => Wr_Data,
|
Wr_Data => Wr_Data,
|
Wr_Reg => Wr_Reg,
|
Wr_Reg => Wr_Reg,
|
Wr_En => Wr_En,
|
Wr_En => Wr_En,
|
--
|
--
|
IO_Done => IO_Done,
|
IO_Done => IO_Done,
|
--
|
--
|
LCD_RS => LCD_RS,
|
LCD_RS => LCD_RS,
|
LCD_E => LCD_E,
|
LCD_E => LCD_E,
|
LCD_DQ => LCD_DQ
|
LCD_DQ => LCD_DQ
|
);
|
);
|
|
|
end generate;
|
end generate;
|
|
|
--------------------------------------------------------------------------------
|
--------------------------------------------------------------------------------
|
-- Backlight control logic (optional)
|
-- Backlight control logic (optional)
|
--------------------------------------------------------------------------------
|
--------------------------------------------------------------------------------
|
|
|
Backlight_Disabled: if( not Use_Backlight )generate
|
Backlight_Disabled: if( not Use_Backlight )generate
|
LCD_BL <= '0';
|
LCD_BL <= '0';
|
end generate;
|
end generate;
|
|
|
Backlight_Enabled: if( Use_Backlight )generate
|
Backlight_Enabled: if( Use_Backlight )generate
|
|
|
U_BL : entity work.vdsm8
|
U_BL : entity work.vdsm8
|
generic map(
|
generic map(
|
Reset_Level => Reset_Level
|
Reset_Level => Reset_Level
|
)
|
)
|
port map(
|
port map(
|
Clock => Clock,
|
Clock => Clock,
|
Reset => Reset,
|
Reset => Reset,
|
DACin => LCD_Bright,
|
DACin => LCD_Bright,
|
DACout => LCD_BL
|
DACout => LCD_BL
|
);
|
);
|
|
|
end generate;
|
end generate;
|
|
|
end architecture;
|
end architecture;
|
|
|