-- Copyright (c)2018, 2020 Jeremy Seth Henry
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-- Copyright (c)2018, 2020 Jeremy Seth Henry
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-- All rights reserved.
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-- All rights reserved.
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--
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--
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-- Redistribution and use in source and binary forms, with or without
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-- Redistribution and use in source and binary forms, with or without
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-- modification, are permitted provided that the following conditions are met:
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-- modification, are permitted provided that the following conditions are met:
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-- * Redistributions of source code must retain the above copyright
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-- * Redistributions of source code must retain the above copyright
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-- notice, this list of conditions and the following disclaimer.
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-- notice, this list of conditions and the following disclaimer.
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-- * Redistributions in binary form must reproduce the above copyright
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-- * Redistributions in binary form must reproduce the above copyright
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-- notice, this list of conditions and the following disclaimer in the
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-- notice, this list of conditions and the following disclaimer in the
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-- documentation and/or other materials provided with the distribution,
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-- documentation and/or other materials provided with the distribution,
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-- where applicable (as part of a user interface, debugging port, etc.)
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-- where applicable (as part of a user interface, debugging port, etc.)
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--
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--
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-- THIS SOFTWARE IS PROVIDED BY JEREMY SETH HENRY ``AS IS'' AND ANY
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-- THIS SOFTWARE IS PROVIDED BY JEREMY SETH HENRY ``AS IS'' AND ANY
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-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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-- DISCLAIMED. IN NO EVENT SHALL JEREMY SETH HENRY BE LIABLE FOR ANY
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-- DISCLAIMED. IN NO EVENT SHALL JEREMY SETH HENRY BE LIABLE FOR ANY
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-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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-- THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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-- THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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--
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--
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-- VHDL Units : o8_register
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-- VHDL Units : o8_register
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-- Description: Provides a byte of pseudo-random data on every read
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-- Description: Provides a byte of pseudo-random data on every read
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--
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--
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-- Register Map:
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-- Register Map:
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-- Offset Bitfield Description Read/Write
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-- Offset Bitfield Description Read/Write
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-- 0x00 AAAAAAAA Data output (RW)
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-- 0x00 AAAAAAAA Data output (RW)
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--
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--
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-- Revision History
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-- Revision History
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-- Author Date Change
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-- Author Date Change
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------------------ -------- ---------------------------------------------------
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------------------ -------- ---------------------------------------------------
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-- Seth Henry 04/25/18 Design Start
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-- Seth Henry 04/25/18 Design Start
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-- Seth Henry 04/10/20 Code cleanup and comments
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-- Seth Henry 04/10/20 Code cleanup and comments
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-- Seth Henry 04/16/20 Modified to use Open8 bus record
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-- Seth Henry 04/16/20 Modified to use Open8 bus record
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_misc.all;
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use ieee.std_logic_misc.all;
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library work;
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library work;
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use work.open8_pkg.all;
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use work.open8_pkg.all;
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entity o8_lfsr32 is
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entity o8_lfsr32 is
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generic(
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generic(
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Init_Seed : std_logic_vector(31 downto 0) := x"CAFEBABE";
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Init_Seed : std_logic_vector(31 downto 0) := x"CAFEBABE";
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Address : ADDRESS_TYPE
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Address : ADDRESS_TYPE
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);
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);
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port(
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port(
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Open8_Bus : in OPEN8_BUS_TYPE;
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Open8_Bus : in OPEN8_BUS_TYPE;
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Rd_Data : out DATA_TYPE
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Rd_Data : out DATA_TYPE
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);
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);
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end entity;
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end entity;
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architecture behave of o8_lfsr32 is
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architecture behave of o8_lfsr32 is
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alias Clock is Open8_Bus.Clock;
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alias Clock is Open8_Bus.Clock;
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alias Reset is Open8_Bus.Reset;
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alias Reset is Open8_Bus.Reset;
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constant User_Addr : std_logic_vector(15 downto 1)
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constant User_Addr : std_logic_vector(15 downto 1)
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:= Address(15 downto 1);
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:= Address(15 downto 1);
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alias Comp_Addr is Open8_Bus.Address(15 downto 1);
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alias Comp_Addr is Open8_Bus.Address(15 downto 1);
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alias Reg_Sel is Open8_Bus.Address(0);
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signal Reg_Sel_q : std_logic := '0';
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signal Addr_Match : std_logic := '0';
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signal Addr_Match : std_logic := '0';
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signal Rd_En : std_logic := '0';
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alias Reg_Sel_d is Open8_Bus.Address(0);
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signal Reg_Sel_q : std_logic := '0';
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signal Rd_En_d : std_logic := '0';
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signal Rd_En_q : std_logic := '0';
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signal d0 : std_logic := '0';
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signal d0 : std_logic := '0';
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signal lfsr : std_logic_vector(31 downto 0) := x"00000000";
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signal lfsr : std_logic_vector(31 downto 0) := x"00000000";
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signal lfsr_q : std_logic_vector(31 downto 0) := x"00000000";
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signal lfsr_q : std_logic_vector(31 downto 0) := x"00000000";
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begin
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begin
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Addr_Match <= Open8_Bus.Rd_En when Comp_Addr = User_Addr else
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Addr_Match <= '1' when Comp_Addr = User_Addr else '0';
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'0';
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Rd_En_d <= Addr_Match and Open8_Bus.Rd_En;
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d0 <= lfsr(31) xnor lfsr(21) xnor lfsr(1) xnor lfsr(0);
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d0 <= lfsr(31) xnor lfsr(21) xnor lfsr(1) xnor lfsr(0);
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lfsr_proc: process( Clock, Reset )
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lfsr_proc: process( Clock, Reset )
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begin
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begin
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if( Reset = Reset_Level )then
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if( Reset = Reset_Level )then
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Reg_Sel_q <= '0';
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Reg_Sel_q <= '0';
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Rd_En <= '0';
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Rd_En_q <= '0';
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Rd_Data <= x"00";
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Rd_Data <= x"00";
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lfsr <= Init_Seed;
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lfsr <= Init_Seed;
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lfsr_q <= x"00000000";
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lfsr_q <= x"00000000";
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elsif( rising_edge(Clock) )then
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elsif( rising_edge(Clock) )then
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Rd_Data <= x"00";
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Reg_Sel_q <= Reg_Sel_d;
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Reg_Sel_q <= Reg_Sel;
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Rd_En <= Addr_Match;
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Rd_En_q <= Rd_En_d;
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if( Rd_En = '1' )then
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Rd_Data <= OPEN8_NULLBUS;
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if( Rd_En_q = '1' )then
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Rd_Data <= lfsr_q(31 downto 24);
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Rd_Data <= lfsr_q(31 downto 24);
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lfsr_q <= lfsr_q(23 downto 0) & x"00";
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lfsr_q <= lfsr_q(23 downto 0) & x"00";
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if( Reg_Sel_q = '1' )then
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if( Reg_Sel_q = '1' )then
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Rd_Data <= lfsr_q(31) & "0000000";
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Rd_Data <= lfsr_q(31) & "0000000";
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lfsr_q <= lfsr_q(30 downto 0) & '0';
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lfsr_q <= lfsr_q(30 downto 0) & '0';
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end if;
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end if;
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end if;
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end if;
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if( or_reduce(lfsr_q) = '0' )then
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if( or_reduce(lfsr_q) = '0' )then
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lfsr_q <= lfsr;
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lfsr_q <= lfsr;
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lfsr <= lfsr(30 downto 0) & d0;
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lfsr <= lfsr(30 downto 0) & d0;
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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