-- Copyright (c)2018, 2020 Jeremy Seth Henry
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-- Copyright (c)2018, 2020 Jeremy Seth Henry
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-- All rights reserved.
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-- All rights reserved.
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--
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--
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-- Redistribution and use in source and binary forms, with or without
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-- Redistribution and use in source and binary forms, with or without
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-- modification, are permitted provided that the following conditions are met:
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-- modification, are permitted provided that the following conditions are met:
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-- * Redistributions of source code must retain the above copyright
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-- * Redistributions of source code must retain the above copyright
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-- notice, this list of conditions and the following disclaimer.
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-- notice, this list of conditions and the following disclaimer.
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-- * Redistributions in binary form must reproduce the above copyright
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-- * Redistributions in binary form must reproduce the above copyright
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-- notice, this list of conditions and the following disclaimer in the
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-- notice, this list of conditions and the following disclaimer in the
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-- documentation and/or other materials provided with the distribution,
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-- documentation and/or other materials provided with the distribution,
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-- where applicable (as part of a user interface, debugging port, etc.)
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-- where applicable (as part of a user interface, debugging port, etc.)
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--
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--
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-- THIS SOFTWARE IS PROVIDED BY JEREMY SETH HENRY ``AS IS'' AND ANY
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-- THIS SOFTWARE IS PROVIDED BY JEREMY SETH HENRY ``AS IS'' AND ANY
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-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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-- DISCLAIMED. IN NO EVENT SHALL JEREMY SETH HENRY BE LIABLE FOR ANY
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-- DISCLAIMED. IN NO EVENT SHALL JEREMY SETH HENRY BE LIABLE FOR ANY
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-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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-- THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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-- THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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--
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--
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-- VHDL Units : o8_pwm16
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-- VHDL Units : o8_pwm16
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-- Description: Provides a 16-bit standard PWM output with 1 uSec resolution,
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-- Description: Provides a 16-bit standard PWM output with 1 uSec resolution,
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-- as well as CPU interrupt on overflow. Note that the PWM
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-- as well as CPU interrupt on overflow. Note that the PWM
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-- timers reload from registers on overflow, not on write
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-- timers reload from registers on overflow, not on write
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--
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--
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-- Register Map:
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-- Register Map:
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-- Offset Bitfield Description Read/Write
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-- Offset Bitfield Description Read/Write
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-- 0x00 AAAAAAAA Period (lower byte) (RW)
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-- 0x00 AAAAAAAA Period (lower byte) (RW)
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-- 0x01 AAAAAAAA Period (upper byte) (RW)
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-- 0x01 AAAAAAAA Period (upper byte) (RW)
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-- 0x02 AAAAAAAA Width (lower byte) (RW)
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-- 0x02 AAAAAAAA Width (lower byte) (RW)
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-- 0x03 AAAAAAAA Width (upper byte) (RW)
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-- 0x03 AAAAAAAA Width (upper byte) (RW)
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-- 0x04 A------- Timer Status (RW)
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-- 0x04 A------- Timer Status (RW)
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-- A: Enabled on '1' / Disable on '0'
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-- A: Enabled on '1' / Disable on '0'
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--
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--
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-- Revision History
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-- Revision History
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-- Author Date Change
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-- Author Date Change
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------------------ -------- ---------------------------------------------------
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------------------ -------- ---------------------------------------------------
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-- Seth Henry 04/25/18 Design Start
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-- Seth Henry 04/25/18 Design Start
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-- Seth Henry 04/10/20 Code cleanup and comments
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-- Seth Henry 04/10/20 Code cleanup and comments
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-- Seth Henry 04/16/20 Modified to use Open8 bus record
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_misc.all;
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use ieee.std_logic_misc.all;
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library work;
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library work;
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use work.open8_pkg.all;
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use work.open8_pkg.all;
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entity o8_pwm16 is
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entity o8_pwm16 is
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generic(
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generic(
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Reset_Level : std_logic;
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Address : ADDRESS_TYPE
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Address : ADDRESS_TYPE
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);
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);
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port(
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port(
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Clock : in std_logic;
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Reset : in std_logic;
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uSec_Tick : in std_logic;
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--
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Open8_Bus : in OPEN8_BUS_TYPE;
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Open8_Bus : in OPEN8_BUS_TYPE;
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Rd_Data : out DATA_TYPE;
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Rd_Data : out DATA_TYPE;
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Interrupt : out std_logic;
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Interrupt : out std_logic;
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--
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--
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PWM_Out : out std_logic
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PWM_Out : out std_logic
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);
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);
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end entity;
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end entity;
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architecture behave of o8_pwm16 is
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architecture behave of o8_pwm16 is
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alias Clock is Open8_Bus.Clock;
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alias Reset is Open8_Bus.Reset;
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alias uSec_Tick is Open8_Bus.uSec_Tick;
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constant User_Addr : std_logic_vector(15 downto 3) :=
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constant User_Addr : std_logic_vector(15 downto 3) :=
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Address(15 downto 3);
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Address(15 downto 3);
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alias Comp_Addr is Open8_Bus.Address(15 downto 3);
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alias Comp_Addr is Open8_Bus.Address(15 downto 3);
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signal Addr_Match : std_logic := '0';
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signal Addr_Match : std_logic := '0';
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alias Reg_Addr is Open8_Bus.Address(2 downto 0);
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alias Reg_Addr is Open8_Bus.Address(2 downto 0);
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signal Reg_Addr_q : std_logic_vector(2 downto 0) := (others => '0');
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signal Reg_Addr_q : std_logic_vector(2 downto 0) := (others => '0');
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signal Wr_En : std_logic := '0';
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signal Wr_En : std_logic := '0';
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signal Wr_Data_q : DATA_TYPE := x"00";
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signal Wr_Data_q : DATA_TYPE := x"00";
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signal Rd_En : std_logic := '0';
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signal Rd_En : std_logic := '0';
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signal PWM_Enable : std_logic := '0';
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signal PWM_Enable : std_logic := '0';
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signal PWM_Period : std_logic_vector(15 downto 0) := (others => '0');
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signal PWM_Period : std_logic_vector(15 downto 0) := (others => '0');
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alias PWM_Period_l is PWM_Period(7 downto 0);
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alias PWM_Period_l is PWM_Period(7 downto 0);
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alias PWM_Period_u is PWM_Period(15 downto 8);
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alias PWM_Period_u is PWM_Period(15 downto 8);
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signal PWM_Width : std_logic_vector(15 downto 0) := (others => '0');
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signal PWM_Width : std_logic_vector(15 downto 0) := (others => '0');
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alias PWM_Width_l is PWM_Width(7 downto 0);
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alias PWM_Width_l is PWM_Width(7 downto 0);
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alias PWM_Width_u is PWM_Width(15 downto 8);
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alias PWM_Width_u is PWM_Width(15 downto 8);
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signal Period_Ctr : std_logic_vector(15 downto 0) := (others => '0');
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signal Period_Ctr : std_logic_vector(15 downto 0) := (others => '0');
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signal Width_Ctr : std_logic_vector(15 downto 0) := (others => '0');
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signal Width_Ctr : std_logic_vector(15 downto 0) := (others => '0');
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begin
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begin
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Addr_Match <= '1' when Comp_Addr = User_Addr else '0';
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Addr_Match <= '1' when Comp_Addr = User_Addr else '0';
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PWM_proc: process( Clock, Reset )
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PWM_proc: process( Clock, Reset )
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begin
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begin
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if( Reset = Reset_Level )then
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if( Reset = Reset_Level )then
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Wr_Data_q <= (others => '0');
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Wr_Data_q <= (others => '0');
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Reg_Addr_q <= (others => '0');
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Reg_Addr_q <= (others => '0');
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Wr_En <= '0';
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Wr_En <= '0';
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Rd_En <= '0';
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Rd_En <= '0';
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Rd_Data <= x"00";
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Rd_Data <= x"00";
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Interrupt <= '0';
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Interrupt <= '0';
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PWM_Enable <= '0';
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PWM_Enable <= '0';
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PWM_Period <= (others => '0');
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PWM_Period <= (others => '0');
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PWM_Width <= (others => '0');
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PWM_Width <= (others => '0');
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Period_Ctr <= (others => '0');
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Period_Ctr <= (others => '0');
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Width_Ctr <= (others => '0');
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Width_Ctr <= (others => '0');
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PWM_Out <= '0';
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PWM_Out <= '0';
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elsif( rising_edge(Clock) )then
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elsif( rising_edge(Clock) )then
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Reg_Addr_q <= Reg_Addr;
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Reg_Addr_q <= Reg_Addr;
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Wr_Data_q <= Open8_Bus.Wr_Data;
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Wr_Data_q <= Open8_Bus.Wr_Data;
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Wr_En <= Addr_Match and Open8_Bus.Wr_En;
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Wr_En <= Addr_Match and Open8_Bus.Wr_En;
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if( Wr_En = '1' )then
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if( Wr_En = '1' )then
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case( Reg_Addr_q )is
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case( Reg_Addr_q )is
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when "000" =>
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when "000" =>
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PWM_Period_l <= Wr_Data_q;
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PWM_Period_l <= Wr_Data_q;
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when "001" =>
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when "001" =>
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PWM_Period_u <= Wr_Data_q;
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PWM_Period_u <= Wr_Data_q;
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when "010" =>
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when "010" =>
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PWM_Width_l <= Wr_Data_q;
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PWM_Width_l <= Wr_Data_q;
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when "011" =>
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when "011" =>
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PWM_Width_u <= Wr_Data_q;
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PWM_Width_u <= Wr_Data_q;
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when "100" | "101" | "110" | "111" =>
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when "100" | "101" | "110" | "111" =>
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PWM_Enable <= Wr_Data_q(7);
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PWM_Enable <= Wr_Data_q(7);
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when others => null;
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when others => null;
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end case;
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end case;
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end if;
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end if;
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Rd_Data <= (others => '0');
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Rd_Data <= (others => '0');
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Rd_En <= Addr_Match and Open8_Bus.Rd_En;
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Rd_En <= Addr_Match and Open8_Bus.Rd_En;
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if( Rd_En = '1' )then
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if( Rd_En = '1' )then
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case( Reg_Addr_q )is
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case( Reg_Addr_q )is
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when "000" =>
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when "000" =>
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Rd_Data <= PWM_Period_l;
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Rd_Data <= PWM_Period_l;
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when "001" =>
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when "001" =>
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Rd_Data <= PWM_Period_u;
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Rd_Data <= PWM_Period_u;
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when "010" =>
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when "010" =>
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Rd_Data <= PWM_Width_l;
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Rd_Data <= PWM_Width_l;
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when "011" =>
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when "011" =>
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Rd_Data <= PWM_Width_u;
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Rd_Data <= PWM_Width_u;
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when "100" | "101" | "110" | "111" =>
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when "100" | "101" | "110" | "111" =>
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Rd_Data <= PWM_Enable & "0000000";
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Rd_Data <= PWM_Enable & "0000000";
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when others => null;
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when others => null;
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end case;
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end case;
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end if;
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end if;
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Interrupt <= '0';
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Interrupt <= '0';
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Period_Ctr <= Period_Ctr - uSec_tick;
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Period_Ctr <= Period_Ctr - uSec_tick;
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Width_Ctr <= Width_Ctr - uSec_tick;
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Width_Ctr <= Width_Ctr - uSec_tick;
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-- Stop the width counter from rolling over at 0
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-- Stop the width counter from rolling over at 0
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if( or_reduce(Width_Ctr) = '0' )then
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if( or_reduce(Width_Ctr) = '0' )then
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Width_Ctr <= (others => '0');
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Width_Ctr <= (others => '0');
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end if;
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end if;
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-- Reload both counters when period reaches 0
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-- Reload both counters when period reaches 0
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if( or_reduce(Period_Ctr) = '0' )then
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if( or_reduce(Period_Ctr) = '0' )then
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Period_Ctr <= PWM_Period;
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Period_Ctr <= PWM_Period;
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Width_Ctr <= PWM_Width;
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Width_Ctr <= PWM_Width;
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Interrupt <= '1';
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Interrupt <= '1';
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end if;
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end if;
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-- Drive the output high as long as Width > 0 and PWM_Enable is high
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-- Drive the output high as long as Width > 0 and PWM_Enable is high
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PWM_Out <= or_reduce(Width_Ctr) and PWM_Enable;
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PWM_Out <= or_reduce(Width_Ctr) and PWM_Enable;
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-- If the counter is disabled, reload the counters, and drive the output
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-- If the counter is disabled, reload the counters, and drive the output
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-- low.
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-- low.
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if( PWM_Enable = '0' )then
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if( PWM_Enable = '0' )then
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Period_Ctr <= PWM_Period;
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Period_Ctr <= PWM_Period;
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Width_Ctr <= PWM_Width;
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Width_Ctr <= PWM_Width;
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Interrupt <= '0';
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Interrupt <= '0';
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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end architecture;
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end architecture;
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