-- Copyright (c)2020 Jeremy Seth Henry
|
-- Copyright (c)2020 Jeremy Seth Henry
|
-- All rights reserved.
|
-- All rights reserved.
|
--
|
--
|
-- Redistribution and use in source and binary forms, with or without
|
-- Redistribution and use in source and binary forms, with or without
|
-- modification, are permitted provided that the following conditions are met:
|
-- modification, are permitted provided that the following conditions are met:
|
-- * Redistributions of source code must retain the above copyright
|
-- * Redistributions of source code must retain the above copyright
|
-- notice, this list of conditions and the following disclaimer.
|
-- notice, this list of conditions and the following disclaimer.
|
-- * Redistributions in binary form must reproduce the above copyright
|
-- * Redistributions in binary form must reproduce the above copyright
|
-- notice, this list of conditions and the following disclaimer in the
|
-- notice, this list of conditions and the following disclaimer in the
|
-- documentation and/or other materials provided with the distribution,
|
-- documentation and/or other materials provided with the distribution,
|
-- where applicable (as part of a user interface, debugging port, etc.)
|
-- where applicable (as part of a user interface, debugging port, etc.)
|
--
|
--
|
-- THIS SOFTWARE IS PROVIDED BY JEREMY SETH HENRY ``AS IS'' AND ANY
|
-- THIS SOFTWARE IS PROVIDED BY JEREMY SETH HENRY ``AS IS'' AND ANY
|
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
-- DISCLAIMED. IN NO EVENT SHALL JEREMY SETH HENRY BE LIABLE FOR ANY
|
-- DISCLAIMED. IN NO EVENT SHALL JEREMY SETH HENRY BE LIABLE FOR ANY
|
-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
--
|
--
|
-- VHDL Entity: pwm_adc
|
-- VHDL Entity: pwm_adc
|
-- Description: Integrates a PWM input to return the approximate duty cycle
|
-- Description: Integrates a PWM input to return the approximate duty cycle
|
-- Uses a 1kB block ram as storage for a rolling integrator that
|
-- Uses a 1kB block ram as storage for a rolling integrator that
|
-- acts as a simple successive-approximation ADC.
|
-- acts as a simple successive-approximation ADC.
|
--
|
--
|
-- Revision History
|
-- Revision History
|
-- Author Date Change
|
-- Author Date Change
|
------------------ -------- ---------------------------------------------------
|
------------------ -------- ---------------------------------------------------
|
-- Seth Henry 05/07/20 Design Start
|
-- Seth Henry 05/07/20 Design Start
|
|
|
library ieee;
|
library ieee;
|
use ieee.std_logic_1164.all;
|
use ieee.std_logic_1164.all;
|
use ieee.std_logic_unsigned.all;
|
use ieee.std_logic_unsigned.all;
|
|
|
library work;
|
library work;
|
use work.open8_pkg.all;
|
use work.open8_pkg.all;
|
|
|
entity o8_pwm_adc is
|
entity o8_pwm_adc is
|
generic(
|
generic(
|
Address : ADDRESS_TYPE
|
Address : ADDRESS_TYPE
|
);
|
);
|
port(
|
port(
|
Open8_Bus : in OPEN8_BUS_TYPE;
|
Open8_Bus : in OPEN8_BUS_TYPE;
|
Rd_Data : out DATA_TYPE;
|
Rd_Data : out DATA_TYPE;
|
--
|
--
|
PWM_In : in std_logic
|
PWM_In : in std_logic
|
);
|
);
|
end entity;
|
end entity;
|
|
|
architecture behave of o8_pwm_adc is
|
architecture behave of o8_pwm_adc is
|
|
|
alias Clock is Open8_Bus.Clock;
|
alias Clock is Open8_Bus.Clock;
|
alias Reset is Open8_Bus.Reset;
|
alias Reset is Open8_Bus.Reset;
|
alias uSec_Tick is Open8_Bus.uSec_Tick;
|
alias uSec_Tick is Open8_Bus.uSec_Tick;
|
|
|
constant User_Addr : std_logic_vector(15 downto 0) := Address(15 downto 0);
|
constant User_Addr : std_logic_vector(15 downto 0) := Address(15 downto 0);
|
alias Comp_Addr is Open8_Bus.Address(15 downto 0);
|
alias Comp_Addr is Open8_Bus.Address(15 downto 0);
|
|
|
signal Addr_Match : std_logic := '0';
|
signal Addr_Match : std_logic := '0';
|
signal Rd_En : std_logic := '0';
|
signal Rd_En_d : std_logic := '0';
|
|
signal Rd_En_q : std_logic := '0';
|
|
|
signal Sample : DATA_TYPE := x"00";
|
signal Sample : DATA_TYPE := x"00";
|
signal RAM_Addr : std_logic_vector(9 downto 0) := (others => '0');
|
signal RAM_Addr : std_logic_vector(9 downto 0) := (others => '0');
|
signal RAM_Data : DATA_TYPE := x"00";
|
signal RAM_Data : DATA_TYPE := x"00";
|
signal Accumulator : std_logic_vector(17 downto 0) := (others => '0');
|
signal Accumulator : std_logic_vector(17 downto 0) := (others => '0');
|
signal Average : DATA_TYPE := x"00";
|
signal Average : DATA_TYPE := x"00";
|
begin
|
begin
|
|
|
Addr_Match <= Open8_Bus.Rd_En when Comp_Addr = User_Addr else '0';
|
Addr_Match <= '1' when Comp_Addr = User_Addr else '0';
|
|
Rd_En_d <= Addr_Match and Open8_Bus.Rd_En;
|
|
|
io_reg: process( Clock, Reset )
|
io_reg: process( Clock, Reset )
|
begin
|
begin
|
if( Reset = Reset_Level )then
|
if( Reset = Reset_Level )then
|
Rd_En <= '0';
|
Rd_En_q <= '0';
|
Rd_Data <= OPEN8_NULLBUS;
|
Rd_Data <= OPEN8_NULLBUS;
|
|
|
elsif( rising_edge( Clock ) )then
|
elsif( rising_edge( Clock ) )then
|
|
|
Rd_En <= Addr_Match and Open8_Bus.Rd_En;
|
Rd_En_q <= Rd_En_d;
|
Rd_Data <= OPEN8_NULLBUS;
|
Rd_Data <= OPEN8_NULLBUS;
|
|
if( Rd_En_q = '1' )then
|
if( Rd_En = '1' )then
|
|
Rd_Data <= Average;
|
Rd_Data <= Average;
|
end if;
|
end if;
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
-- PWM input is binary, so the sample swings between 0x00 and 0xFF
|
-- PWM input is binary, so the sample swings between 0x00 and 0xFF
|
Sample <= (others => PWM_In);
|
Sample <= (others => PWM_In);
|
|
|
U_DP : entity work.o8_pwm_adc_ram
|
U_DP : entity work.o8_pwm_adc_ram
|
port map(
|
port map(
|
address => RAM_Addr,
|
address => RAM_Addr,
|
clock => Clock,
|
clock => Clock,
|
data => Sample,
|
data => Sample,
|
wren => '1',
|
wren => '1',
|
q => RAM_Data
|
q => RAM_Data
|
);
|
);
|
|
|
ADC_proc: process( Clock, Reset )
|
ADC_proc: process( Clock, Reset )
|
begin
|
begin
|
if( Reset = Reset_Level )then
|
if( Reset = Reset_Level )then
|
RAM_Addr <= (others => '0');
|
RAM_Addr <= (others => '0');
|
Accumulator <= (others => '0');
|
Accumulator <= (others => '0');
|
Average <= (others => '0');
|
Average <= (others => '0');
|
elsif( rising_edge(Clock) )then
|
elsif( rising_edge(Clock) )then
|
RAM_Addr <= RAM_Addr + 1;
|
RAM_Addr <= RAM_Addr + 1;
|
Accumulator <= Accumulator + ("0000000000" & RAM_Data);
|
Accumulator <= Accumulator + ("0000000000" & RAM_Data);
|
if( RAM_Addr = 0 )then
|
if( RAM_Addr = 0 )then
|
Accumulator <= (others => '0');
|
Accumulator <= (others => '0');
|
Average <= Accumulator(17 downto 10);
|
Average <= Accumulator(17 downto 10);
|
end if;
|
end if;
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
|
|