-- Copyright (c)2020 Jeremy Seth Henry
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-- Copyright (c)2020 Jeremy Seth Henry
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-- All rights reserved.
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-- All rights reserved.
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--
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--
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-- Redistribution and use in source and binary forms, with or without
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-- Redistribution and use in source and binary forms, with or without
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-- modification, are permitted provided that the following conditions are met:
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-- modification, are permitted provided that the following conditions are met:
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-- * Redistributions of source code must retain the above copyright
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-- * Redistributions of source code must retain the above copyright
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-- notice, this list of conditions and the following disclaimer.
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-- notice, this list of conditions and the following disclaimer.
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-- * Redistributions in binary form must reproduce the above copyright
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-- * Redistributions in binary form must reproduce the above copyright
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-- notice, this list of conditions and the following disclaimer in the
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-- notice, this list of conditions and the following disclaimer in the
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-- documentation and/or other materials provided with the distribution,
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-- documentation and/or other materials provided with the distribution,
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-- where applicable (as part of a user interface, debugging port, etc.)
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-- where applicable (as part of a user interface, debugging port, etc.)
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--
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--
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-- THIS SOFTWARE IS PROVIDED BY JEREMY SETH HENRY ``AS IS'' AND ANY
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-- THIS SOFTWARE IS PROVIDED BY JEREMY SETH HENRY ``AS IS'' AND ANY
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-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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-- DISCLAIMED. IN NO EVENT SHALL JEREMY SETH HENRY BE LIABLE FOR ANY
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-- DISCLAIMED. IN NO EVENT SHALL JEREMY SETH HENRY BE LIABLE FOR ANY
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-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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--
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--
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-- VHDL Entity: pwm_adc
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-- VHDL Entity: pwm_adc
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-- Description: Integrates a PWM input to return the approximate duty cycle
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-- Description: Integrates a PWM input to return the approximate duty cycle
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-- Uses a 1kB block ram as storage for a rolling integrator that
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-- Uses a 1kB block ram as storage for a rolling integrator that
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-- acts as a simple successive-approximation ADC.
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-- acts as a simple successive-approximation ADC.
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--
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--
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-- Revision History
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-- Revision History
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-- Author Date Change
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-- Author Date Change
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------------------ -------- ---------------------------------------------------
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------------------ -------- ---------------------------------------------------
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-- Seth Henry 05/07/20 Design Start
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-- Seth Henry 05/07/20 Design Start
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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library work;
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library work;
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use work.open8_pkg.all;
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use work.open8_pkg.all;
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entity o8_pwm_adc is
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entity o8_pwm_adc is
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generic(
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generic(
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Address : ADDRESS_TYPE
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Address : ADDRESS_TYPE
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);
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);
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port(
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port(
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Open8_Bus : in OPEN8_BUS_TYPE;
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Open8_Bus : in OPEN8_BUS_TYPE;
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Rd_Data : out DATA_TYPE;
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Rd_Data : out DATA_TYPE;
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--
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--
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PWM_In : in std_logic
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PWM_In : in std_logic
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);
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);
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end entity;
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end entity;
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architecture behave of o8_pwm_adc is
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architecture behave of o8_pwm_adc is
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alias Clock is Open8_Bus.Clock;
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alias Clock is Open8_Bus.Clock;
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alias Reset is Open8_Bus.Reset;
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alias Reset is Open8_Bus.Reset;
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alias uSec_Tick is Open8_Bus.uSec_Tick;
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alias uSec_Tick is Open8_Bus.uSec_Tick;
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constant User_Addr : std_logic_vector(15 downto 0) := Address(15 downto 0);
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constant User_Addr : std_logic_vector(15 downto 0) := Address(15 downto 0);
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alias Comp_Addr is Open8_Bus.Address(15 downto 0);
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alias Comp_Addr is Open8_Bus.Address(15 downto 0);
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signal Addr_Match : std_logic := '0';
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signal Addr_Match : std_logic := '0';
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signal Rd_En : std_logic := '0';
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signal Rd_En_d : std_logic := '0';
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signal Rd_En_q : std_logic := '0';
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signal Sample : DATA_TYPE := x"00";
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signal Sample : DATA_TYPE := x"00";
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signal RAM_Addr : std_logic_vector(9 downto 0) := (others => '0');
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signal RAM_Addr : std_logic_vector(9 downto 0) := (others => '0');
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signal RAM_Data : DATA_TYPE := x"00";
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signal RAM_Data : DATA_TYPE := x"00";
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signal Accumulator : std_logic_vector(17 downto 0) := (others => '0');
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signal Accumulator : std_logic_vector(17 downto 0) := (others => '0');
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signal Average : DATA_TYPE := x"00";
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signal Average : DATA_TYPE := x"00";
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begin
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begin
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Addr_Match <= Open8_Bus.Rd_En when Comp_Addr = User_Addr else '0';
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Addr_Match <= '1' when Comp_Addr = User_Addr else '0';
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Rd_En_d <= Addr_Match and Open8_Bus.Rd_En;
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io_reg: process( Clock, Reset )
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io_reg: process( Clock, Reset )
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begin
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begin
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if( Reset = Reset_Level )then
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if( Reset = Reset_Level )then
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Rd_En <= '0';
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Rd_En_q <= '0';
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Rd_Data <= OPEN8_NULLBUS;
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Rd_Data <= OPEN8_NULLBUS;
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elsif( rising_edge( Clock ) )then
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elsif( rising_edge( Clock ) )then
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Rd_En <= Addr_Match and Open8_Bus.Rd_En;
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Rd_En_q <= Rd_En_d;
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Rd_Data <= OPEN8_NULLBUS;
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Rd_Data <= OPEN8_NULLBUS;
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if( Rd_En_q = '1' )then
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if( Rd_En = '1' )then
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Rd_Data <= Average;
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Rd_Data <= Average;
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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-- PWM input is binary, so the sample swings between 0x00 and 0xFF
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-- PWM input is binary, so the sample swings between 0x00 and 0xFF
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Sample <= (others => PWM_In);
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Sample <= (others => PWM_In);
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U_DP : entity work.o8_pwm_adc_ram
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U_DP : entity work.o8_pwm_adc_ram
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port map(
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port map(
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address => RAM_Addr,
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address => RAM_Addr,
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clock => Clock,
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clock => Clock,
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data => Sample,
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data => Sample,
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wren => '1',
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wren => '1',
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q => RAM_Data
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q => RAM_Data
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);
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);
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ADC_proc: process( Clock, Reset )
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ADC_proc: process( Clock, Reset )
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begin
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begin
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if( Reset = Reset_Level )then
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if( Reset = Reset_Level )then
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RAM_Addr <= (others => '0');
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RAM_Addr <= (others => '0');
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Accumulator <= (others => '0');
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Accumulator <= (others => '0');
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Average <= (others => '0');
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Average <= (others => '0');
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elsif( rising_edge(Clock) )then
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elsif( rising_edge(Clock) )then
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RAM_Addr <= RAM_Addr + 1;
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RAM_Addr <= RAM_Addr + 1;
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Accumulator <= Accumulator + ("0000000000" & RAM_Data);
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Accumulator <= Accumulator + ("0000000000" & RAM_Data);
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if( RAM_Addr = 0 )then
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if( RAM_Addr = 0 )then
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Accumulator <= (others => '0');
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Accumulator <= (others => '0');
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Average <= Accumulator(17 downto 10);
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Average <= Accumulator(17 downto 10);
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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