-- Copyright (c)2023 Jeremy Seth Henry
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-- Copyright (c)2023 Jeremy Seth Henry
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-- All rights reserved.
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-- All rights reserved.
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--
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--
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-- Redistribution and use in source and binary forms, with or without
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-- Redistribution and use in source and binary forms, with or without
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-- modification, are permitted provided that the following conditions are met:
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-- modification, are permitted provided that the following conditions are met:
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-- * Redistributions of source code must retain the above copyright
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-- * Redistributions of source code must retain the above copyright
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-- notice, this list of conditions and the following disclaimer.
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-- notice, this list of conditions and the following disclaimer.
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-- * Redistributions in binary form must reproduce the above copyright
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-- * Redistributions in binary form must reproduce the above copyright
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-- notice, this list of conditions and the following disclaimer in the
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-- notice, this list of conditions and the following disclaimer in the
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-- documentation and/or other materials provided with the distribution,
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-- documentation and/or other materials provided with the distribution,
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-- where applicable (as part of a user interface, debugging port, etc.)
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-- where applicable (as part of a user interface, debugging port, etc.)
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--
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--
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-- THIS SOFTWARE IS PROVIDED BY JEREMY SETH HENRY ``AS IS'' AND ANY
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-- THIS SOFTWARE IS PROVIDED BY JEREMY SETH HENRY ``AS IS'' AND ANY
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-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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-- DISCLAIMED. IN NO EVENT SHALL JEREMY SETH HENRY BE LIABLE FOR ANY
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-- DISCLAIMED. IN NO EVENT SHALL JEREMY SETH HENRY BE LIABLE FOR ANY
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-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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-- THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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-- THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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--
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--
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-- VHDL units : o8_scale_conv
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-- VHDL units : o8_scale_conv
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-- Description: Performs the operation ACC = [(A*B)/C] + D, returning a 33-bit
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-- Description: Performs the operation ACC = [(A*B)/C] + D, returning a 33-bit
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-- value. Optionally converts this value into packed BCD format.
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-- value. Optionally converts this value into packed BCD format.
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--
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--
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-- Note1: Operands A,B are 16-bit values. The output from this step is a 32-bit
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-- Note1: Operands A,B are 16-bit values. The output from this step is a 32-bit
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-- value, which can be divided by Operand C, with the result added to
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-- value, which can be divided by Operand C, with the result added to
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-- Operand D. Both operand C and D are 32-bit values.
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-- Operand D. Both operand C and D are 32-bit values.
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-- Note2: If the operation type is '1', or SIGNED, then operand A,B, and D
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-- Note2: If the operation type is '1', or SIGNED, then operand A,B, and D
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-- will be treated as SIGNED values, while operand C remains UNSIGNED
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-- will be treated as SIGNED values, while operand C remains UNSIGNED
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-- If the operation type is '0', or UNSIGNED, all operands will be
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-- If the operation type is '0', or UNSIGNED, all operands will be
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-- treated as UNSIGNED values.
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-- treated as UNSIGNED values.
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-- Note3: Setting Operand C to 0 or 1 will skip the division step. This
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-- Note3: Setting Operand C to 0 or 1 will skip the division step. This
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-- resolves the issue of divide by 0, as 0 will be treated as 1, as
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-- resolves the issue of divide by 0, as 0 will be treated as 1, as
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-- well as saving time if the division isn't required.
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-- well as saving time if the division isn't required.
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--
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--
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-- Register Map:
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-- Register Map:
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-- Offset Bitfield Description Read/Write
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-- Offset Bitfield Description Read/Write
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-- 0x00 AAAAAAAA Operand A, Lower Byte RW
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-- 0x00 AAAAAAAA Operand A, Lower Byte (RW)
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-- 0x01 AAAAAAAA Operand A, Upper Byte RW
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-- 0x01 AAAAAAAA Operand A, Upper Byte (RW)
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-- 0x02 AAAAAAAA Operand B, Lower Byte RW
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-- 0x02 AAAAAAAA Operand B, Lower Byte (RW)
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-- 0x03 AAAAAAAA Operand B, Upper Byte RW
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-- 0x03 AAAAAAAA Operand B, Upper Byte (RW)
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-- 0x04 AAAAAAAA Operand C, Byte 0 RW
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-- 0x04 AAAAAAAA Operand C, Byte 0 (RW)
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-- 0x05 AAAAAAAA Operand C, Byte 1 RW
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-- 0x05 AAAAAAAA Operand C, Byte 1 (RW)
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-- 0x06 AAAAAAAA Operand C, Byte 2 RW
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-- 0x06 AAAAAAAA Operand C, Byte 2 (RW)
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-- 0x07 AAAAAAAA Operand C, Byte 3 RW
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-- 0x07 AAAAAAAA Operand C, Byte 3 (RW)
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-- 0x08 AAAAAAAA Operand D, Byte 0 RW
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-- 0x08 AAAAAAAA Operand D, Byte 0 (RW)
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-- 0x09 AAAAAAAA Operand D, Byte 1 RW
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-- 0x09 AAAAAAAA Operand D, Byte 1 (RW)
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-- 0x0A AAAAAAAA Operand D, Byte 2 RW
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-- 0x0A AAAAAAAA Operand D, Byte 2 (RW)
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-- 0x0B AAAAAAAA Operand D, Byte 3 RW
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-- 0x0B AAAAAAAA Operand D, Byte 3 (RW)
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--
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-- 0x10 AAAAAAAA Accumulator, Byte 0 R0
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-- 0x10 AAAAAAAA Accumulator, Byte 0 (R0)
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-- 0x11 AAAAAAAA Accumulator, Byte 1 R0
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-- 0x11 AAAAAAAA Accumulator, Byte 1 (R0)
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-- 0x12 AAAAAAAA Accumulator, Byte 2 R0
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-- 0x12 AAAAAAAA Accumulator, Byte 2 (R0)
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-- 0x13 AAAAAAAA Accumulator, Byte 3 R0
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-- 0x13 AAAAAAAA Accumulator, Byte 3 (R0)
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-- 0x14 A------- Accumulator, Sign / Bit 32 R0
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-- 0x14 A------- Accumulator, Sign / Bit 32 (R0)
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--
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-- 0x18 AAAAAAAA BCD Data, Digits 1,0 RO
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-- 0x18 AAAAAAAA BCD Data, Digits 1,0 (RO)
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-- 0x19 AAAAAAAA BCD Data, Digits 3,2 RO
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-- 0x19 AAAAAAAA BCD Data, Digits 3,2 (RO)
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-- 0x1A AAAAAAAA BCD Data, Digits 5,4 RO
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-- 0x1A AAAAAAAA BCD Data, Digits 5,4 (RO)
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-- 0x1B AAAAAAAA BCD Data, Digits 7,6 RO
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-- 0x1B AAAAAAAA BCD Data, Digits 7,6 (RO)
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-- 0x1C AAAAAAAA BCD Data, Digits 9,8 RO
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-- 0x1C AAAAAAAA BCD Data, Digits 9,8 (RO)
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-- 0x1D A------- BCD Data, Sign [pos (0), neg (1)] R0
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-- 0x1D A------- BCD Data, Sign [pos (0), neg (1)] (RO)
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--
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-- 0x1F C-----BA Control/Status RW
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-- 0x1F C-----BA Control/Status (RW)
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-- A = Operation Type:
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-- A = Operation Type:
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-- Unsigned (0) / Signed (1)
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-- Unsigned (0) / Signed (1)
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-- B = BCD conversion (if set) (WR)*
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-- B = BCD conversion (if set) (WR)*
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-- BCD result valid if set (RD)
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-- BCD result valid if set (RD)
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-- C = Conversion Status (1 = busy)
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-- C = Conversion Status (1 = busy)
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--
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--
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-- Note4: Setting bit 1 TRUE will enable the packed BCD conversion system
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-- Note4: Setting bit 1 TRUE will enable the packed BCD conversion system
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-- at the cost of ~3.5uS per conversion. If the most recent result
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-- at the cost of ~3.5uS per conversion. If the most recent result
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-- was converted, reading this bit will return a '1' to indicate
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-- was converted, reading this bit will return a '1' to indicate
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-- that the data is "fresh", or matches the raw result data.
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-- that the data is "fresh", or matches the raw result data.
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-- Setting this bit FALSE will allow a new math operation to occur
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-- Setting this bit FALSE will allow a new math operation to occur
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-- WITHOUT altering the last BCD conversion, but will set this bit to
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-- WITHOUT altering the last BCD conversion, but will set this bit to
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-- 0 on read to indicate that the BCD value is "stale", or no longer
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-- 0 on read to indicate that the BCD value is "stale", or no longer
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-- matches the raw result data.
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-- matches the raw result data.
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--
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--
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-- Revision History
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-- Revision History
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-- Author Date Change
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-- Author Date Change
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------------------ -------- ---------------------------------------------------
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------------------ -------- ---------------------------------------------------
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-- Seth Henry 04/10/23 Initial Design
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-- Seth Henry 04/10/23 Initial Design
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_signed.all;
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use ieee.std_logic_signed.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_misc.all;
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use ieee.std_logic_misc.all;
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library work;
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library work;
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use work.open8_pkg.all;
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use work.open8_pkg.all;
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use work.open8_cfg.all;
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use work.open8_cfg.all;
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entity o8_scale_conv is
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entity o8_scale_conv is
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generic(
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generic(
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Address : ADDRESS_TYPE
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Address : ADDRESS_TYPE
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);
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);
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port(
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port(
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-- Bus IF Interface
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-- Bus IF Interface
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Open8_Bus : in OPEN8_BUS_TYPE;
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Open8_Bus : in OPEN8_BUS_TYPE;
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Write_Qual : in std_logic;
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Write_Qual : in std_logic;
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Rd_Data : out DATA_TYPE;
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Rd_Data : out DATA_TYPE;
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Interrupt : out std_logic
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Interrupt : out std_logic
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);
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);
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end entity;
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end entity;
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architecture behave of o8_scale_conv is
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architecture behave of o8_scale_conv is
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-- Bus Interface Signals
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-- Bus Interface Signals
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alias Clock is Open8_Bus.Clock;
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alias Clock is Open8_Bus.Clock;
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alias Reset is Open8_Bus.Reset;
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alias Reset is Open8_Bus.Reset;
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alias uSec_Tick is Open8_Bus.uSec_Tick;
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alias uSec_Tick is Open8_Bus.uSec_Tick;
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constant User_Addr : std_logic_vector(15 downto 5) :=
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constant User_Addr : std_logic_vector(15 downto 5) :=
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Address(15 downto 5);
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Address(15 downto 5);
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alias Comp_Addr is Open8_Bus.Address(15 downto 5);
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alias Comp_Addr is Open8_Bus.Address(15 downto 5);
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signal Addr_Match : std_logic := '0';
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signal Addr_Match : std_logic := '0';
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alias Reg_Sel_d is Open8_Bus.Address(4 downto 0);
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alias Reg_Sel_d is Open8_Bus.Address(4 downto 0);
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signal Reg_Sel_q : std_logic_vector(4 downto 0) := (others => '0');
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signal Reg_Sel_q : std_logic_vector(4 downto 0) := (others => '0');
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signal Wr_En_d : std_logic := '0';
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signal Wr_En_d : std_logic := '0';
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signal Wr_En_q : std_logic := '0';
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signal Wr_En_q : std_logic := '0';
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alias Wr_Data_d is Open8_Bus.Wr_Data;
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alias Wr_Data_d is Open8_Bus.Wr_Data;
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signal Wr_Data_q : DATA_TYPE := x"00";
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signal Wr_Data_q : DATA_TYPE := x"00";
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signal Rd_En_d : std_logic := '0';
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signal Rd_En_d : std_logic := '0';
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signal Rd_En_q : std_logic := '0';
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signal Rd_En_q : std_logic := '0';
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-- Operands A, B, and C are 16-bit with sign-extension, or 17-bit values
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-- Operands A, B, and C are 16-bit with sign-extension, or 17-bit values
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constant OPER_ABC_WIDTH : integer := 17;
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constant OPER_ABC_WIDTH : integer := 17;
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signal OperandA : signed(OPER_ABC_WIDTH - 1 downto 0) :=
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signal OperandA : signed(OPER_ABC_WIDTH - 1 downto 0) :=
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(others => '0');
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(others => '0');
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alias OperandA_LB is OperandA(7 downto 0);
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alias OperandA_LB is OperandA(7 downto 0);
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alias OperandA_UB is OperandA(15 downto 8);
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alias OperandA_UB is OperandA(15 downto 8);
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alias OperandA_S is OperandA(15);
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alias OperandA_S is OperandA(15);
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alias OperandA_SX is OperandA(OPER_ABC_WIDTH - 1 downto 16);
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alias OperandA_SX is OperandA(OPER_ABC_WIDTH - 1 downto 16);
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signal OperandB : signed(OPER_ABC_WIDTH - 1 downto 0) :=
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signal OperandB : signed(OPER_ABC_WIDTH - 1 downto 0) :=
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(others => '0');
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(others => '0');
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alias OperandB_LB is OperandB(7 downto 0);
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alias OperandB_LB is OperandB(7 downto 0);
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alias OperandB_UB is OperandB(15 downto 8);
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alias OperandB_UB is OperandB(15 downto 8);
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alias OperandB_S is OperandB(15);
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alias OperandB_S is OperandB(15);
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alias OperandB_SX is OperandB(OPER_ABC_WIDTH - 1 downto 16);
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alias OperandB_SX is OperandB(OPER_ABC_WIDTH - 1 downto 16);
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-- The product will, by definition, be twice as wide as the input operands
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-- The product will, by definition, be twice as wide as the input operands
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constant MULT_WIDTH : integer := 2*OPER_ABC_WIDTH;
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constant MULT_WIDTH : integer := 2*OPER_ABC_WIDTH;
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signal Product_AB : signed(MULT_WIDTH - 1 downto 0) :=
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signal Product_AB : signed(MULT_WIDTH - 1 downto 0) :=
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(others => '0');
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(others => '0');
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-- The divider only needs a single bit for sign extension, so drop one
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-- The divider only needs a single bit for sign extension, so drop one
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-- bit from the multiplier width
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-- bit from the multiplier width
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constant DIVIDER_WIDTH : integer := MULT_WIDTH - 1;
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constant DIVIDER_WIDTH : integer := MULT_WIDTH - 1;
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alias Operand_AB is Product_AB(DIVIDER_WIDTH - 1 downto 0);
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alias Operand_AB is Product_AB(DIVIDER_WIDTH - 1 downto 0);
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signal OperandC : signed(DIVIDER_WIDTH - 1 downto 0) :=
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signal OperandC : signed(DIVIDER_WIDTH - 1 downto 0) :=
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(others => '0');
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(others => '0');
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alias OperandC_B0 is OperandC(7 downto 0);
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alias OperandC_B0 is OperandC(7 downto 0);
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alias OperandC_B1 is OperandC(15 downto 8);
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alias OperandC_B1 is OperandC(15 downto 8);
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alias OperandC_B2 is OperandC(23 downto 16);
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alias OperandC_B2 is OperandC(23 downto 16);
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alias OperandC_B3 is OperandC(31 downto 24);
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alias OperandC_B3 is OperandC(31 downto 24);
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alias OperandC_SX is OperandC(DIVIDER_WIDTH - 1 downto 32);
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alias OperandC_SX is OperandC(DIVIDER_WIDTH - 1 downto 32);
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signal OperandABC : signed(DIVIDER_WIDTH - 1 downto 0) :=
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signal OperandABC : signed(DIVIDER_WIDTH - 1 downto 0) :=
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(others => '0');
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(others => '0');
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signal OperandD : signed(DIVIDER_WIDTH - 1 downto 0) :=
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signal OperandD : signed(DIVIDER_WIDTH - 1 downto 0) :=
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(others => '0');
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(others => '0');
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alias OperandD_B0 is OperandD(7 downto 0);
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alias OperandD_B0 is OperandD(7 downto 0);
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alias OperandD_B1 is OperandD(15 downto 8);
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alias OperandD_B1 is OperandD(15 downto 8);
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alias OperandD_B2 is OperandD(23 downto 16);
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alias OperandD_B2 is OperandD(23 downto 16);
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alias OperandD_B3 is OperandD(31 downto 24);
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alias OperandD_B3 is OperandD(31 downto 24);
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alias OperandD_S is OperandD(31);
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alias OperandD_S is OperandD(31);
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alias OperandD_SX is OperandD(DIVIDER_WIDTH - 1 downto 32);
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alias OperandD_SX is OperandD(DIVIDER_WIDTH - 1 downto 32);
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signal Accumulator : signed(DIVIDER_WIDTH - 1 downto 0) :=
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signal Accumulator : signed(DIVIDER_WIDTH - 1 downto 0) :=
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(others => '0');
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(others => '0');
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alias RAW_Data_B0 is Accumulator(7 downto 0);
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alias RAW_Data_B0 is Accumulator(7 downto 0);
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alias RAW_Data_B1 is Accumulator(15 downto 8);
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alias RAW_Data_B1 is Accumulator(15 downto 8);
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alias RAW_Data_B2 is Accumulator(23 downto 16);
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alias RAW_Data_B2 is Accumulator(23 downto 16);
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alias RAW_Data_B3 is Accumulator(31 downto 24);
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alias RAW_Data_B3 is Accumulator(31 downto 24);
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alias RAW_Sign_MSB is Accumulator(32);
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alias RAW_Sign_MSB is Accumulator(32);
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-- Conversion control signals
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-- Conversion control signals
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type CONV_STATES is ( IDLE,
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type CONV_STATES is ( IDLE,
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MULT_WAIT,
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MULT_WAIT,
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DIV_START, DIV_WAIT, DIV_SKIP,
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DIV_START, DIV_WAIT, DIV_SKIP,
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ACCUM_WAIT,
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ACCUM_WAIT,
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DAA_INIT, DAA_NEGATE,
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DAA_INIT, DAA_NEGATE,
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DAA_STEP1, DAA_WAIT1,
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DAA_STEP1, DAA_WAIT1,
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DAA_STEP2, DAA_WAIT2,
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DAA_STEP2, DAA_WAIT2,
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DAA_STEP3, DAA_WAIT3,
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DAA_STEP3, DAA_WAIT3,
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DAA_STEP4, DAA_WAIT4,
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DAA_STEP4, DAA_WAIT4,
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DAA_STEP5, DAA_WAIT5,
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DAA_STEP5, DAA_WAIT5,
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DAA_STEP6, DAA_WAIT6,
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DAA_STEP6, DAA_WAIT6,
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DAA_STEP7, DAA_WAIT7,
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DAA_STEP7, DAA_WAIT7,
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DAA_STEP8, DAA_WAIT8,
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DAA_STEP8, DAA_WAIT8,
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DAA_STEP9, DAA_WAIT9,
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DAA_STEP9, DAA_WAIT9,
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DAA_DONE );
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DAA_DONE );
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signal Conv_State : CONV_STATES := IDLE;
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signal Conv_State : CONV_STATES := IDLE;
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signal CNV_En : std_logic := '0';
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signal CNV_En : std_logic := '0';
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signal DAA_En : std_logic := '0';
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signal DAA_En : std_logic := '0';
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signal CNV_Busy : std_logic := '0';
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signal CNV_Busy : std_logic := '0';
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signal CNV_Mode : std_logic := '0';
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signal CNV_Mode : std_logic := '0';
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constant CNV_SIGNED : std_logic := '1';
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constant CNV_SIGNED : std_logic := '1';
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constant CNV_UNSIGNED : std_logic := '0';
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constant CNV_UNSIGNED : std_logic := '0';
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signal CNV_Done : std_logic := '0';
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signal CNV_Done : std_logic := '0';
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-- Decimal adjust / BCD conversion signals
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-- Decimal adjust / BCD conversion signals
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signal DAA_Valid : std_logic := '0';
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signal DAA_Valid : std_logic := '0';
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constant DAA_ST1_DIV : std_logic_vector(DIVIDER_WIDTH - 1 downto 0) :=
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constant DAA_ST1_DIV : std_logic_vector(DIVIDER_WIDTH - 1 downto 0) :=
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conv_std_logic_vector(1000000000,DIVIDER_WIDTH);
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conv_std_logic_vector(1000000000,DIVIDER_WIDTH);
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constant DAA_ST2_DIV : std_logic_vector(DIVIDER_WIDTH - 1 downto 0) :=
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constant DAA_ST2_DIV : std_logic_vector(DIVIDER_WIDTH - 1 downto 0) :=
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conv_std_logic_vector(100000000,DIVIDER_WIDTH);
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conv_std_logic_vector(100000000,DIVIDER_WIDTH);
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constant DAA_ST3_DIV : std_logic_vector(DIVIDER_WIDTH - 1 downto 0) :=
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constant DAA_ST3_DIV : std_logic_vector(DIVIDER_WIDTH - 1 downto 0) :=
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conv_std_logic_vector(10000000,DIVIDER_WIDTH);
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conv_std_logic_vector(10000000,DIVIDER_WIDTH);
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constant DAA_ST4_DIV : std_logic_vector(DIVIDER_WIDTH - 1 downto 0) :=
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constant DAA_ST4_DIV : std_logic_vector(DIVIDER_WIDTH - 1 downto 0) :=
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conv_std_logic_vector(1000000,DIVIDER_WIDTH);
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conv_std_logic_vector(1000000,DIVIDER_WIDTH);
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constant DAA_ST5_DIV : std_logic_vector(DIVIDER_WIDTH - 1 downto 0) :=
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constant DAA_ST5_DIV : std_logic_vector(DIVIDER_WIDTH - 1 downto 0) :=
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conv_std_logic_vector(100000,DIVIDER_WIDTH);
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conv_std_logic_vector(100000,DIVIDER_WIDTH);
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constant DAA_ST6_DIV : std_logic_vector(DIVIDER_WIDTH - 1 downto 0) :=
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constant DAA_ST6_DIV : std_logic_vector(DIVIDER_WIDTH - 1 downto 0) :=
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conv_std_logic_vector(10000,DIVIDER_WIDTH);
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conv_std_logic_vector(10000,DIVIDER_WIDTH);
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constant DAA_ST7_DIV : std_logic_vector(DIVIDER_WIDTH - 1 downto 0) :=
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constant DAA_ST7_DIV : std_logic_vector(DIVIDER_WIDTH - 1 downto 0) :=
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conv_std_logic_vector(1000,DIVIDER_WIDTH);
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conv_std_logic_vector(1000,DIVIDER_WIDTH);
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constant DAA_ST8_DIV : std_logic_vector(DIVIDER_WIDTH - 1 downto 0) :=
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constant DAA_ST8_DIV : std_logic_vector(DIVIDER_WIDTH - 1 downto 0) :=
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conv_std_logic_vector(100,DIVIDER_WIDTH);
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conv_std_logic_vector(100,DIVIDER_WIDTH);
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constant DAA_ST9_DIV : std_logic_vector(DIVIDER_WIDTH - 1 downto 0) :=
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constant DAA_ST9_DIV : std_logic_vector(DIVIDER_WIDTH - 1 downto 0) :=
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conv_std_logic_vector(10,DIVIDER_WIDTH);
|
conv_std_logic_vector(10,DIVIDER_WIDTH);
|
|
|
signal DAA_Next : std_logic_vector(DIVIDER_WIDTH - 1 downto 0) :=
|
signal DAA_Next : std_logic_vector(DIVIDER_WIDTH - 1 downto 0) :=
|
(others => '0');
|
(others => '0');
|
|
|
signal DAA_Sign : std_logic := '0';
|
signal DAA_Sign : std_logic := '0';
|
|
|
signal DAA_Buffer : std_logic_vector(39 downto 0) := (others => '0');
|
signal DAA_Buffer : std_logic_vector(39 downto 0) := (others => '0');
|
|
|
alias DAA_Data_B0 is DAA_Buffer(7 downto 0);
|
alias DAA_Data_B0 is DAA_Buffer(7 downto 0);
|
alias DAA_Data_B1 is DAA_Buffer(15 downto 8);
|
alias DAA_Data_B1 is DAA_Buffer(15 downto 8);
|
alias DAA_Data_B2 is DAA_Buffer(23 downto 16);
|
alias DAA_Data_B2 is DAA_Buffer(23 downto 16);
|
alias DAA_Data_B3 is DAA_Buffer(31 downto 24);
|
alias DAA_Data_B3 is DAA_Buffer(31 downto 24);
|
alias DAA_Data_B4 is DAA_Buffer(39 downto 32);
|
alias DAA_Data_B4 is DAA_Buffer(39 downto 32);
|
|
|
alias DAA_Digit_0 is DAA_Buffer( 3 downto 0);
|
alias DAA_Digit_0 is DAA_Buffer( 3 downto 0);
|
alias DAA_Digit_1 is DAA_Buffer( 7 downto 4);
|
alias DAA_Digit_1 is DAA_Buffer( 7 downto 4);
|
alias DAA_Digit_2 is DAA_Buffer(11 downto 8);
|
alias DAA_Digit_2 is DAA_Buffer(11 downto 8);
|
alias DAA_Digit_3 is DAA_Buffer(15 downto 12);
|
alias DAA_Digit_3 is DAA_Buffer(15 downto 12);
|
alias DAA_Digit_4 is DAA_Buffer(19 downto 16);
|
alias DAA_Digit_4 is DAA_Buffer(19 downto 16);
|
alias DAA_Digit_5 is DAA_Buffer(23 downto 20);
|
alias DAA_Digit_5 is DAA_Buffer(23 downto 20);
|
alias DAA_Digit_6 is DAA_Buffer(27 downto 24);
|
alias DAA_Digit_6 is DAA_Buffer(27 downto 24);
|
alias DAA_Digit_7 is DAA_Buffer(31 downto 28);
|
alias DAA_Digit_7 is DAA_Buffer(31 downto 28);
|
alias DAA_Digit_8 is DAA_Buffer(35 downto 32);
|
alias DAA_Digit_8 is DAA_Buffer(35 downto 32);
|
alias DAA_Digit_9 is DAA_Buffer(39 downto 36);
|
alias DAA_Digit_9 is DAA_Buffer(39 downto 36);
|
|
|
-- Integer divide unit signals
|
-- Integer divide unit signals
|
|
|
signal Div_Enable : std_logic := '0';
|
signal Div_Enable : std_logic := '0';
|
signal Div_Busy : std_logic := '0';
|
signal Div_Busy : std_logic := '0';
|
|
|
signal Dividend : std_logic_vector(DIVIDER_WIDTH - 1 downto 0) :=
|
signal Dividend : std_logic_vector(DIVIDER_WIDTH - 1 downto 0) :=
|
(others => '0');
|
(others => '0');
|
|
|
signal Divisor : std_logic_vector(DIVIDER_WIDTH - 1 downto 0) :=
|
signal Divisor : std_logic_vector(DIVIDER_WIDTH - 1 downto 0) :=
|
(others => '0');
|
(others => '0');
|
|
|
signal Quotient : std_logic_vector(DIVIDER_WIDTH - 1 downto 0) :=
|
signal Quotient : std_logic_vector(DIVIDER_WIDTH - 1 downto 0) :=
|
(others => '0');
|
(others => '0');
|
|
|
signal Remainder : std_logic_vector(DIVIDER_WIDTH - 1 downto 0) :=
|
signal Remainder : std_logic_vector(DIVIDER_WIDTH - 1 downto 0) :=
|
(others => '0');
|
(others => '0');
|
|
|
begin
|
begin
|
|
|
Addr_Match <= '1' when Comp_Addr = User_Addr else '0';
|
Addr_Match <= '1' when Comp_Addr = User_Addr else '0';
|
Wr_En_d <= Addr_Match and Open8_Bus.Wr_En and Write_Qual;
|
Wr_En_d <= Addr_Match and Open8_Bus.Wr_En and Write_Qual;
|
Rd_En_d <= Addr_Match and Open8_Bus.Rd_En;
|
Rd_En_d <= Addr_Match and Open8_Bus.Rd_En;
|
|
|
reg_proc: process( Clock, Reset )
|
reg_proc: process( Clock, Reset )
|
begin
|
begin
|
if( Reset = Reset_Level )then
|
if( Reset = Reset_Level )then
|
Reg_Sel_q <= (others => '0');
|
Reg_Sel_q <= (others => '0');
|
Wr_En_q <= '0';
|
Wr_En_q <= '0';
|
Wr_Data_q <= x"00";
|
Wr_Data_q <= x"00";
|
Rd_En_q <= '0';
|
Rd_En_q <= '0';
|
Rd_Data <= OPEN8_NULLBUS;
|
Rd_Data <= OPEN8_NULLBUS;
|
|
|
OperandA <= (others => '0');
|
OperandA <= (others => '0');
|
OperandB <= (others => '0');
|
OperandB <= (others => '0');
|
OperandC <= (others => '0');
|
OperandC <= (others => '0');
|
OperandD <= (others => '0');
|
OperandD <= (others => '0');
|
|
|
CNV_En <= '0';
|
CNV_En <= '0';
|
DAA_En <= '0';
|
DAA_En <= '0';
|
CNV_Mode <= '0';
|
CNV_Mode <= '0';
|
CNV_Busy <= '0';
|
CNV_Busy <= '0';
|
|
|
Interrupt <= '0';
|
Interrupt <= '0';
|
|
|
elsif( rising_edge(Clock) )then
|
elsif( rising_edge(Clock) )then
|
Reg_Sel_q <= Reg_Sel_d;
|
Reg_Sel_q <= Reg_Sel_d;
|
|
|
Wr_En_q <= Wr_En_d;
|
Wr_En_q <= Wr_En_d;
|
Wr_Data_q <= Wr_Data_d;
|
Wr_Data_q <= Wr_Data_d;
|
|
|
CNV_En <= '0';
|
CNV_En <= '0';
|
|
|
if( Wr_En_q = '1' )then
|
if( Wr_En_q = '1' )then
|
case( Reg_Sel_q )is
|
case( Reg_Sel_q )is
|
when "00000" =>
|
when "00000" =>
|
OperandA_LB <= signed(Wr_Data_q);
|
OperandA_LB <= signed(Wr_Data_q);
|
when "00001" =>
|
when "00001" =>
|
OperandA_UB <= signed(Wr_Data_q);
|
OperandA_UB <= signed(Wr_Data_q);
|
when "00010" =>
|
when "00010" =>
|
OperandB_LB <= signed(Wr_Data_q);
|
OperandB_LB <= signed(Wr_Data_q);
|
when "00011" =>
|
when "00011" =>
|
OperandB_UB <= signed(Wr_Data_q);
|
OperandB_UB <= signed(Wr_Data_q);
|
when "00100" =>
|
when "00100" =>
|
OperandC_B0 <= signed(Wr_Data_q);
|
OperandC_B0 <= signed(Wr_Data_q);
|
when "00101" =>
|
when "00101" =>
|
OperandC_B1 <= signed(Wr_Data_q);
|
OperandC_B1 <= signed(Wr_Data_q);
|
when "00110" =>
|
when "00110" =>
|
OperandC_B2 <= signed(Wr_Data_q);
|
OperandC_B2 <= signed(Wr_Data_q);
|
when "00111" =>
|
when "00111" =>
|
OperandC_B3 <= signed(Wr_Data_q);
|
OperandC_B3 <= signed(Wr_Data_q);
|
when "01000" =>
|
when "01000" =>
|
OperandD_B0 <= signed(Wr_Data_q);
|
OperandD_B0 <= signed(Wr_Data_q);
|
when "01001" =>
|
when "01001" =>
|
OperandD_B1 <= signed(Wr_Data_q);
|
OperandD_B1 <= signed(Wr_Data_q);
|
when "01010" =>
|
when "01010" =>
|
OperandD_B2 <= signed(Wr_Data_q);
|
OperandD_B2 <= signed(Wr_Data_q);
|
when "01011" =>
|
when "01011" =>
|
OperandD_B3 <= signed(Wr_Data_q);
|
OperandD_B3 <= signed(Wr_Data_q);
|
|
|
when "11111" =>
|
when "11111" =>
|
CNV_Mode <= Wr_Data_q(0);
|
CNV_Mode <= Wr_Data_q(0);
|
DAA_En <= Wr_Data_q(1);
|
DAA_En <= Wr_Data_q(1);
|
CNV_En <= '1';
|
CNV_En <= '1';
|
CNV_Busy <= '1';
|
CNV_Busy <= '1';
|
when others => null;
|
when others => null;
|
end case;
|
end case;
|
end if;
|
end if;
|
|
|
Interrupt <= '0';
|
Interrupt <= '0';
|
if( CNV_Done = '1' )then
|
if( CNV_Done = '1' )then
|
CNV_Busy <= '0';
|
CNV_Busy <= '0';
|
Interrupt <= '1';
|
Interrupt <= '1';
|
end if;
|
end if;
|
|
|
OperandA_SX <= (others => '0');
|
OperandA_SX <= (others => '0');
|
OperandB_SX <= (others => '0');
|
OperandB_SX <= (others => '0');
|
OperandC_SX <= (others => '0');
|
OperandC_SX <= (others => '0');
|
OperandD_SX <= (others => '0');
|
OperandD_SX <= (others => '0');
|
|
|
if( CNV_Mode = CNV_SIGNED )then
|
if( CNV_Mode = CNV_SIGNED )then
|
OperandA_SX <= (others => OperandA_S);
|
OperandA_SX <= (others => OperandA_S);
|
OperandB_SX <= (others => OperandB_S);
|
OperandB_SX <= (others => OperandB_S);
|
OperandD_SX <= (others => OperandD_S);
|
OperandD_SX <= (others => OperandD_S);
|
end if;
|
end if;
|
|
|
Rd_En_q <= Rd_En_d;
|
Rd_En_q <= Rd_En_d;
|
Rd_Data <= OPEN8_NULLBUS;
|
Rd_Data <= OPEN8_NULLBUS;
|
if( Rd_En_q = '1' )then
|
if( Rd_En_q = '1' )then
|
case( Reg_Sel_q )is
|
case( Reg_Sel_q )is
|
-- Input operands
|
-- Input operands
|
when "00000" =>
|
when "00000" =>
|
Rd_Data <= std_logic_vector(OperandA_LB);
|
Rd_Data <= std_logic_vector(OperandA_LB);
|
when "00001" =>
|
when "00001" =>
|
Rd_Data <= std_logic_vector(OperandA_UB);
|
Rd_Data <= std_logic_vector(OperandA_UB);
|
when "00010" =>
|
when "00010" =>
|
Rd_Data <= std_logic_vector(OperandB_LB);
|
Rd_Data <= std_logic_vector(OperandB_LB);
|
when "00011" =>
|
when "00011" =>
|
Rd_Data <= std_logic_vector(OperandB_UB);
|
Rd_Data <= std_logic_vector(OperandB_UB);
|
when "00100" =>
|
when "00100" =>
|
Rd_Data <= std_logic_vector(OperandC_B0);
|
Rd_Data <= std_logic_vector(OperandC_B0);
|
when "00101" =>
|
when "00101" =>
|
Rd_Data <= std_logic_vector(OperandC_B1);
|
Rd_Data <= std_logic_vector(OperandC_B1);
|
when "00110" =>
|
when "00110" =>
|
Rd_Data <= std_logic_vector(OperandC_B2);
|
Rd_Data <= std_logic_vector(OperandC_B2);
|
when "00111" =>
|
when "00111" =>
|
Rd_Data <= std_logic_vector(OperandC_B3);
|
Rd_Data <= std_logic_vector(OperandC_B3);
|
when "01000" =>
|
when "01000" =>
|
Rd_Data <= std_logic_vector(OperandD_B0);
|
Rd_Data <= std_logic_vector(OperandD_B0);
|
when "01001" =>
|
when "01001" =>
|
Rd_Data <= std_logic_vector(OperandD_B1);
|
Rd_Data <= std_logic_vector(OperandD_B1);
|
when "01010" =>
|
when "01010" =>
|
Rd_Data <= std_logic_vector(OperandD_B2);
|
Rd_Data <= std_logic_vector(OperandD_B2);
|
when "01011" =>
|
when "01011" =>
|
Rd_Data <= std_logic_vector(OperandD_B3);
|
Rd_Data <= std_logic_vector(OperandD_B3);
|
|
|
-- Raw results
|
-- Raw results
|
when "10000" =>
|
when "10000" =>
|
Rd_Data <= std_logic_vector(RAW_Data_B0);
|
Rd_Data <= std_logic_vector(RAW_Data_B0);
|
when "10001" =>
|
when "10001" =>
|
Rd_Data <= std_logic_vector(RAW_Data_B1);
|
Rd_Data <= std_logic_vector(RAW_Data_B1);
|
when "10010" =>
|
when "10010" =>
|
Rd_Data <= std_logic_vector(RAW_Data_B2);
|
Rd_Data <= std_logic_vector(RAW_Data_B2);
|
when "10011" =>
|
when "10011" =>
|
Rd_Data <= std_logic_vector(RAW_Data_B3);
|
Rd_Data <= std_logic_vector(RAW_Data_B3);
|
when "10100" =>
|
when "10100" =>
|
Rd_Data(7) <= RAW_Sign_MSB;
|
Rd_Data(7) <= RAW_Sign_MSB;
|
|
|
-- BCD Conversion
|
-- BCD Conversion
|
when "11000" =>
|
when "11000" =>
|
Rd_Data <= DAA_Data_B0;
|
Rd_Data <= DAA_Data_B0;
|
when "11001" =>
|
when "11001" =>
|
Rd_Data <= DAA_Data_B1;
|
Rd_Data <= DAA_Data_B1;
|
when "11010" =>
|
when "11010" =>
|
Rd_Data <= DAA_Data_B2;
|
Rd_Data <= DAA_Data_B2;
|
when "11011" =>
|
when "11011" =>
|
Rd_Data <= DAA_Data_B3;
|
Rd_Data <= DAA_Data_B3;
|
when "11100" =>
|
when "11100" =>
|
Rd_Data <= DAA_Data_B4;
|
Rd_Data <= DAA_Data_B4;
|
when "11101" =>
|
when "11101" =>
|
Rd_Data(7) <= DAA_Sign;
|
Rd_Data(7) <= DAA_Sign;
|
|
|
-- Control/Status
|
-- Control/Status
|
when "11111" =>
|
when "11111" =>
|
Rd_Data(0) <= CNV_Mode;
|
Rd_Data(0) <= CNV_Mode;
|
Rd_Data(1) <= DAA_Valid;
|
Rd_Data(1) <= DAA_Valid;
|
Rd_Data(7) <= CNV_Busy;
|
Rd_Data(7) <= CNV_Busy;
|
when others => null;
|
when others => null;
|
end case;
|
end case;
|
end if;
|
end if;
|
|
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
Conversion_FSM_proc: process( Clock, Reset )
|
Conversion_FSM_proc: process( Clock, Reset )
|
begin
|
begin
|
if( Reset = Reset_Level )then
|
if( Reset = Reset_Level )then
|
Conv_State <= IDLE;
|
Conv_State <= IDLE;
|
Div_Enable <= '0';
|
Div_Enable <= '0';
|
Dividend <= (others => '0');
|
Dividend <= (others => '0');
|
Divisor <= (others => '0');
|
Divisor <= (others => '0');
|
OperandABC <= (others => '0');
|
OperandABC <= (others => '0');
|
Accumulator <= (others => '0');
|
Accumulator <= (others => '0');
|
DAA_Sign <= '0';
|
DAA_Sign <= '0';
|
DAA_Buffer <= (others => '0');
|
DAA_Buffer <= (others => '0');
|
DAA_Next <= (others => '0');
|
DAA_Next <= (others => '0');
|
CNV_Done <= '0';
|
CNV_Done <= '0';
|
elsif( rising_edge(Clock) )then
|
elsif( rising_edge(Clock) )then
|
|
|
Div_Enable <= '0';
|
Div_Enable <= '0';
|
CNV_Done <= '0';
|
CNV_Done <= '0';
|
|
|
case Conv_State is
|
case Conv_State is
|
when IDLE =>
|
when IDLE =>
|
if( CNV_En = '1' )then
|
if( CNV_En = '1' )then
|
Conv_State <= MULT_WAIT;
|
Conv_State <= MULT_WAIT;
|
end if;
|
end if;
|
|
|
when MULT_WAIT =>
|
when MULT_WAIT =>
|
-- Skip division if the operand is < 2
|
-- Skip division if the operand is < 2
|
Conv_State <= DIV_SKIP;
|
Conv_State <= DIV_SKIP;
|
if( OperandC > 1 )then
|
if( OperandC > 1 )then
|
Conv_State <= DIV_START;
|
Conv_State <= DIV_START;
|
end if;
|
end if;
|
|
|
when DIV_START =>
|
when DIV_START =>
|
Div_Enable <= '1';
|
Div_Enable <= '1';
|
Dividend <= std_logic_vector(Operand_AB);
|
Dividend <= std_logic_vector(Operand_AB);
|
Divisor <= std_logic_vector(OperandC);
|
Divisor <= std_logic_vector(OperandC);
|
if( Div_Busy = '1' )then
|
if( Div_Busy = '1' )then
|
Conv_State <= DIV_WAIT;
|
Conv_State <= DIV_WAIT;
|
end if;
|
end if;
|
|
|
when DIV_WAIT =>
|
when DIV_WAIT =>
|
if( Div_Busy = '0' )then
|
if( Div_Busy = '0' )then
|
OperandABC <= signed(Quotient);
|
OperandABC <= signed(Quotient);
|
Conv_State <= ACCUM_WAIT;
|
Conv_State <= ACCUM_WAIT;
|
end if;
|
end if;
|
|
|
when DIV_SKIP =>
|
when DIV_SKIP =>
|
OperandABC <= Operand_AB;
|
OperandABC <= Operand_AB;
|
Conv_State <= ACCUM_WAIT;
|
Conv_State <= ACCUM_WAIT;
|
|
|
when ACCUM_WAIT =>
|
when ACCUM_WAIT =>
|
Conv_State <= DAA_INIT;
|
Conv_State <= DAA_INIT;
|
if( DAA_En = '0' )then
|
if( DAA_En = '0' )then
|
DAA_Valid <= '0';
|
DAA_Valid <= '0';
|
CNV_Done <= '1';
|
CNV_Done <= '1';
|
Conv_State <= IDLE;
|
Conv_State <= IDLE;
|
end if;
|
end if;
|
|
|
when DAA_INIT =>
|
when DAA_INIT =>
|
DAA_Sign <= '0';
|
DAA_Sign <= '0';
|
DAA_Next <= std_logic_vector(Accumulator);
|
DAA_Next <= std_logic_vector(Accumulator);
|
Conv_State <= DAA_STEP1;
|
Conv_State <= DAA_STEP1;
|
if( RAW_Sign_MSB = '1' and CNV_Mode = CNV_SIGNED )then
|
if( RAW_Sign_MSB = '1' and CNV_Mode = CNV_SIGNED )then
|
Conv_State <= DAA_NEGATE;
|
Conv_State <= DAA_NEGATE;
|
end if;
|
end if;
|
|
|
when DAA_NEGATE =>
|
when DAA_NEGATE =>
|
DAA_Sign <= '1';
|
DAA_Sign <= '1';
|
DAA_Next <= (not DAA_Next) + 1;
|
DAA_Next <= (not DAA_Next) + 1;
|
Conv_State <= DAA_STEP1;
|
Conv_State <= DAA_STEP1;
|
|
|
when DAA_STEP1 =>
|
when DAA_STEP1 =>
|
Dividend <= DAA_Next;
|
Dividend <= DAA_Next;
|
Divisor <= DAA_ST1_DIV;
|
Divisor <= DAA_ST1_DIV;
|
Div_Enable <= '1';
|
Div_Enable <= '1';
|
if( DIV_Busy = '1' )then
|
if( DIV_Busy = '1' )then
|
Conv_State <= DAA_WAIT1;
|
Conv_State <= DAA_WAIT1;
|
end if;
|
end if;
|
|
|
when DAA_WAIT1 =>
|
when DAA_WAIT1 =>
|
if( DIV_Busy = '0' )then
|
if( DIV_Busy = '0' )then
|
DAA_Digit_9 <= Quotient(3 downto 0);
|
DAA_Digit_9 <= Quotient(3 downto 0);
|
DAA_Next <= Remainder;
|
DAA_Next <= Remainder;
|
Conv_State <= DAA_STEP2;
|
Conv_State <= DAA_STEP2;
|
end if;
|
end if;
|
|
|
when DAA_STEP2 =>
|
when DAA_STEP2 =>
|
Dividend <= DAA_Next;
|
Dividend <= DAA_Next;
|
Divisor <= DAA_ST2_DIV;
|
Divisor <= DAA_ST2_DIV;
|
Div_Enable <= '1';
|
Div_Enable <= '1';
|
if( DIV_Busy = '1' )then
|
if( DIV_Busy = '1' )then
|
Conv_State <= DAA_WAIT2;
|
Conv_State <= DAA_WAIT2;
|
end if;
|
end if;
|
|
|
when DAA_WAIT2 =>
|
when DAA_WAIT2 =>
|
if( DIV_Busy = '0' )then
|
if( DIV_Busy = '0' )then
|
DAA_Digit_8 <= Quotient(3 downto 0);
|
DAA_Digit_8 <= Quotient(3 downto 0);
|
DAA_Next <= Remainder;
|
DAA_Next <= Remainder;
|
Conv_State <= DAA_STEP3;
|
Conv_State <= DAA_STEP3;
|
end if;
|
end if;
|
|
|
when DAA_STEP3 =>
|
when DAA_STEP3 =>
|
Dividend <= DAA_Next;
|
Dividend <= DAA_Next;
|
Divisor <= DAA_ST3_DIV;
|
Divisor <= DAA_ST3_DIV;
|
Div_Enable <= '1';
|
Div_Enable <= '1';
|
if( DIV_Busy = '1' )then
|
if( DIV_Busy = '1' )then
|
Conv_State <= DAA_WAIT3;
|
Conv_State <= DAA_WAIT3;
|
end if;
|
end if;
|
|
|
when DAA_WAIT3 =>
|
when DAA_WAIT3 =>
|
if( DIV_Busy = '0' )then
|
if( DIV_Busy = '0' )then
|
DAA_Digit_7 <= Quotient(3 downto 0);
|
DAA_Digit_7 <= Quotient(3 downto 0);
|
DAA_Next <= Remainder;
|
DAA_Next <= Remainder;
|
Conv_State <= DAA_STEP4;
|
Conv_State <= DAA_STEP4;
|
end if;
|
end if;
|
|
|
when DAA_STEP4 =>
|
when DAA_STEP4 =>
|
Dividend <= DAA_Next;
|
Dividend <= DAA_Next;
|
Divisor <= DAA_ST4_DIV;
|
Divisor <= DAA_ST4_DIV;
|
Div_Enable <= '1';
|
Div_Enable <= '1';
|
if( DIV_Busy = '1' )then
|
if( DIV_Busy = '1' )then
|
Conv_State <= DAA_WAIT4;
|
Conv_State <= DAA_WAIT4;
|
end if;
|
end if;
|
|
|
when DAA_WAIT4 =>
|
when DAA_WAIT4 =>
|
if( DIV_Busy = '0' )then
|
if( DIV_Busy = '0' )then
|
DAA_Digit_6 <= Quotient(3 downto 0);
|
DAA_Digit_6 <= Quotient(3 downto 0);
|
DAA_Next <= Remainder;
|
DAA_Next <= Remainder;
|
Conv_State <= DAA_STEP5;
|
Conv_State <= DAA_STEP5;
|
end if;
|
end if;
|
|
|
when DAA_STEP5 =>
|
when DAA_STEP5 =>
|
Dividend <= DAA_Next;
|
Dividend <= DAA_Next;
|
Divisor <= DAA_ST5_DIV;
|
Divisor <= DAA_ST5_DIV;
|
Div_Enable <= '1';
|
Div_Enable <= '1';
|
if( DIV_Busy = '1' )then
|
if( DIV_Busy = '1' )then
|
Conv_State <= DAA_WAIT5;
|
Conv_State <= DAA_WAIT5;
|
end if;
|
end if;
|
|
|
when DAA_WAIT5 =>
|
when DAA_WAIT5 =>
|
if( DIV_Busy = '0' )then
|
if( DIV_Busy = '0' )then
|
DAA_Digit_5 <= Quotient(3 downto 0);
|
DAA_Digit_5 <= Quotient(3 downto 0);
|
DAA_Next <= Remainder;
|
DAA_Next <= Remainder;
|
Conv_State <= DAA_STEP6;
|
Conv_State <= DAA_STEP6;
|
end if;
|
end if;
|
|
|
when DAA_STEP6 =>
|
when DAA_STEP6 =>
|
Dividend <= DAA_Next;
|
Dividend <= DAA_Next;
|
Divisor <= DAA_ST6_DIV;
|
Divisor <= DAA_ST6_DIV;
|
Div_Enable <= '1';
|
Div_Enable <= '1';
|
if( DIV_Busy = '1' )then
|
if( DIV_Busy = '1' )then
|
Conv_State <= DAA_WAIT6;
|
Conv_State <= DAA_WAIT6;
|
end if;
|
end if;
|
|
|
when DAA_WAIT6 =>
|
when DAA_WAIT6 =>
|
if( DIV_Busy = '0' )then
|
if( DIV_Busy = '0' )then
|
DAA_Digit_4 <= Quotient(3 downto 0);
|
DAA_Digit_4 <= Quotient(3 downto 0);
|
DAA_Next <= Remainder;
|
DAA_Next <= Remainder;
|
Conv_State <= DAA_STEP7;
|
Conv_State <= DAA_STEP7;
|
end if;
|
end if;
|
|
|
when DAA_STEP7 =>
|
when DAA_STEP7 =>
|
Dividend <= DAA_Next;
|
Dividend <= DAA_Next;
|
Divisor <= DAA_ST7_DIV;
|
Divisor <= DAA_ST7_DIV;
|
Div_Enable <= '1';
|
Div_Enable <= '1';
|
if( DIV_Busy = '1' )then
|
if( DIV_Busy = '1' )then
|
Conv_State <= DAA_WAIT7;
|
Conv_State <= DAA_WAIT7;
|
end if;
|
end if;
|
|
|
when DAA_WAIT7 =>
|
when DAA_WAIT7 =>
|
if( DIV_Busy = '0' )then
|
if( DIV_Busy = '0' )then
|
DAA_Digit_3 <= Quotient(3 downto 0);
|
DAA_Digit_3 <= Quotient(3 downto 0);
|
DAA_Next <= Remainder;
|
DAA_Next <= Remainder;
|
Conv_State <= DAA_STEP8;
|
Conv_State <= DAA_STEP8;
|
end if;
|
end if;
|
|
|
when DAA_STEP8 =>
|
when DAA_STEP8 =>
|
Dividend <= DAA_Next;
|
Dividend <= DAA_Next;
|
Divisor <= DAA_ST8_DIV;
|
Divisor <= DAA_ST8_DIV;
|
Div_Enable <= '1';
|
Div_Enable <= '1';
|
if( DIV_Busy = '1' )then
|
if( DIV_Busy = '1' )then
|
Conv_State <= DAA_WAIT8;
|
Conv_State <= DAA_WAIT8;
|
end if;
|
end if;
|
|
|
when DAA_WAIT8 =>
|
when DAA_WAIT8 =>
|
if( DIV_Busy = '0' )then
|
if( DIV_Busy = '0' )then
|
DAA_Digit_2 <= Quotient(3 downto 0);
|
DAA_Digit_2 <= Quotient(3 downto 0);
|
DAA_Next <= Remainder;
|
DAA_Next <= Remainder;
|
Conv_State <= DAA_STEP9;
|
Conv_State <= DAA_STEP9;
|
end if;
|
end if;
|
|
|
when DAA_STEP9 =>
|
when DAA_STEP9 =>
|
Dividend <= DAA_Next;
|
Dividend <= DAA_Next;
|
Divisor <= DAA_ST9_DIV;
|
Divisor <= DAA_ST9_DIV;
|
Div_Enable <= '1';
|
Div_Enable <= '1';
|
if( DIV_Busy = '1' )then
|
if( DIV_Busy = '1' )then
|
Conv_State <= DAA_WAIT9;
|
Conv_State <= DAA_WAIT9;
|
end if;
|
end if;
|
|
|
when DAA_WAIT9 =>
|
when DAA_WAIT9 =>
|
if( DIV_Busy = '0' )then
|
if( DIV_Busy = '0' )then
|
DAA_Digit_1 <= Quotient(3 downto 0);
|
DAA_Digit_1 <= Quotient(3 downto 0);
|
DAA_Digit_0 <= Remainder(3 downto 0);
|
DAA_Digit_0 <= Remainder(3 downto 0);
|
Conv_State <= DAA_DONE;
|
Conv_State <= DAA_DONE;
|
end if;
|
end if;
|
|
|
when DAA_DONE =>
|
when DAA_DONE =>
|
DAA_Valid <= '1';
|
DAA_Valid <= '1';
|
CNV_Done <= '1';
|
CNV_Done <= '1';
|
Conv_State <= IDLE;
|
Conv_State <= IDLE;
|
|
|
when others => null;
|
when others => null;
|
end case;
|
end case;
|
|
|
Product_AB <= OperandA * OperandB;
|
Product_AB <= OperandA * OperandB;
|
Accumulator <= OperandABC + OperandD;
|
Accumulator <= OperandABC + OperandD;
|
|
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
-- Mult_proc: process( Clock)
|
-- Mult_proc: process( Clock)
|
-- begin
|
-- begin
|
-- if( rising_edge(Clock) )then
|
-- if( rising_edge(Clock) )then
|
-- Product_AB <= OperandA * OperandB;
|
-- Product_AB <= OperandA * OperandB;
|
-- end if;
|
-- end if;
|
-- end process;
|
-- end process;
|
|
|
U_DIV : entity work.intdiv
|
U_DIV : entity work.intdiv
|
generic map(
|
generic map(
|
Div_Width => DIVIDER_WIDTH,
|
Div_Width => DIVIDER_WIDTH,
|
Reset_Level => Reset_Level
|
Reset_Level => Reset_Level
|
)
|
)
|
port map(
|
port map(
|
Clock => Clock,
|
Clock => Clock,
|
Reset => Reset,
|
Reset => Reset,
|
--
|
--
|
Enable => Div_Enable,
|
Enable => Div_Enable,
|
Busy => Div_Busy,
|
Busy => Div_Busy,
|
--
|
--
|
Dividend => Dividend,
|
Dividend => Dividend,
|
Divisor => Divisor,
|
Divisor => Divisor,
|
Quotient => Quotient,
|
Quotient => Quotient,
|
Remainder => Remainder
|
Remainder => Remainder
|
);
|
);
|
|
|
|
|