-- Copyright (c)2020 Jeremy Seth Henry
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-- Copyright (c)2020 Jeremy Seth Henry
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-- All rights reserved.
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-- All rights reserved.
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--
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--
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-- Redistribution and use in source and binary forms, with or without
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-- Redistribution and use in source and binary forms, with or without
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-- modification, are permitted provided that the following conditions are met:
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-- modification, are permitted provided that the following conditions are met:
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-- * Redistributions of source code must retain the above copyright
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-- * Redistributions of source code must retain the above copyright
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-- notice, this list of conditions and the following disclaimer.
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-- notice, this list of conditions and the following disclaimer.
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-- * Redistributions in binary form must reproduce the above copyright
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-- * Redistributions in binary form must reproduce the above copyright
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-- notice, this list of conditions and the following disclaimer in the
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-- notice, this list of conditions and the following disclaimer in the
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-- documentation and/or other materials provided with the distribution,
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-- documentation and/or other materials provided with the distribution,
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-- where applicable (as part of a user interface, debugging port, etc.)
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-- where applicable (as part of a user interface, debugging port, etc.)
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--
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--
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-- THIS SOFTWARE IS PROVIDED BY JEREMY SETH HENRY ``AS IS'' AND ANY
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-- THIS SOFTWARE IS PROVIDED BY JEREMY SETH HENRY ``AS IS'' AND ANY
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-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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-- DISCLAIMED. IN NO EVENT SHALL JEREMY SETH HENRY BE LIABLE FOR ANY
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-- DISCLAIMED. IN NO EVENT SHALL JEREMY SETH HENRY BE LIABLE FOR ANY
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-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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-- THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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-- THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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--
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--
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-- VHDL Units : o8_sdlc_if
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-- VHDL Units : o8_sdlc_if
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-- Description: Provides a full memory-mapped SDLC stack with automatic CRC16
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-- Description: Provides a full memory-mapped SDLC stack with automatic CRC16
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-- Checksum insertion and integrity checking.
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-- Checksum insertion and integrity checking.
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--
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--
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-- Transmit Memory Map
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-- Transmit Memory Map
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-- "0_0000_0000" (0x000) TX Buffer START
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-- "0_0000_0000" (0x000) TX Buffer START
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-- "0_1111_1101" (0x0FD) TX Buffer END
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-- "0_1111_1101" (0x0FD) TX Buffer END
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-- "0_1111_1110" (0x0FE) Clock Status*
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-- "0_1111_1110" (0x0FE) Clock Status*
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-- "0_1111_1111" (0x0FF) TX Length / Status**
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-- "0_1111_1111" (0x0FF) TX Length / Status**
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--
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--
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-- Receive Memory Map
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-- Receive Memory Map
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-- "1_0000_0000" (0x100) RX Buffer START
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-- "1_0000_0000" (0x100) RX Buffer START
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-- "1_1111_1110" (0x1FE) RX Buffer END
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-- "1_1111_1101" (0x1FD) RX Buffer END
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-- "1_1111_1111" (0x1FF) RX Length / Status
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-- "1_1111_1110" (0x0FE) Reserved
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-- "1_1111_1111" (0x1FF) RX Length / Status***
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--
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-- * Address 0xFE reports the SDLC bit clock status and updates on changes.
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-- 1) If BClk_Okay = '0' (Bitclock is NOT present), the field will report
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-- 0x00. Otherwise, it will report 0xFF if the bitclock is present.
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-- 2) Writing any value to the register will cause the controller to
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-- silently reset the clock status without causing an interrupt.
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--
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--
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-- * Address 0xFE reports the SDLC bit clock status and updates on changes. If
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-- ** This location serves as the control/status register for transmit
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-- the bit clock goes away (BClk_Okay = '0'), the field will report 0x00.
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-- 1) Writing a value between 1 and 253 will trigger the transmit engine,
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-- otherwise it will report 0xFF. Note that the CPU can overwrite this
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-- location, at which point the status will be invalid.
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--
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-- ** This location serves as the control/status register for the interface
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-- 1) Writing 0x00 will reset the clock status flag in 0xFE without
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-- triggering an interrupt.
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-- 2) Writing a value between 1 and 253 will trigger the transmit engine,
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-- using the write value as the packet length.
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-- using the write value as the packet length.
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-- 3) Writing 0xFE or 0xFF will be ignored by the engine.
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-- 2) Values 0x00, 0xFE, or 0xFF are invalid, and will be ignored.
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-- 4) This value will change from the user written value to 0xFF once the
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-- 3) This value will change from the user written value to 0xFF once the
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-- packet is transmitted.
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-- packet is transmitted to indicate the transmission is complete.
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--
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--
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-- *** This location serves as the status register for the receive
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-- 1) This value is only updated on reception of a full frame, indicated
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-- by a start followed by a stop flag. Incomplete frames are ignored.
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-- 2) If the packet CRC matches the transmitted CRC, the packet is
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-- considered valid, and the received length (less CRC) is written.
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-- 3) If the packet CRC doesn't match, a value of ERR_CHECKSUM is written.
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-- 4) If too many bytes are received (buffer overflow), a value of
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-- ERR_LENGTH is written.
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_arith.all;
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library work;
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library work;
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use work.open8_pkg.all;
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use work.open8_pkg.all;
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library work;
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library work;
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use work.sdlc_serial_pkg.all;
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use work.sdlc_serial_pkg.all;
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entity o8_sdlc_if is
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entity o8_sdlc_if is
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generic(
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generic(
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Monitor_Enable : boolean := true;
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Attach_Monitor_to_CPU_Side : boolean := false;
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Poly_Init : std_logic_vector(15 downto 0) := x"0000";
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Poly_Init : std_logic_vector(15 downto 0) := x"0000";
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Set_As_Master : boolean := true;
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Set_As_Master : boolean := true;
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Clock_Offset : integer := 6;
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Clock_Offset : integer := 6;
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BitClock_Freq : real := 500000.0;
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BitClock_Freq : real := 500000.0;
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Sys_Freq : real := 100000000.0;
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Sys_Freq : real := 100000000.0;
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Reset_Level : std_logic := '1';
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Reset_Level : std_logic := '1';
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Address : ADDRESS_TYPE
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Address : ADDRESS_TYPE
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);
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);
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port(
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port(
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Clock : in std_logic;
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Clock : in std_logic;
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Reset : in std_logic;
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Reset : in std_logic;
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--
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--
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Bus_Address : in ADDRESS_TYPE;
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Bus_Address : in ADDRESS_TYPE;
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Wr_Enable : in std_logic;
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Wr_Enable : in std_logic;
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Wr_Data : in DATA_TYPE;
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Wr_Data : in DATA_TYPE;
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Rd_Enable : in std_logic;
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Rd_Enable : in std_logic;
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Rd_Data : out DATA_TYPE;
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Rd_Data : out DATA_TYPE;
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Interrupt : out std_logic;
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Interrupt : out std_logic;
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-- Serial IO
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-- Serial IO
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SDLC_In : in std_logic;
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SDLC_In : in std_logic;
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SDLC_SClk : in std_logic;
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SDLC_SClk : in std_logic;
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SDLC_MClk : out std_logic;
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SDLC_MClk : out std_logic;
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SDLC_Out : out std_logic
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SDLC_Out : out std_logic
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);
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);
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end entity;
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end entity;
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architecture behave of o8_sdlc_if is
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architecture behave of o8_sdlc_if is
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-- Connect the CPU to the dual-port memory
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-- Connect the CPU to the dual-port memory
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constant Base_Addr : std_logic_vector(15 downto 9)
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constant Base_Addr : std_logic_vector(15 downto 9)
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:= Address(15 downto 9);
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:= Address(15 downto 9);
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alias RAM_Upper_Addr is Bus_Address(15 downto 9);
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alias RAM_Upper_Addr is Bus_Address(15 downto 9);
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alias RAM_Lower_Addr is Bus_Address(8 downto 0);
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alias RAM_Lower_Addr is Bus_Address(8 downto 0);
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signal RAM_Addr_Match : std_logic := '0';
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signal RAM_Addr_Match : std_logic := '0';
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signal RAM_Wr_En : std_logic := '0';
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signal RAM_Wr_En : std_logic := '0';
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signal RAM_Rd_En : std_logic := '0';
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signal RAM_Rd_En : std_logic := '0';
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signal Rd_Data_i : DATA_TYPE := OPEN8_NULLBUS;
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signal Rd_Data_i : DATA_TYPE := OPEN8_NULLBUS;
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constant Reg_Sub_Addr : std_logic_vector(8 downto 0) :=
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constant Reg_Sub_Addr : std_logic_vector(8 downto 1) := x"7F";
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conv_std_logic_vector(255,9);
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alias Reg_Upper_Addr is Bus_Address(8 downto 1);
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alias Reg_Lower_Addr is Bus_Address(0);
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signal Reg_Addr : std_logic_vector(8 downto 0) := (others => '0');
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signal Reg_Addr : std_logic_vector(8 downto 1) := (others => '0');
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signal Reg_Sel : std_logic := '0';
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signal Reg_Wr_En : std_logic := '0';
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signal Reg_Wr_En : std_logic := '0';
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signal Reg_Updated : std_logic := '0';
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signal Reg_Clk_Sel : std_logic := '0';
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signal Reg_TxS_Sel : std_logic := '0';
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-- Connect the serial engine to the dual-port memory
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-- Connect the serial engine to the dual-port memory
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signal DP_Addr : std_logic_vector(8 downto 0) := (others => '0');
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signal DP_Addr : std_logic_vector(8 downto 0) := (others => '0');
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signal DP_Wr_Data : DATA_IN_TYPE := x"00";
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signal DP_Wr_Data : DATA_IN_TYPE := x"00";
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signal DP_Wr_En : std_logic := '0';
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signal DP_Wr_En : std_logic := '0';
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signal DP_Rd_Data : DATA_IN_TYPE := x"00";
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signal DP_Rd_Data : DATA_IN_TYPE := x"00";
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signal BClk_RE : std_logic := '0';
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signal BClk_RE : std_logic := '0';
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signal BClk_FE : std_logic := '0';
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signal BClk_FE : std_logic := '0';
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signal TX_Wr_En : std_logic := '0';
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signal TX_Wr_En : std_logic := '0';
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signal TX_Wr_Flag : std_logic := '0';
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signal TX_Wr_Flag : std_logic := '0';
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signal TX_Wr_Data : DATA_IN_TYPE := x"00";
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signal TX_Wr_Data : DATA_IN_TYPE := x"00";
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signal TX_Req_Next : std_logic := '0';
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signal TX_Req_Next : std_logic := '0';
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signal TX_CRC_Clr : std_logic := '0';
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signal TX_CRC_Clr : std_logic := '0';
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signal TX_CRC_En : std_logic := '0';
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signal TX_CRC_En : std_logic := '0';
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signal TX_CRC_Data : CRC_OUT_TYPE := x"0000";
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signal TX_CRC_Data : CRC_OUT_TYPE := x"0000";
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alias TX_CRC_Data_LB is TX_CRC_Data(7 downto 0);
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alias TX_CRC_Data_LB is TX_CRC_Data(7 downto 0);
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alias TX_CRC_Data_UB is TX_CRC_Data(15 downto 8);
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alias TX_CRC_Data_UB is TX_CRC_Data(15 downto 8);
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signal TX_CRC_Valid : std_logic := '0';
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signal TX_CRC_Valid : std_logic := '0';
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signal RX_Valid : std_logic := '0';
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signal RX_Valid : std_logic := '0';
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signal RX_Flag : std_logic := '0';
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signal RX_Flag : std_logic := '0';
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signal RX_Data : DATA_IN_TYPE := x"00";
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signal RX_Data : DATA_IN_TYPE := x"00";
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signal RX_Idle : std_logic := '0';
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signal RX_Idle : std_logic := '0';
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signal RX_CRC_Clr : std_logic := '0';
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signal RX_CRC_Clr : std_logic := '0';
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signal RX_CRC_En : std_logic := '0';
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signal RX_CRC_En : std_logic := '0';
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signal RX_CRC_Data : CRC_OUT_TYPE := x"0000";
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signal RX_CRC_Data : CRC_OUT_TYPE := x"0000";
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signal RX_CRC_Valid : std_logic := '0';
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signal RX_CRC_Valid : std_logic := '0';
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signal BClk_Okay : std_logic := '0';
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signal BClk_Okay : std_logic := '0';
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begin
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begin
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-- This decode needs to happen immediately, to give the RAM a chance to
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-- This decode needs to happen immediately, to give the RAM a chance to
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-- do the lookup before we have to set Rd_Data
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-- do the lookup before we have to set Rd_Data
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RAM_Addr_Match <= '1' when Base_Addr = RAM_Upper_Addr else '0';
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RAM_Addr_Match <= '1' when Base_Addr = RAM_Upper_Addr else '0';
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RAM_Wr_En <= RAM_Addr_Match and Wr_Enable;
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RAM_Wr_En <= RAM_Addr_Match and Wr_Enable;
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CPU_RAM_proc: process( Reset, Clock )
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CPU_RAM_proc: process( Reset, Clock )
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begin
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begin
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if( Reset = Reset_Level )then
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if( Reset = Reset_Level )then
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Reg_Addr <= (others => '0');
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Reg_Addr <= (others => '0');
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Reg_Wr_En <= '0';
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Reg_Wr_En <= '0';
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Reg_Updated <= '0';
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Reg_Clk_Sel <= '0';
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Reg_TxS_Sel <= '0';
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RAM_Rd_En <= '0';
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RAM_Rd_En <= '0';
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Rd_Data <= OPEN8_NULLBUS;
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Rd_Data <= OPEN8_NULLBUS;
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elsif( rising_edge(Clock) )then
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elsif( rising_edge(Clock) )then
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Reg_Addr <= RAM_Lower_Addr;
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Reg_Addr <= Reg_Upper_Addr;
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Reg_Sel <= Reg_Lower_Addr;
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Reg_Wr_En <= RAM_Addr_Match and Wr_Enable;
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Reg_Wr_En <= RAM_Addr_Match and Wr_Enable;
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Reg_Updated <= '0';
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Reg_Clk_Sel <= '0';
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Reg_TxS_Sel <= '0';
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if( Reg_Addr = Reg_Sub_Addr )then
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if( Reg_Addr = Reg_Sub_Addr )then
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Reg_Updated <= Reg_Wr_En;
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Reg_Clk_Sel <= Reg_Wr_En and not Reg_Sel;
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Reg_TxS_Sel <= Reg_Wr_En and Reg_Sel;
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end if;
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end if;
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RAM_Rd_En <= RAM_Addr_Match and Rd_Enable;
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RAM_Rd_En <= RAM_Addr_Match and Rd_Enable;
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Rd_Data <= OPEN8_NULLBUS;
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Rd_Data <= OPEN8_NULLBUS;
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if( RAM_Rd_En = '1' )then
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if( RAM_Rd_En = '1' )then
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Rd_Data <= Rd_Data_i;
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Rd_Data <= Rd_Data_i;
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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U_RAM : entity work.ram_dp512b_core
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U_RAM : entity work.ram_dp512b_core
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port map(
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port map(
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clock => Clock,
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clock => Clock,
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address_a => RAM_Lower_Addr,
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address_a => RAM_Lower_Addr,
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address_b => DP_Addr,
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address_b => DP_Addr,
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data_a => Wr_Data,
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data_a => Wr_Data,
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data_b => DP_Wr_Data,
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data_b => DP_Wr_Data,
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wren_a => RAM_Wr_En,
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wren_a => RAM_Wr_En,
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wren_b => DP_Wr_En,
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wren_b => DP_Wr_En,
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q_a => Rd_Data_i,
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q_a => Rd_Data_i,
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q_b => DP_Rd_Data
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q_b => DP_Rd_Data
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);
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);
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Attach_to_CPU_side: if( Monitor_Enable and Attach_Monitor_to_CPU_Side )generate
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U_MON: entity work.monitor
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port map(
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clock => Clock,
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address => RAM_Lower_Addr,
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data => Wr_Data,
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wren => RAM_Wr_En,
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q => open
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);
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end generate;
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Attach_to_Int_side: if( Monitor_Enable and not Attach_Monitor_to_CPU_Side )generate
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U_MON: entity work.monitor
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port map(
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clock => Clock,
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address => DP_Addr,
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data => DP_Wr_Data,
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wren => DP_Wr_En,
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q => open
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);
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end generate;
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U_BCLK : entity work.sdlc_serial_clk
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U_BCLK : entity work.sdlc_serial_clk
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generic map(
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generic map(
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Set_As_Master => Set_As_Master,
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Set_As_Master => Set_As_Master,
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BitClock_Freq => BitClock_Freq,
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BitClock_Freq => BitClock_Freq,
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Reset_Level => Reset_Level,
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Reset_Level => Reset_Level,
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Sys_Freq => Sys_Freq
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Sys_Freq => Sys_Freq
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)
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)
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port map(
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port map(
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Clock => Clock,
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Clock => Clock,
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Reset => Reset,
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Reset => Reset,
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--
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--
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BClk_In => SDLC_SClk,
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BClk_In => SDLC_SClk,
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BClk_Out => SDLC_MClk,
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BClk_Out => SDLC_MClk,
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BClk_FE => BClk_FE,
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BClk_FE => BClk_FE,
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BClk_RE => BClk_RE,
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BClk_RE => BClk_RE,
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BClk_Okay => BClk_Okay
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BClk_Okay => BClk_Okay
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);
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);
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U_CTRL : entity work.sdlc_serial_ctrl
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U_CTRL : entity work.sdlc_serial_ctrl
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generic map(
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generic map(
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Reset_Level => Reset_Level
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Reset_Level => Reset_Level
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)
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)
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port map(
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port map(
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Clock => Clock,
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Clock => Clock,
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Reset => Reset,
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Reset => Reset,
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--
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--
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BClk_Okay => BClk_Okay,
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BClk_Okay => BClk_Okay,
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--
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--
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Reg_Updated => Reg_Updated,
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Reg_Clk_Sel => Reg_Clk_Sel,
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Reg_TxS_Sel => Reg_TxS_Sel,
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--
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--
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DP_Addr => DP_Addr,
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DP_Addr => DP_Addr,
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DP_Wr_Data => DP_Wr_Data,
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DP_Wr_Data => DP_Wr_Data,
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DP_Wr_En => DP_Wr_En,
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DP_Wr_En => DP_Wr_En,
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DP_Rd_Data => DP_Rd_Data,
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DP_Rd_Data => DP_Rd_Data,
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--
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--
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TX_Wr_En => TX_Wr_En,
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TX_Wr_En => TX_Wr_En,
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TX_Wr_Flag => TX_Wr_Flag,
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TX_Wr_Flag => TX_Wr_Flag,
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TX_Wr_Data => TX_Wr_Data,
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TX_Wr_Data => TX_Wr_Data,
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TX_Req_Next => TX_Req_Next,
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TX_Req_Next => TX_Req_Next,
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--
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--
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TX_CRC_Clr => TX_CRC_Clr,
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TX_CRC_Clr => TX_CRC_Clr,
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TX_CRC_En => TX_CRC_En,
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TX_CRC_En => TX_CRC_En,
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TX_CRC_Data => TX_CRC_Data,
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TX_CRC_Data => TX_CRC_Data,
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TX_CRC_Valid => TX_CRC_Valid,
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TX_CRC_Valid => TX_CRC_Valid,
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--
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--
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RX_Valid => RX_Valid,
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RX_Valid => RX_Valid,
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RX_Flag => RX_Flag,
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RX_Flag => RX_Flag,
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RX_Data => RX_Data,
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RX_Data => RX_Data,
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RX_Idle => RX_Idle,
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RX_Idle => RX_Idle,
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--
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--
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RX_CRC_Clr => RX_CRC_Clr,
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RX_CRC_Clr => RX_CRC_Clr,
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RX_CRC_En => RX_CRC_En,
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RX_CRC_En => RX_CRC_En,
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RX_CRC_Data => RX_CRC_Data,
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RX_CRC_Data => RX_CRC_Data,
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RX_CRC_Valid => RX_CRC_Valid,
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RX_CRC_Valid => RX_CRC_Valid,
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--
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--
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Interrupt => Interrupt
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Interrupt => Interrupt
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);
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);
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U_TX_SER : entity work.sdlc_serial_tx
|
U_TX_SER : entity work.sdlc_serial_tx
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generic map(
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generic map(
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Reset_Level => Reset_Level
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Reset_Level => Reset_Level
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)
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)
|
port map(
|
port map(
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Clock => Clock,
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Clock => Clock,
|
Reset => Reset,
|
Reset => Reset,
|
--
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--
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BClk_FE => BClk_FE,
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BClk_FE => BClk_FE,
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BClk_RE => BClk_RE,
|
BClk_RE => BClk_RE,
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BClk_Okay => BClk_Okay,
|
BClk_Okay => BClk_Okay,
|
--
|
--
|
TX_En => TX_Wr_En,
|
TX_En => TX_Wr_En,
|
TX_FSS_Flag => TX_Wr_Flag,
|
TX_FSS_Flag => TX_Wr_Flag,
|
TX_Data => TX_Wr_Data,
|
TX_Data => TX_Wr_Data,
|
TX_Req_Next => TX_Req_Next,
|
TX_Req_Next => TX_Req_Next,
|
--
|
--
|
Serial_Out => SDLC_Out
|
Serial_Out => SDLC_Out
|
);
|
);
|
|
|
U_TX_CRC : entity work.sdlc_crc16_ccitt
|
U_TX_CRC : entity work.sdlc_crc16_ccitt
|
generic map(
|
generic map(
|
Poly_Init => Poly_Init,
|
Poly_Init => Poly_Init,
|
Reset_Level => Reset_Level
|
Reset_Level => Reset_Level
|
)
|
)
|
port map(
|
port map(
|
Clock => Clock,
|
Clock => Clock,
|
Reset => Reset,
|
Reset => Reset,
|
--
|
--
|
Clear => TX_CRC_Clr,
|
Clear => TX_CRC_Clr,
|
Wr_Data => TX_Wr_Data,
|
Wr_Data => TX_Wr_Data,
|
Wr_En => TX_CRC_En,
|
Wr_En => TX_CRC_En,
|
--
|
--
|
CRC16_Out => TX_CRC_Data,
|
CRC16_Out => TX_CRC_Data,
|
CRC16_Valid => TX_CRC_Valid
|
CRC16_Valid => TX_CRC_Valid
|
);
|
);
|
|
|
U_RX_SER : entity work.sdlc_serial_rx
|
U_RX_SER : entity work.sdlc_serial_rx
|
generic map(
|
generic map(
|
Set_As_Master => Set_As_Master,
|
Set_As_Master => Set_As_Master,
|
Clock_Offset => Clock_Offset,
|
Clock_Offset => Clock_Offset,
|
Reset_Level => Reset_Level
|
Reset_Level => Reset_Level
|
)
|
)
|
port map(
|
port map(
|
Clock => Clock,
|
Clock => Clock,
|
Reset => Reset,
|
Reset => Reset,
|
--
|
--
|
BClk_RE => BClk_RE,
|
BClk_RE => BClk_RE,
|
BClk_Okay => BClk_Okay,
|
BClk_Okay => BClk_Okay,
|
--
|
--
|
Serial_In => SDLC_In,
|
Serial_In => SDLC_In,
|
--
|
--
|
RX_Valid => RX_Valid,
|
RX_Valid => RX_Valid,
|
RX_Flag => RX_Flag,
|
RX_Flag => RX_Flag,
|
RX_Data => RX_Data,
|
RX_Data => RX_Data,
|
RX_Idle => RX_Idle
|
RX_Idle => RX_Idle
|
);
|
);
|
|
|
U_RX_CRC : entity work.sdlc_crc16_ccitt
|
U_RX_CRC : entity work.sdlc_crc16_ccitt
|
generic map(
|
generic map(
|
Poly_Init => Poly_Init,
|
Poly_Init => Poly_Init,
|
Reset_Level => Reset_Level
|
Reset_Level => Reset_Level
|
)
|
)
|
port map(
|
port map(
|
Clock => Clock,
|
Clock => Clock,
|
Reset => Reset,
|
Reset => Reset,
|
--
|
--
|
Clear => RX_CRC_Clr,
|
Clear => RX_CRC_Clr,
|
Wr_Data => RX_Data,
|
Wr_Data => RX_Data,
|
Wr_En => RX_CRC_En,
|
Wr_En => RX_CRC_En,
|
--
|
--
|
CRC16_Out => RX_CRC_Data,
|
CRC16_Out => RX_CRC_Data,
|
CRC16_Valid => RX_CRC_Valid
|
CRC16_Valid => RX_CRC_Valid
|
);
|
);
|
|
|
|
|
