-- Copyright (c)2006, 2016, 2019 Jeremy Seth Henry
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-- Copyright (c)2006, 2016, 2019 Jeremy Seth Henry
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-- All rights reserved.
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-- All rights reserved.
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--
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--
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-- Redistribution and use in source and binary forms, with or without
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-- Redistribution and use in source and binary forms, with or without
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-- modification, are permitted provided that the following conditions are met:
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-- modification, are permitted provided that the following conditions are met:
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-- * Redistributions of source code must retain the above copyright
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-- * Redistributions of source code must retain the above copyright
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-- notice, this list of conditions and the following disclaimer.
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-- notice, this list of conditions and the following disclaimer.
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-- * Redistributions in binary form must reproduce the above copyright
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-- * Redistributions in binary form must reproduce the above copyright
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-- notice, this list of conditions and the following disclaimer in the
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-- notice, this list of conditions and the following disclaimer in the
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-- documentation and/or other materials provided with the distribution,
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-- documentation and/or other materials provided with the distribution,
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-- where applicable (as part of a user interface, debugging port, etc.)
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-- where applicable (as part of a user interface, debugging port, etc.)
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--
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--
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-- THIS SOFTWARE IS PROVIDED BY JEREMY SETH HENRY ``AS IS'' AND ANY
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-- THIS SOFTWARE IS PROVIDED BY JEREMY SETH HENRY ``AS IS'' AND ANY
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-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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-- DISCLAIMED. IN NO EVENT SHALL JEREMY SETH HENRY BE LIABLE FOR ANY
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-- DISCLAIMED. IN NO EVENT SHALL JEREMY SETH HENRY BE LIABLE FOR ANY
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-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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--
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--
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-- VHDL Units : o8_status_led
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-- VHDL Units : o8_status_led
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-- Description: Provides a multi-state status LED controller
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-- Description: Provides a multi-state status LED controller
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--
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--
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-- Register Map:
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-- Register Map:
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-- Offset Bitfield Description Read/Write
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-- Offset Bitfield Description Read/Write
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-- 0x00 -----AAA LED Mode (2:0) (RW)
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-- 0x00 -----AAA LED Mode (2:0) (RW)
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--
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--
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-- LED Modes:
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-- LED Modes:
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-- 0x00 - LED is fully off
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-- 0x00 - LED is fully off
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-- 0x01 - LED is fully on
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-- 0x01 - LED is fully on
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-- 0x02 - LED is dimmed to 50%
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-- 0x02 - LED is dimmed to 50%
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-- 0x03 - LED Toggles at 1Hz
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-- 0x03 - LED Toggles at 1Hz
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-- 0x04 - LED fades in and out
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-- 0x04 - LED fades in and out
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--
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--
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-- Revision History
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-- Revision History
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-- Author Date Change
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-- Author Date Change
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------------------ -------- ---------------------------------------------------
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------------------ -------- ---------------------------------------------------
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-- Seth Henry 12/20/19 Design Start
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-- Seth Henry 12/20/19 Design Start
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_misc.all;
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use ieee.std_logic_misc.all;
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library work;
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library work;
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use work.open8_pkg.all;
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use work.open8_pkg.all;
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entity o8_status_led is
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entity o8_status_led is
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generic(
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generic(
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Reset_Level : std_logic;
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Reset_Level : std_logic;
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Address : ADDRESS_TYPE
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Address : ADDRESS_TYPE
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);
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);
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port(
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port(
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Clock : in std_logic;
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Clock : in std_logic;
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Reset : in std_logic;
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Reset : in std_logic;
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--
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--
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Bus_Address : in ADDRESS_TYPE;
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Bus_Address : in ADDRESS_TYPE;
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Wr_Enable : in std_logic;
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Wr_Enable : in std_logic;
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Wr_Data : in DATA_TYPE;
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Wr_Data : in DATA_TYPE;
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Rd_Enable : in std_logic;
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Rd_Enable : in std_logic;
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Rd_Data : out DATA_TYPE;
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Rd_Data : out DATA_TYPE;
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--
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--
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LED_Out : out std_logic
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LED_Out : out std_logic
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);
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);
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end entity;
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end entity;
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architecture behave of o8_status_led is
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architecture behave of o8_status_led is
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function ceil_log2 (x : in natural) return natural is
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variable retval : natural;
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begin
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retval := 1;
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while ((2**retval) - 1) < x loop
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retval := retval + 1;
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end loop;
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return retval;
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end function;
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constant User_Addr : std_logic_vector(15 downto 0)
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constant User_Addr : std_logic_vector(15 downto 0)
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:= Address(15 downto 0);
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:= Address(15 downto 0);
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alias Comp_Addr is Bus_Address(15 downto 0);
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alias Comp_Addr is Bus_Address(15 downto 0);
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signal Addr_Match : std_logic;
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signal Addr_Match : std_logic;
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signal Wr_En : std_logic;
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signal Wr_En : std_logic;
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signal Wr_Data_q : std_logic_vector(2 downto 0);
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signal Wr_Data_q : std_logic_vector(2 downto 0);
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signal LED_Mode : std_logic_vector(2 downto 0);
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signal LED_Mode : std_logic_vector(2 downto 0);
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signal Rd_En : std_logic;
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signal Rd_En : std_logic;
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signal Dim50Pct_Out : std_logic;
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signal Dim50Pct_Out : std_logic;
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signal Half_Hz_Timer : std_logic_vector(15 downto 0);
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signal Half_Hz_Timer : std_logic_vector(15 downto 0);
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constant HALF_HZ_PRD : std_logic_vector(15 downto 0) :=
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constant HALF_HZ_PRD : std_logic_vector(15 downto 0) :=
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conv_std_logic_vector(500000,16);
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conv_std_logic_vector(500000,16);
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signal One_Hz_Out : std_logic;
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signal One_Hz_Out : std_logic;
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constant TIMER_MSB : integer range 9 to 20 := 18;
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constant TIMER_MSB : integer range 9 to 20 := 18;
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signal Fade_Timer1 : std_logic_vector(TIMER_MSB downto 0);
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signal Fade_Timer1 : std_logic_vector(TIMER_MSB downto 0);
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signal Fade_Timer2 : std_logic_vector(TIMER_MSB downto 0);
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signal Fade_Timer2 : std_logic_vector(TIMER_MSB downto 0);
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signal Fade_Out : std_logic;
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signal Fade_Out : std_logic;
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begin
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begin
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Addr_Match <= '1' when Comp_Addr = User_Addr else '0';
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Addr_Match <= '1' when Comp_Addr = User_Addr else '0';
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io_reg: process( Clock, Reset )
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io_reg: process( Clock, Reset )
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begin
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begin
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if( Reset = Reset_Level )then
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if( Reset = Reset_Level )then
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Wr_En <= '0';
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Wr_En <= '0';
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Wr_Data_q <= (others => '0');
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Wr_Data_q <= (others => '0');
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LED_Mode <= (others => '0');
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LED_Mode <= (others => '0');
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Rd_En <= '0';
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Rd_En <= '0';
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Rd_Data <= x"00";
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Rd_Data <= x"00";
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elsif( rising_edge( Clock ) )then
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elsif( rising_edge( Clock ) )then
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Wr_En <= Addr_Match and Wr_Enable;
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Wr_En <= Addr_Match and Wr_Enable;
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Wr_Data_q <= Wr_Data(2 downto 0);
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Wr_Data_q <= Wr_Data(2 downto 0);
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if( Wr_En = '1' )then
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if( Wr_En = '1' )then
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LED_Mode <= Wr_Data_q;
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LED_Mode <= Wr_Data_q;
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end if;
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end if;
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Rd_Data <= (others => '0');
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Rd_Data <= (others => '0');
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Rd_En <= Addr_Match and Rd_Enable;
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Rd_En <= Addr_Match and Rd_Enable;
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if( Rd_En = '1' )then
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if( Rd_En = '1' )then
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Rd_Data <= "00000" & LED_Mode;
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Rd_Data <= "00000" & LED_Mode;
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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Output_FF: process( Clock, Reset )
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Output_FF: process( Clock, Reset )
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begin
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begin
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if( Reset = Reset_Level )then
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if( Reset = Reset_Level )then
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LED_Out <= '0';
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LED_Out <= '0';
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elsif( rising_edge(Clock) )then
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elsif( rising_edge(Clock) )then
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LED_Out <= '0';
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LED_Out <= '0';
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case( LED_Mode )is
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case( LED_Mode )is
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when "001" =>
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when "001" =>
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LED_Out <= '1';
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LED_Out <= '1';
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when "010" =>
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when "010" =>
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LED_Out <= Dim50Pct_Out;
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LED_Out <= Dim50Pct_Out;
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when "011" =>
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when "011" =>
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LED_Out <= One_Hz_Out;
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LED_Out <= One_Hz_Out;
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when "100" =>
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when "100" =>
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LED_Out <= Fade_out;
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LED_Out <= Fade_out;
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when others => null;
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when others => null;
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end case;
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end case;
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end if;
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end if;
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end process;
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end process;
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Timer_proc: process( Clock, Reset )
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Timer_proc: process( Clock, Reset )
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begin
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begin
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if( Reset = Reset_Level )then
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if( Reset = Reset_Level )then
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Dim50Pct_Out <= '0';
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Dim50Pct_Out <= '0';
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Half_Hz_Timer <= (others => '0');
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Half_Hz_Timer <= (others => '0');
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One_Hz_Out <= '0';
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One_Hz_Out <= '0';
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Fade_Timer1 <= (others => '0');
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Fade_Timer1 <= (others => '0');
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Fade_Timer2 <= (others => '0');
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Fade_Timer2 <= (others => '0');
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Fade_out <= '0';
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Fade_out <= '0';
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elsif( rising_edge(Clock) )then
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elsif( rising_edge(Clock) )then
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Dim50Pct_Out <= not Dim50Pct_Out;
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Dim50Pct_Out <= not Dim50Pct_Out;
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Half_Hz_Timer <= Half_Hz_Timer - 1;
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Half_Hz_Timer <= Half_Hz_Timer - 1;
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if( Half_Hz_Timer = 0 )then
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if( Half_Hz_Timer = 0 )then
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Half_Hz_Timer <= HALF_HZ_PRD;
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Half_Hz_Timer <= HALF_HZ_PRD;
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One_Hz_Out <= not One_Hz_Out;
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One_Hz_Out <= not One_Hz_Out;
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end if;
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end if;
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Fade_Timer1 <= Fade_Timer1 - 1;
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Fade_Timer1 <= Fade_Timer1 - 1;
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Fade_Timer2 <= Fade_Timer2 - 1;
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Fade_Timer2 <= Fade_Timer2 - 1;
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if( or_reduce(Fade_Timer2) = '0' )then
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if( or_reduce(Fade_Timer2) = '0' )then
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Fade_Timer2(TIMER_MSB downto TIMER_MSB - 8) <= (others => '1');
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Fade_Timer2(TIMER_MSB downto TIMER_MSB - 8) <= (others => '1');
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Fade_Timer2(TIMER_MSB - 9 downto 0 ) <= (others => '0');
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Fade_Timer2(TIMER_MSB - 9 downto 0 ) <= (others => '0');
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end if;
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end if;
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Fade_out <= Fade_Timer1(TIMER_MSB) xor Fade_Timer2(TIMER_MSB);
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Fade_out <= Fade_Timer1(TIMER_MSB) xor Fade_Timer2(TIMER_MSB);
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end if;
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end if;
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end process;
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end process;
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end architecture;
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end architecture;
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