-- Copyright (c)2020 Jeremy Seth Henry
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-- Copyright (c)2020 Jeremy Seth Henry
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-- All rights reserved.
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-- All rights reserved.
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--
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--
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-- Redistribution and use in source and binary forms, with or without
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-- Redistribution and use in source and binary forms, with or without
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-- modification, are permitted provided that the following conditions are met:
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-- modification, are permitted provided that the following conditions are met:
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-- * Redistributions of source code must retain the above copyright
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-- * Redistributions of source code must retain the above copyright
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-- notice, this list of conditions and the following disclaimer.
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-- notice, this list of conditions and the following disclaimer.
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-- * Redistributions in binary form must reproduce the above copyright
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-- * Redistributions in binary form must reproduce the above copyright
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-- notice, this list of conditions and the following disclaimer in the
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-- notice, this list of conditions and the following disclaimer in the
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-- documentation and/or other materials provided with the distribution,
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-- documentation and/or other materials provided with the distribution,
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-- where applicable (as part of a user interface, debugging port, etc.)
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-- where applicable (as part of a user interface, debugging port, etc.)
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--
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--
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-- THIS SOFTWARE IS PROVIDED BY JEREMY SETH HENRY ``AS IS'' AND ANY
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-- THIS SOFTWARE IS PROVIDED BY JEREMY SETH HENRY ``AS IS'' AND ANY
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-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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-- DISCLAIMED. IN NO EVENT SHALL JEREMY SETH HENRY BE LIABLE FOR ANY
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-- DISCLAIMED. IN NO EVENT SHALL JEREMY SETH HENRY BE LIABLE FOR ANY
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-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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--
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--
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-- VHDL Entity: o8_trig_delay
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-- VHDL Entity: o8_trig_delay
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-- Description: Programmable delay timer with time-base selection. Allows both
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-- Description: Programmable delay timer with time-base selection. Allows both
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-- they delay after triggering and pulse width to be set by
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-- they delay after triggering and pulse width to be set by
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-- software. Output may either be routed to a pin or used to
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-- software. Output may either be routed to a pin or used to
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-- trigger an interrupt.
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-- trigger an interrupt.
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--
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--
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-- Register Map:
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-- Register Map:
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-- Offset Bitfield Description Read/Write
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-- Offset Bitfield Description Read/Write
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-- 0x0 AAAAAAAA Delay Time Byte 0 (RW)
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-- 0x0 AAAAAAAA Delay Time Byte 0 (RW)
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-- 0x1 AAAAAAAA Delay Time Byte 1 (RW)
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-- 0x1 AAAAAAAA Delay Time Byte 1 (RW)
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-- 0x2 AAAAAAAA Delay Time Byte 2 (RW)
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-- 0x2 AAAAAAAA Delay Time Byte 2 (RW)
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-- 0x3 AAAAAAAA Pulse Width Byte 0 (RW)
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-- 0x3 AAAAAAAA Pulse Width Byte 0 (RW)
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-- 0x4 AAAAAAAA Pulse Width Byte 1 (RW)
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-- 0x4 AAAAAAAA Pulse Width Byte 1 (RW)
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-- 0x5 AAAAAAAA Pulse Width Byte 2 (RW)
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-- 0x5 AAAAAAAA Pulse Width Byte 2 (RW)
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-- 0x6 EDCBAA-- Time Configuration (RW*)
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-- 0x6 EDCBAA-- Timer Configuration (RW*)
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-- A: Interrupt Select
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-- A: Interrupt Select
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-- 00 - Disabled
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-- 00 - Disabled
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-- 01 - Interrupt on trigger event
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-- 01 - Interrupt on trigger event
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-- 10 - Interrupt on delay done
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-- 10 - Interrupt on delay done
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-- 11 - Interrupt on pulse done
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-- 11 - Interrupt on pulse done
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-- B: Trigger Edge
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-- B: Trigger Edge
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-- 0 - Trigger on falling edge
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-- 0 - Trigger on falling edge
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-- 1 - Trigger on rising edge
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-- 1 - Trigger on rising edge
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-- C: Automatic Re-Arm (enabled if 1)
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-- C: Automatic Re-Arm (enabled if 1)
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-- D: Time base locked (okay if 1) (read-only)
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-- D: Time base locked (okay if 1) (read-only)
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-- E: Time base source
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-- E: Time base source
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-- 0 - Use the internal uSec_Tick pulse
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-- 0 - Use the internal uSec_Tick pulse
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-- 1 - Use an external clock source
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-- 1 - Use an external clock source
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-- 0x7 DCBA---- Timer Control (RW*)
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-- 0x7 DCBA---- Timer Control (RW*)
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-- A: Current output level (read-only)
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-- A: Current output level (read-only)
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-- B: Clear/Re-Arm on '1' (one-shot)
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-- B: Clear/Re-Arm on '1' (one-shot)
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-- Trigger event status on read
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-- Trigger event status on read
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-- C: Disable/Safe Trigger (one-shot)
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-- C: Disable/Safe Trigger (one-shot)
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-- Returns '0' on read
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-- Returns '0' on read
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-- D: Enable/Arm Trigger (one-shot)
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-- D: Enable/Arm Trigger (one-shot)
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-- Trigger armed status on read
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-- Trigger armed status on read
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--
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--
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-- Revision History
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-- Revision History
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-- Author Date Change
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-- Author Date Change
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------------------ -------- ---------------------------------------------------
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------------------ -------- ---------------------------------------------------
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-- Seth Henry 05/14/20 Design start
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-- Seth Henry 05/14/20 Design start
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-- Seth Henry 05/18/20 Added write qualification input
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-- Seth Henry 05/18/20 Added write qualification input
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_misc.all;
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use ieee.std_logic_misc.all;
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library work;
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library work;
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use work.open8_pkg.all;
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use work.open8_pkg.all;
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entity o8_trig_delay is
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entity o8_trig_delay is
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generic(
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generic(
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Default_Delay : std_logic_vector(23 downto 0) := x"000000";
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Default_Delay : std_logic_vector(23 downto 0) := x"000000";
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Default_Width : std_logic_vector(23 downto 0) := x"000000";
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Default_Width : std_logic_vector(23 downto 0) := x"000000";
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Default_Timebase : std_logic := '0';
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Default_Timebase : std_logic := '0';
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Default_Auto_ReArm : std_logic := '0';
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Default_Auto_ReArm : std_logic := '0';
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Default_Trigger_Edge : std_logic := '1';
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Default_Trigger_Edge : std_logic := '1';
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Default_Int_Source : std_logic_vector(1 downto 0) := "00";
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Default_Int_Source : std_logic_vector(1 downto 0) := "00";
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Address : ADDRESS_TYPE
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Address : ADDRESS_TYPE
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);
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);
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port(
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port(
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Open8_Bus : in OPEN8_BUS_TYPE;
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Open8_Bus : in OPEN8_BUS_TYPE;
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Write_Qual : in std_logic := '1';
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Write_Qual : in std_logic := '1';
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Rd_Data : out DATA_TYPE;
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Rd_Data : out DATA_TYPE;
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Interrupt : out std_logic;
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Interrupt : out std_logic;
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--
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--
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Time_Base_Clock : in std_logic := '0';
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Time_Base_Clock : in std_logic := '0';
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Time_Base_Locked : in std_logic := '1';
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Time_Base_Locked : in std_logic := '1';
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--
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--
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Ext_Trig : in std_logic;
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Ext_Trig : in std_logic;
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Timer_Out : out std_logic
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Timer_Out : out std_logic
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);
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);
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end entity;
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end entity;
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architecture behave of o8_trig_delay is
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architecture behave of o8_trig_delay is
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alias Clock is Open8_Bus.Clock;
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alias Clock is Open8_Bus.Clock;
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alias Reset is Open8_Bus.Reset;
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alias Reset is Open8_Bus.Reset;
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alias uSec_Tick is Open8_Bus.uSec_Tick;
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alias uSec_Tick is Open8_Bus.uSec_Tick;
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alias Wr_Data_d is Open8_Bus.Wr_Data;
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alias Wr_Data_d is Open8_Bus.Wr_Data;
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constant User_Addr : std_logic_vector(15 downto 3) :=
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constant User_Addr : std_logic_vector(15 downto 3) :=
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Address(15 downto 3);
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Address(15 downto 3);
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alias Comp_Addr is Open8_Bus.Address(15 downto 3);
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alias Comp_Addr is Open8_Bus.Address(15 downto 3);
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alias Reg_Sel_d is Open8_Bus.Address(2 downto 0);
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alias Reg_Sel_d is Open8_Bus.Address(2 downto 0);
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signal Addr_Match : std_logic := '0';
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signal Addr_Match : std_logic := '0';
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signal Reg_Sel_q : std_logic_vector(2 downto 0) := "000";
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signal Reg_Sel_q : std_logic_vector(2 downto 0) := "000";
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signal Wr_En_d : std_logic := '0';
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signal Wr_En_d : std_logic := '0';
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signal Wr_En_q : std_logic := '0';
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signal Wr_En_q : std_logic := '0';
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signal Wr_Data_q : DATA_TYPE := x"00";
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signal Wr_Data_q : DATA_TYPE := x"00";
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signal Rd_En_d : std_logic := '0';
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signal Rd_En_d : std_logic := '0';
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signal Rd_En_q : std_logic := '0';
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signal Rd_En_q : std_logic := '0';
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-- Configuration Registers
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-- Configuration Registers
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signal Pulse_Delay : std_logic_vector(23 downto 0) := x"000000";
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signal Pulse_Delay : std_logic_vector(23 downto 0) := x"000000";
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alias Pulse_Delay_B0 is Pulse_Delay( 7 downto 0);
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alias Pulse_Delay_B0 is Pulse_Delay( 7 downto 0);
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alias Pulse_Delay_B1 is Pulse_Delay(15 downto 8);
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alias Pulse_Delay_B1 is Pulse_Delay(15 downto 8);
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alias Pulse_Delay_B2 is Pulse_Delay(23 downto 16);
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alias Pulse_Delay_B2 is Pulse_Delay(23 downto 16);
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signal Pulse_Width : std_logic_vector(23 downto 0) := x"000000";
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signal Pulse_Width : std_logic_vector(23 downto 0) := x"000000";
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alias Pulse_Width_B0 is Pulse_Width( 7 downto 0);
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alias Pulse_Width_B0 is Pulse_Width( 7 downto 0);
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alias Pulse_Width_B1 is Pulse_Width(15 downto 8);
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alias Pulse_Width_B1 is Pulse_Width(15 downto 8);
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alias Pulse_Width_B2 is Pulse_Width(23 downto 16);
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alias Pulse_Width_B2 is Pulse_Width(23 downto 16);
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signal Time_Base_Source : std_logic := '0';
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signal Time_Base_Source : std_logic := '0';
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signal Time_Base_Status : std_logic := '0';
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signal Time_Base_Status : std_logic := '0';
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signal Auto_ReArm : std_logic := '0';
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signal Auto_ReArm : std_logic := '0';
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signal Trigger_Edge : std_logic := '0';
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signal Trigger_Edge : std_logic := '0';
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signal Interrupt_Select : std_logic_vector(1 downto 0);
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signal Interrupt_Select : std_logic_vector(1 downto 0);
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signal Arm_Timer : std_logic := '0';
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signal Arm_Timer : std_logic := '0';
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signal Safe_Timer : std_logic := '0';
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signal Safe_Timer : std_logic := '0';
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signal Clear_Trigd : std_logic := '0';
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signal Clear_Trigd : std_logic := '0';
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-- Time Base signals
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-- Time Base signals
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signal Ext_TBC_SR : std_logic_vector(3 downto 0) := "0000";
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signal Ext_TBC_SR : std_logic_vector(3 downto 0) := "0000";
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signal Ext_TBL_SR : std_logic_vector(3 downto 0) := "0000";
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signal Ext_TBL_SR : std_logic_vector(3 downto 0) := "0000";
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signal Timer_Tick : std_logic := '0';
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signal Timer_Tick : std_logic := '0';
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-- Trigger signals
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-- Trigger signals
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signal Ext_Trig_SR : std_logic_vector(3 downto 0) := "0000";
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signal Ext_Trig_SR : std_logic_vector(3 downto 0) := "0000";
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signal Trig_RE : std_logic := '0';
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signal Trig_RE : std_logic := '0';
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signal Trig_FE : std_logic := '0';
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signal Trig_FE : std_logic := '0';
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signal Delay_Trig : std_logic := '0';
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signal Delay_Trig : std_logic := '0';
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signal Trigger_Armed : std_logic := '0';
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signal Trigger_Armed : std_logic := '0';
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signal Trigger_Event : std_logic := '0';
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signal Trigger_Event : std_logic := '0';
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-- Delay Timer signals
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-- Delay Timer signals
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signal Delay_Pending : std_logic := '0';
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signal Delay_Pending : std_logic := '0';
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signal Delay_Tmr : std_logic_vector(23 downto 0) := x"000000";
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signal Delay_Tmr : std_logic_vector(23 downto 0) := x"000000";
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signal Delay_Tmr_SR : std_logic_vector(1 downto 0);
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signal Delay_Tmr_SR : std_logic_vector(1 downto 0);
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signal Width_Trig : std_logic := '0';
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signal Width_Trig : std_logic := '0';
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-- Pulse Timer signals
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-- Pulse Timer signals
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signal Width_Tmr : std_logic_vector(23 downto 0) := x"000000";
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signal Width_Tmr : std_logic_vector(23 downto 0) := x"000000";
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signal Width_Tmr_SR : std_logic_vector(1 downto 0);
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signal Width_Tmr_SR : std_logic_vector(1 downto 0);
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signal Pulse_Out : std_logic := '0';
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signal Pulse_Out : std_logic := '0';
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signal Pulse_Done : std_logic := '0';
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signal Pulse_Done : std_logic := '0';
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begin
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begin
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Timer_Out <= Pulse_Out;
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Timer_Out <= Pulse_Out;
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Addr_Match <= '1' when Comp_Addr = User_Addr else '0';
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Addr_Match <= '1' when Comp_Addr = User_Addr else '0';
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Wr_En_d <= Addr_Match and Open8_Bus.Wr_En;
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Wr_En_d <= Addr_Match and Open8_Bus.Wr_En;
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Rd_En_d <= Addr_Match and Open8_Bus.Rd_En;
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Rd_En_d <= Addr_Match and Open8_Bus.Rd_En;
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io_reg: process( Clock, Reset )
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io_reg: process( Clock, Reset )
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begin
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begin
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if( Reset = Reset_Level )then
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if( Reset = Reset_Level )then
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Reg_Sel_q <= (others => '0');
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Reg_Sel_q <= (others => '0');
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Wr_En_q <= '0';
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Wr_En_q <= '0';
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Wr_Data_q <= (others => '0');
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Wr_Data_q <= (others => '0');
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Rd_En_q <= '0';
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Rd_En_q <= '0';
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Rd_Data <= OPEN8_NULLBUS;
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Rd_Data <= OPEN8_NULLBUS;
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Pulse_Delay <= Default_Delay;
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Pulse_Delay <= Default_Delay;
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Pulse_Width <= Default_Width;
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Pulse_Width <= Default_Width;
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Time_Base_Source <= Default_Timebase;
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Time_Base_Source <= Default_Timebase;
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Auto_ReArm <= Default_Auto_ReArm;
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Auto_ReArm <= Default_Auto_ReArm;
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Trigger_Edge <= Default_Trigger_Edge;
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Trigger_Edge <= Default_Trigger_Edge;
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Interrupt_Select <= Default_Int_Source;
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Interrupt_Select <= Default_Int_Source;
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Arm_Timer <= '0';
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Arm_Timer <= '0';
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Safe_Timer <= '0';
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Safe_Timer <= '0';
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Clear_Trigd <= '0';
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Clear_Trigd <= '0';
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Interrupt <= '0';
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Interrupt <= '0';
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elsif( rising_edge( Clock ) )then
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elsif( rising_edge( Clock ) )then
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Reg_Sel_q <= Reg_Sel_d;
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Reg_Sel_q <= Reg_Sel_d;
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Wr_En_q <= Wr_En_d;
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Wr_En_q <= Wr_En_d;
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Wr_Data_q <= Wr_Data_d;
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Wr_Data_q <= Wr_Data_d;
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Arm_Timer <= '0';
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Arm_Timer <= '0';
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Safe_Timer <= '0';
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Safe_Timer <= '0';
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Clear_Trigd <= '0';
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Clear_Trigd <= '0';
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if( Wr_En_q = '1' and Write_Qual = '1' )then
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if( Wr_En_q = '1' and Write_Qual = '1' )then
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case( Reg_Sel_q )is
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case( Reg_Sel_q )is
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when "000" =>
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when "000" =>
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Pulse_Delay_B0 <= Wr_Data_q;
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Pulse_Delay_B0 <= Wr_Data_q;
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when "001" =>
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when "001" =>
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Pulse_Delay_B1 <= Wr_Data_q;
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Pulse_Delay_B1 <= Wr_Data_q;
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when "010" =>
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when "010" =>
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Pulse_Delay_B2 <= Wr_Data_q;
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Pulse_Delay_B2 <= Wr_Data_q;
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when "011" =>
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when "011" =>
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Pulse_Width_B0 <= Wr_Data_q;
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Pulse_Width_B0 <= Wr_Data_q;
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when "100" =>
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when "100" =>
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Pulse_Width_B1 <= Wr_Data_q;
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Pulse_Width_B1 <= Wr_Data_q;
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when "101" =>
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when "101" =>
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Pulse_Width_B2 <= Wr_Data_q;
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Pulse_Width_B2 <= Wr_Data_q;
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when "110" =>
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when "110" =>
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Time_Base_Source <= Wr_Data_q(7);
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Time_Base_Source <= Wr_Data_q(7);
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-- Reserved for status bit
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-- Reserved for status bit
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Auto_ReArm <= Wr_Data_q(5);
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Auto_ReArm <= Wr_Data_q(5);
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Trigger_Edge <= Wr_Data_q(4);
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Trigger_Edge <= Wr_Data_q(4);
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Interrupt_Select <= Wr_Data_q(3 downto 2);
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Interrupt_Select <= Wr_Data_q(3 downto 2);
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when "111" =>
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when "111" =>
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Arm_Timer <= Wr_Data_q(7);
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Arm_Timer <= Wr_Data_q(7);
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Safe_Timer <= Wr_Data_q(6);
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Safe_Timer <= Wr_Data_q(6);
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Clear_Trigd <= Wr_Data_q(5);
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Clear_Trigd <= Wr_Data_q(5);
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when others => null;
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when others => null;
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end case;
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end case;
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end if;
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end if;
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Rd_Data <= OPEN8_NULLBUS;
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Rd_Data <= OPEN8_NULLBUS;
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Rd_En_q <= Rd_En_d;
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Rd_En_q <= Rd_En_d;
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if( Rd_En_q = '1' )then
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if( Rd_En_q = '1' )then
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case( Reg_Sel_q )is
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case( Reg_Sel_q )is
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when "000" =>
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when "000" =>
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Rd_Data <= Pulse_Delay_B0;
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Rd_Data <= Pulse_Delay_B0;
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when "001" =>
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when "001" =>
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Rd_Data <= Pulse_Delay_B1;
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Rd_Data <= Pulse_Delay_B1;
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when "010" =>
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when "010" =>
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Rd_Data <= Pulse_Delay_B2;
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Rd_Data <= Pulse_Delay_B2;
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when "011" =>
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when "011" =>
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Rd_Data <= Pulse_Width_B0;
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Rd_Data <= Pulse_Width_B0;
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when "100" =>
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when "100" =>
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Rd_Data <= Pulse_Width_B1;
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Rd_Data <= Pulse_Width_B1;
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when "101" =>
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when "101" =>
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Rd_Data <= Pulse_Width_B2;
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Rd_Data <= Pulse_Width_B2;
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when "110" =>
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when "110" =>
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Rd_Data <= Time_Base_Source & -- Bit 7
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Rd_Data <= Time_Base_Source & -- Bit 7
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Time_Base_Status & -- Bit 6
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Time_Base_Status & -- Bit 6
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Auto_ReArm & -- Bit 5
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Auto_ReArm & -- Bit 5
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Trigger_Edge & -- Bit 4
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Trigger_Edge & -- Bit 4
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Interrupt_Select & -- Bits 3:2
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Interrupt_Select & -- Bits 3:2
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"00"; -- Bits 1:0
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"00"; -- Bits 1:0
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when "111" =>
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when "111" =>
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Rd_Data <= Trigger_Armed & -- Bit 7
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Rd_Data <= Trigger_Armed & -- Bit 7
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'0' & -- Bit 6
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'0' & -- Bit 6
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Trigger_Event & -- Bit 5
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Trigger_Event & -- Bit 5
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Pulse_Out & -- Bit 4
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Pulse_Out & -- Bit 4
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"0000"; -- Bits 3:0
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"0000"; -- Bits 3:0
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when others => null;
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when others => null;
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end case;
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end case;
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end if;
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end if;
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case( Interrupt_Select )is
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case( Interrupt_Select )is
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when "00" =>
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when "00" =>
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Interrupt <= '0';
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Interrupt <= '0';
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when "01" =>
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when "01" =>
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Interrupt <= Delay_Trig;
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Interrupt <= Delay_Trig;
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when "10" =>
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when "10" =>
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Interrupt <= Width_Trig;
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Interrupt <= Width_Trig;
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when "11" =>
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when "11" =>
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Interrupt <= Pulse_Done;
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Interrupt <= Pulse_Done;
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when others =>
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when others =>
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null;
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null;
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end case;
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end case;
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end if;
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end if;
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end process;
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end process;
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Time_Base_proc: process( Clock, Reset )
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Time_Base_proc: process( Clock, Reset )
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begin
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begin
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if( Reset = Reset_Level )then
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if( Reset = Reset_Level )then
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Ext_TBC_SR <= (others => '0');
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Ext_TBC_SR <= (others => '0');
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Ext_TBL_SR <= (others => '0');
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Ext_TBL_SR <= (others => '0');
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Time_Base_Status <= '0';
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Time_Base_Status <= '0';
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Timer_Tick <= '0';
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Timer_Tick <= '0';
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elsif( rising_edge(Clock) )then
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elsif( rising_edge(Clock) )then
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Ext_TBC_SR <= Ext_TBC_SR(2 downto 0) & Time_Base_Clock;
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Ext_TBC_SR <= Ext_TBC_SR(2 downto 0) & Time_Base_Clock;
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Ext_TBL_SR <= Ext_TBL_SR(2 downto 0) & Time_Base_Locked;
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Ext_TBL_SR <= Ext_TBL_SR(2 downto 0) & Time_Base_Locked;
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Time_Base_Status <= '1';
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Time_Base_Status <= '1';
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Timer_Tick <= uSec_Tick;
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Timer_Tick <= uSec_Tick;
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if( Time_Base_Source = '1' )then
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if( Time_Base_Source = '1' )then
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Time_Base_Status <= Ext_TBL_SR(3);
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Time_Base_Status <= Ext_TBL_SR(3);
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Timer_Tick <= Ext_TBC_SR(2) and not Ext_TBC_SR(3);
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Timer_Tick <= Ext_TBC_SR(2) and not Ext_TBC_SR(3);
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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Trigger_proc: process( Clock, Reset )
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Trigger_proc: process( Clock, Reset )
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begin
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begin
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if( Reset = Reset_Level )then
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if( Reset = Reset_Level )then
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Ext_Trig_SR <= (others => '0');
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Ext_Trig_SR <= (others => '0');
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Trig_RE <= '0';
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Trig_RE <= '0';
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Trig_FE <= '0';
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Trig_FE <= '0';
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Delay_Trig <= '0';
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Delay_Trig <= '0';
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Trigger_Armed <= '0';
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Trigger_Armed <= '0';
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Trigger_Event <= '0';
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Trigger_Event <= '0';
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elsif( rising_edge(Clock) )then
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elsif( rising_edge(Clock) )then
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Ext_Trig_SR <= Ext_Trig_SR(2 downto 0) & Ext_Trig;
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Ext_Trig_SR <= Ext_Trig_SR(2 downto 0) & Ext_Trig;
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Trig_RE <= Ext_Trig_SR(2) and not Ext_Trig_SR(3);
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Trig_RE <= Ext_Trig_SR(2) and not Ext_Trig_SR(3);
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Trig_FE <= Ext_Trig_SR(3) and not Ext_Trig_SR(2);
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Trig_FE <= Ext_Trig_SR(3) and not Ext_Trig_SR(2);
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Delay_Trig <= ((Trig_FE and not Trigger_Edge) or
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Delay_Trig <= ((Trig_FE and not Trigger_Edge) or
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(Trig_RE and Trigger_Edge)) and
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(Trig_RE and Trigger_Edge)) and
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Trigger_Armed and (not Trigger_Event);
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Trigger_Armed and (not Trigger_Event);
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|
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if( Arm_Timer = '1' )then
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if( Arm_Timer = '1' )then
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Trigger_Armed <= '1';
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Trigger_Armed <= '1';
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elsif( Safe_Timer = '1' )then
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elsif( Safe_Timer = '1' )then
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Trigger_Armed <= '0';
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Trigger_Armed <= '0';
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end if;
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end if;
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if( Delay_Trig = '1' )then
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if( Delay_Trig = '1' )then
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Trigger_Event <= '1';
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Trigger_Event <= '1';
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elsif( Clear_Trigd = '1' or Auto_ReArm = '1' )then
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elsif( Clear_Trigd = '1' or Auto_ReArm = '1' )then
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Trigger_Event <= '0';
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Trigger_Event <= '0';
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end if;
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end if;
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|
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end if;
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end if;
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end process;
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end process;
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Delay_proc: process( Clock, Reset )
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Delay_proc: process( Clock, Reset )
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begin
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begin
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if( Reset = Reset_Level )then
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if( Reset = Reset_Level )then
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Delay_Pending <= '0';
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Delay_Pending <= '0';
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Delay_Tmr <= (others => '0');
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Delay_Tmr <= (others => '0');
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Delay_Tmr_SR <= (others => '0');
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Delay_Tmr_SR <= (others => '0');
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Width_Trig <= '0';
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Width_Trig <= '0';
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elsif( rising_edge(Clock) )then
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elsif( rising_edge(Clock) )then
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|
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if( Delay_Trig = '1' )then
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if( Delay_Trig = '1' )then
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Delay_Pending <= '1';
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Delay_Pending <= '1';
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elsif( Timer_Tick = '1' and Delay_Pending = '1' )then
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elsif( Timer_Tick = '1' and Delay_Pending = '1' )then
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Delay_Pending <= '0';
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Delay_Pending <= '0';
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end if;
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end if;
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|
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Delay_Tmr <= Delay_Tmr - Timer_Tick;
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Delay_Tmr <= Delay_Tmr - Timer_Tick;
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if( Timer_Tick = '1' and Delay_Pending = '1' )then
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if( Timer_Tick = '1' and Delay_Pending = '1' )then
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Delay_Tmr <= Pulse_Delay;
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Delay_Tmr <= Pulse_Delay;
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elsif( Delay_Tmr = 0 )then
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elsif( Delay_Tmr = 0 )then
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Delay_Tmr <= (others => '0');
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Delay_Tmr <= (others => '0');
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end if;
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end if;
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|
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Delay_Tmr_SR <= Delay_Tmr_SR(0) & nor_reduce(Delay_Tmr);
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Delay_Tmr_SR <= Delay_Tmr_SR(0) & nor_reduce(Delay_Tmr);
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|
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-- If the pulse delay is set to zero, trigger the pulse output
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-- If the pulse delay is set to zero, trigger the pulse output
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-- immediately (overriding the timer logic) otherwise, trigger when
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-- immediately (overriding the timer logic) otherwise, trigger when
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-- the delay timer crosses from 1 to 0
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-- the delay timer crosses from 1 to 0
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Width_Trig <= (Delay_Trig and nor_reduce(Pulse_Delay)) or
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Width_Trig <= (Delay_Trig and nor_reduce(Pulse_Delay)) or
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(Delay_Tmr_SR(0) and not Delay_Tmr_SR(1));
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(Delay_Tmr_SR(0) and not Delay_Tmr_SR(1));
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|
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end if;
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end if;
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end process;
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end process;
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Timer_proc: process( Clock, Reset )
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Timer_proc: process( Clock, Reset )
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begin
|
begin
|
if( Reset = Reset_Level )then
|
if( Reset = Reset_Level )then
|
Width_Tmr <= (others => '0');
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Width_Tmr <= (others => '0');
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Pulse_Done <= '0';
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Pulse_Done <= '0';
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Pulse_Out <= '0';
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Pulse_Out <= '0';
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elsif( rising_edge(Clock) )then
|
elsif( rising_edge(Clock) )then
|
Width_Tmr <= Width_Tmr - Timer_Tick;
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Width_Tmr <= Width_Tmr - Timer_Tick;
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if( Width_Trig = '1' )then
|
if( Width_Trig = '1' )then
|
Width_Tmr <= Pulse_Width;
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Width_Tmr <= Pulse_Width;
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elsif( Width_Tmr = 0 )then
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elsif( Width_Tmr = 0 )then
|
Width_Tmr <= (others => '0');
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Width_Tmr <= (others => '0');
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end if;
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end if;
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|
|
Width_Tmr_SR <= Width_Tmr_SR(0) & nor_reduce(Width_Tmr);
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Width_Tmr_SR <= Width_Tmr_SR(0) & nor_reduce(Width_Tmr);
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|
|
Pulse_Done <= (Width_Trig and nor_reduce(Pulse_Width)) or
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Pulse_Done <= (Width_Trig and nor_reduce(Pulse_Width)) or
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(Width_Tmr_SR(0) and not Width_Tmr_SR(1));
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(Width_Tmr_SR(0) and not Width_Tmr_SR(1));
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|
|
if( Width_Trig = '1' )then
|
if( Width_Trig = '1' )then
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Pulse_Out <= '1';
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Pulse_Out <= '1';
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elsif( Pulse_Done = '1' )then
|
elsif( Pulse_Done = '1' )then
|
Pulse_Out <= '0';
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Pulse_Out <= '0';
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end if;
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end if;
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|
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end if;
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end if;
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end process;
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end process;
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