-- Copyright (c)2019 Jeremy Seth Henry
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-- Copyright (c)2019, 2020 Jeremy Seth Henry
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-- All rights reserved.
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-- All rights reserved.
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--
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--
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-- Redistribution and use in source and binary forms, with or without
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-- Redistribution and use in source and binary forms, with or without
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-- modification, are permitted provided that the following conditions are met:
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-- modification, are permitted provided that the following conditions are met:
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-- * Redistributions of source code must retain the above copyright
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-- * Redistributions of source code must retain the above copyright
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-- notice, this list of conditions and the following disclaimer.
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-- notice, this list of conditions and the following disclaimer.
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-- * Redistributions in binary form must reproduce the above copyright
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-- * Redistributions in binary form must reproduce the above copyright
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-- notice, this list of conditions and the following disclaimer in the
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-- notice, this list of conditions and the following disclaimer in the
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-- documentation and/or other materials provided with the distribution,
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-- documentation and/or other materials provided with the distribution,
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-- where applicable (as part of a user interface, debugging port, etc.)
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-- where applicable (as part of a user interface, debugging port, etc.)
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--
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--
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-- THIS SOFTWARE IS PROVIDED BY JEREMY SETH HENRY ``AS IS'' AND ANY
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-- THIS SOFTWARE IS PROVIDED BY JEREMY SETH HENRY ``AS IS'' AND ANY
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-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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-- DISCLAIMED. IN NO EVENT SHALL JEREMY SETH HENRY BE LIABLE FOR ANY
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-- DISCLAIMED. IN NO EVENT SHALL JEREMY SETH HENRY BE LIABLE FOR ANY
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-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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-- THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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--
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--
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-- VHDL Units : o8_vdsm12
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-- VHDL Units : o8_vdsm12
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-- Description: 12-bit variable delta-sigma modulator. Requires Open8_pkg.vhd
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-- Description: 12-bit variable delta-sigma modulator. Requires Open8_pkg.vhd
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--
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--
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-- Register Map:
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-- Register Map:
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-- Offset Bitfield Description Read/Write
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-- Offset Bitfield Description Read/Write
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-- 0x0 AAAAAAAA Pending DAC Level (7:0) (R/W)
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-- 0x0 AAAAAAAA Pending DAC Level (7:0) (R/W)
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-- 0x1 AAAAAAAA Pending DAC Level (11:8) (R/W)
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-- 0x1 AAAAAAAA Pending DAC Level (11:8) (R/W)
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-- 0x2 -------- Clear DAC Output (on write) (WO)
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-- 0x2 -------- Clear DAC Output (on write) (WO)
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-- 0x3 AAAAAAAA Update DAC Output (on write) (RO)
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-- 0x3 AAAAAAAA Update DAC Output (on write) (RO)
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--
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--
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-- Revision History
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-- Revision History
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-- Author Date Change
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-- Author Date Change
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------------------ -------- ---------------------------------------------------
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------------------ -------- ---------------------------------------------------
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-- Seth Henry 12/18/19 Design start
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-- Seth Henry 12/18/19 Design start
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_arith.all;
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library work;
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library work;
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use work.open8_pkg.all;
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use work.open8_pkg.all;
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entity o8_vdsm12 is
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entity o8_vdsm12 is
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generic(
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generic(
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Reset_Level : std_logic := '1';
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Reset_Level : std_logic := '1';
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Address : ADDRESS_TYPE
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Address : ADDRESS_TYPE
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);
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);
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port(
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port(
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Clock : in std_logic;
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Clock : in std_logic;
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Reset : in std_logic;
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Reset : in std_logic;
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--
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--
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Bus_Address : in ADDRESS_TYPE;
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Bus_Address : in ADDRESS_TYPE;
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Wr_Enable : in std_logic;
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Wr_Enable : in std_logic;
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Wr_Data : in DATA_TYPE;
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Wr_Data : in DATA_TYPE;
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Rd_Enable : in std_logic;
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Rd_Enable : in std_logic;
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Rd_Data : out DATA_TYPE;
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Rd_Data : out DATA_TYPE;
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--
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--
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PDM_Out : out std_logic
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PDM_Out : out std_logic
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);
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);
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end entity;
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end entity;
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architecture behave of o8_vdsm12 is
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architecture behave of o8_vdsm12 is
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constant User_Addr : std_logic_vector(15 downto 2)
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constant User_Addr : std_logic_vector(15 downto 2)
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:= Address(15 downto 2);
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:= Address(15 downto 2);
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alias Comp_Addr is Bus_Address(15 downto 2);
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alias Comp_Addr is Bus_Address(15 downto 2);
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alias Reg_Addr is Bus_Address(1 downto 0);
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alias Reg_Addr is Bus_Address(1 downto 0);
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signal Reg_Sel : std_logic_vector(1 downto 0);
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signal Reg_Sel : std_logic_vector(1 downto 0);
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signal Addr_Match : std_logic;
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signal Addr_Match : std_logic;
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signal Wr_En : std_logic;
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signal Wr_En : std_logic;
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signal Wr_Data_q : DATA_TYPE;
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signal Wr_Data_q : DATA_TYPE;
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signal Rd_En : std_logic;
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signal Rd_En : std_logic;
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constant DAC_Width : integer := 12;
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constant DAC_Width : integer := 12;
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signal DAC_Val_LB : DATA_TYPE;
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signal DAC_Val_LB : DATA_TYPE;
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signal DAC_Val_UB : DATA_TYPE;
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signal DAC_Val_UB : DATA_TYPE;
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signal DAC_Val : std_logic_vector(DAC_Width-1 downto 0);
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signal DAC_Val : std_logic_vector(DAC_Width-1 downto 0);
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constant DELTA_1_I : integer := 1;
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constant DELTA_1_I : integer := 1;
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constant DELTA_2_I : integer := 5;
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constant DELTA_2_I : integer := 5;
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constant DELTA_3_I : integer := 25;
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constant DELTA_3_I : integer := 25;
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constant DELTA_4_I : integer := 75;
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constant DELTA_4_I : integer := 75;
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constant DELTA_5_I : integer := 125;
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constant DELTA_5_I : integer := 125;
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constant DELTA_6_I : integer := 250;
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constant DELTA_6_I : integer := 250;
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constant DELTA_7_I : integer := 500;
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constant DELTA_7_I : integer := 500;
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constant DELTA_8_I : integer := 1000;
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constant DELTA_8_I : integer := 1000;
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constant DELTA_9_I : integer := 2000;
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constant DELTA_9_I : integer := 2000;
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constant DELTA_10_I : integer := 3000;
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constant DELTA_10_I : integer := 3000;
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constant DELTA_1 : std_logic_vector(DAC_Width-1 downto 0) :=
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constant DELTA_1 : std_logic_vector(DAC_Width-1 downto 0) :=
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conv_std_logic_vector(DELTA_1_I, DAC_Width);
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conv_std_logic_vector(DELTA_1_I, DAC_Width);
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constant DELTA_2 : std_logic_vector(DAC_Width-1 downto 0) :=
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constant DELTA_2 : std_logic_vector(DAC_Width-1 downto 0) :=
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conv_std_logic_vector(DELTA_2_I, DAC_Width);
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conv_std_logic_vector(DELTA_2_I, DAC_Width);
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constant DELTA_3 : std_logic_vector(DAC_Width-1 downto 0) :=
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constant DELTA_3 : std_logic_vector(DAC_Width-1 downto 0) :=
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conv_std_logic_vector(DELTA_3_I, DAC_Width);
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conv_std_logic_vector(DELTA_3_I, DAC_Width);
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constant DELTA_4 : std_logic_vector(DAC_Width-1 downto 0) :=
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constant DELTA_4 : std_logic_vector(DAC_Width-1 downto 0) :=
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conv_std_logic_vector(DELTA_4_I, DAC_Width);
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conv_std_logic_vector(DELTA_4_I, DAC_Width);
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constant DELTA_5 : std_logic_vector(DAC_Width-1 downto 0) :=
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constant DELTA_5 : std_logic_vector(DAC_Width-1 downto 0) :=
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conv_std_logic_vector(DELTA_5_I, DAC_Width);
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conv_std_logic_vector(DELTA_5_I, DAC_Width);
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constant DELTA_6 : std_logic_vector(DAC_Width-1 downto 0) :=
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constant DELTA_6 : std_logic_vector(DAC_Width-1 downto 0) :=
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conv_std_logic_vector(DELTA_6_I, DAC_Width);
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conv_std_logic_vector(DELTA_6_I, DAC_Width);
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constant DELTA_7 : std_logic_vector(DAC_Width-1 downto 0) :=
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constant DELTA_7 : std_logic_vector(DAC_Width-1 downto 0) :=
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conv_std_logic_vector(DELTA_7_I, DAC_Width);
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conv_std_logic_vector(DELTA_7_I, DAC_Width);
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constant DELTA_8 : std_logic_vector(DAC_Width-1 downto 0) :=
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constant DELTA_8 : std_logic_vector(DAC_Width-1 downto 0) :=
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conv_std_logic_vector(DELTA_8_I, DAC_Width);
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conv_std_logic_vector(DELTA_8_I, DAC_Width);
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constant DELTA_9 : std_logic_vector(DAC_Width-1 downto 0) :=
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constant DELTA_9 : std_logic_vector(DAC_Width-1 downto 0) :=
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conv_std_logic_vector(DELTA_9_I, DAC_Width);
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conv_std_logic_vector(DELTA_9_I, DAC_Width);
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constant DELTA_10 : std_logic_vector(DAC_Width-1 downto 0) :=
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constant DELTA_10 : std_logic_vector(DAC_Width-1 downto 0) :=
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conv_std_logic_vector(DELTA_10_I, DAC_Width);
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conv_std_logic_vector(DELTA_10_I, DAC_Width);
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constant MAX_PERIOD : integer := 2**DAC_Width;
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constant MAX_PERIOD : integer := 2**DAC_Width;
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constant DIV_WIDTH : integer := DAC_Width * 2;
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constant DIV_WIDTH : integer := DAC_Width * 2;
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constant PADJ_1_I : integer := DELTA_1_I * MAX_PERIOD;
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constant PADJ_1_I : integer := DELTA_1_I * MAX_PERIOD;
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constant PADJ_2_I : integer := DELTA_2_I * MAX_PERIOD;
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constant PADJ_2_I : integer := DELTA_2_I * MAX_PERIOD;
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constant PADJ_3_I : integer := DELTA_3_I * MAX_PERIOD;
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constant PADJ_3_I : integer := DELTA_3_I * MAX_PERIOD;
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constant PADJ_4_I : integer := DELTA_4_I * MAX_PERIOD;
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constant PADJ_4_I : integer := DELTA_4_I * MAX_PERIOD;
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constant PADJ_5_I : integer := DELTA_5_I * MAX_PERIOD;
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constant PADJ_5_I : integer := DELTA_5_I * MAX_PERIOD;
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constant PADJ_6_I : integer := DELTA_6_I * MAX_PERIOD;
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constant PADJ_6_I : integer := DELTA_6_I * MAX_PERIOD;
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constant PADJ_7_I : integer := DELTA_7_I * MAX_PERIOD;
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constant PADJ_7_I : integer := DELTA_7_I * MAX_PERIOD;
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constant PADJ_8_I : integer := DELTA_8_I * MAX_PERIOD;
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constant PADJ_8_I : integer := DELTA_8_I * MAX_PERIOD;
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constant PADJ_9_I : integer := DELTA_9_I * MAX_PERIOD;
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constant PADJ_9_I : integer := DELTA_9_I * MAX_PERIOD;
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constant PADJ_10_I : integer := DELTA_10_I * MAX_PERIOD;
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constant PADJ_10_I : integer := DELTA_10_I * MAX_PERIOD;
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constant PADJ_1 : std_logic_vector(DIV_WIDTH-1 downto 0) :=
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constant PADJ_1 : std_logic_vector(DIV_WIDTH-1 downto 0) :=
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conv_std_logic_vector(PADJ_1_I,DIV_WIDTH);
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conv_std_logic_vector(PADJ_1_I,DIV_WIDTH);
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constant PADJ_2 : std_logic_vector(DIV_WIDTH-1 downto 0) :=
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constant PADJ_2 : std_logic_vector(DIV_WIDTH-1 downto 0) :=
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conv_std_logic_vector(PADJ_2_I,DIV_WIDTH);
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conv_std_logic_vector(PADJ_2_I,DIV_WIDTH);
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constant PADJ_3 : std_logic_vector(DIV_WIDTH-1 downto 0) :=
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constant PADJ_3 : std_logic_vector(DIV_WIDTH-1 downto 0) :=
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conv_std_logic_vector(PADJ_3_I,DIV_WIDTH);
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conv_std_logic_vector(PADJ_3_I,DIV_WIDTH);
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constant PADJ_4 : std_logic_vector(DIV_WIDTH-1 downto 0) :=
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constant PADJ_4 : std_logic_vector(DIV_WIDTH-1 downto 0) :=
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conv_std_logic_vector(PADJ_4_I,DIV_WIDTH);
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conv_std_logic_vector(PADJ_4_I,DIV_WIDTH);
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constant PADJ_5 : std_logic_vector(DIV_WIDTH-1 downto 0) :=
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constant PADJ_5 : std_logic_vector(DIV_WIDTH-1 downto 0) :=
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conv_std_logic_vector(PADJ_5_I,DIV_WIDTH);
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conv_std_logic_vector(PADJ_5_I,DIV_WIDTH);
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constant PADJ_6 : std_logic_vector(DIV_WIDTH-1 downto 0) :=
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constant PADJ_6 : std_logic_vector(DIV_WIDTH-1 downto 0) :=
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conv_std_logic_vector(PADJ_6_I,DIV_WIDTH);
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conv_std_logic_vector(PADJ_6_I,DIV_WIDTH);
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constant PADJ_7 : std_logic_vector(DIV_WIDTH-1 downto 0) :=
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constant PADJ_7 : std_logic_vector(DIV_WIDTH-1 downto 0) :=
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conv_std_logic_vector(PADJ_7_I,DIV_WIDTH);
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conv_std_logic_vector(PADJ_7_I,DIV_WIDTH);
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constant PADJ_8 : std_logic_vector(DIV_WIDTH-1 downto 0) :=
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constant PADJ_8 : std_logic_vector(DIV_WIDTH-1 downto 0) :=
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conv_std_logic_vector(PADJ_8_I,DIV_WIDTH);
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conv_std_logic_vector(PADJ_8_I,DIV_WIDTH);
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constant PADJ_9 : std_logic_vector(DIV_WIDTH-1 downto 0) :=
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constant PADJ_9 : std_logic_vector(DIV_WIDTH-1 downto 0) :=
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conv_std_logic_vector(PADJ_9_I,DIV_WIDTH);
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conv_std_logic_vector(PADJ_9_I,DIV_WIDTH);
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constant PADJ_10 : std_logic_vector(DIV_WIDTH-1 downto 0) :=
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constant PADJ_10 : std_logic_vector(DIV_WIDTH-1 downto 0) :=
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conv_std_logic_vector(PADJ_10_I,DIV_WIDTH);
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conv_std_logic_vector(PADJ_10_I,DIV_WIDTH);
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signal DACin_q : std_logic_vector(DAC_Width-1 downto 0);
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signal DACin_q : std_logic_vector(DAC_Width-1 downto 0);
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signal Divisor : std_logic_vector(DIV_WIDTH-1 downto 0);
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signal Divisor : std_logic_vector(DIV_WIDTH-1 downto 0);
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signal Dividend : std_logic_vector(DIV_WIDTH-1 downto 0);
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signal Dividend : std_logic_vector(DIV_WIDTH-1 downto 0);
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signal q : std_logic_vector(DIV_WIDTH*2-1 downto 0);
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signal q : std_logic_vector(DIV_WIDTH*2-1 downto 0);
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signal diff : std_logic_vector(DIV_WIDTH downto 0);
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signal diff : std_logic_vector(DIV_WIDTH downto 0);
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constant CB : integer := ceil_log2(DIV_WIDTH);
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constant CB : integer := ceil_log2(DIV_WIDTH);
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signal count : std_logic_vector(CB-1 downto 0);
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signal count : std_logic_vector(CB-1 downto 0);
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signal Next_Width : std_logic_vector(DAC_Width-1 downto 0);
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signal Next_Width : std_logic_vector(DAC_Width-1 downto 0);
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signal Next_Period : std_logic_vector(DAC_Width-1 downto 0);
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signal Next_Period : std_logic_vector(DAC_Width-1 downto 0);
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signal PWM_Width : std_logic_vector(DAC_Width-1 downto 0);
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signal PWM_Width : std_logic_vector(DAC_Width-1 downto 0);
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signal PWM_Period : std_logic_vector(DAC_Width-1 downto 0);
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signal PWM_Period : std_logic_vector(DAC_Width-1 downto 0);
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signal Width_Ctr : std_logic_vector(DAC_Width-1 downto 0);
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signal Width_Ctr : std_logic_vector(DAC_Width-1 downto 0);
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signal Period_Ctr : std_logic_vector(DAC_Width-1 downto 0);
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signal Period_Ctr : std_logic_vector(DAC_Width-1 downto 0);
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begin
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begin
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Addr_Match <= '1' when Comp_Addr = User_Addr else '0';
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Addr_Match <= '1' when Comp_Addr = User_Addr else '0';
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io_reg: process( Clock, Reset )
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io_reg: process( Clock, Reset )
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begin
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begin
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if( Reset = Reset_Level )then
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if( Reset = Reset_Level )then
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Reg_Sel <= "00";
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Reg_Sel <= "00";
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Rd_En <= '0';
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Rd_En <= '0';
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Rd_Data <= OPEN8_NULLBUS;
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Rd_Data <= OPEN8_NULLBUS;
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Wr_En <= '0';
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Wr_En <= '0';
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Wr_Data_q <= x"00";
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Wr_Data_q <= x"00";
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DAC_Val_LB <= x"00";
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DAC_Val_LB <= x"00";
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DAC_Val_UB <= x"00";
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DAC_Val_UB <= x"00";
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DAC_Val <= (others => '0');
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DAC_Val <= (others => '0');
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elsif( rising_edge( Clock ) )then
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elsif( rising_edge( Clock ) )then
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Reg_Sel <= Reg_Addr;
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Reg_Sel <= Reg_Addr;
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Wr_En <= Addr_Match and Wr_Enable;
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Wr_En <= Addr_Match and Wr_Enable;
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Wr_Data_q <= Wr_Data;
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Wr_Data_q <= Wr_Data;
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if( Wr_En = '1' )then
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if( Wr_En = '1' )then
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case( Reg_Sel )is
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case( Reg_Sel )is
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when "00" =>
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when "00" =>
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DAC_Val_LB <= Wr_Data_q;
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DAC_Val_LB <= Wr_Data_q;
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when "01" =>
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when "01" =>
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DAC_Val_UB <= "0000" & Wr_Data_q(3 downto 0);
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DAC_Val_UB <= "0000" & Wr_Data_q(3 downto 0);
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when "10" =>
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when "10" =>
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DAC_Val <= (others => '0');
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DAC_Val <= (others => '0');
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when "11" =>
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when "11" =>
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DAC_Val <= DAC_Val_UB(3 downto 0) & DAC_Val_LB;
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DAC_Val <= DAC_Val_UB(3 downto 0) & DAC_Val_LB;
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when others => null;
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when others => null;
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end case;
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end case;
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end if;
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end if;
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Rd_Data <= OPEN8_NULLBUS;
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Rd_Data <= OPEN8_NULLBUS;
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Rd_En <= Addr_Match and Rd_Enable;
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Rd_En <= Addr_Match and Rd_Enable;
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if( Rd_En = '1' )then
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if( Rd_En = '1' )then
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case( Reg_Sel )is
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case( Reg_Sel )is
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when "00" =>
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when "00" =>
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Rd_Data <= DAC_Val_LB;
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Rd_Data <= DAC_Val_LB;
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when "01" =>
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when "01" =>
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Rd_Data <= DAC_Val_UB;
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Rd_Data <= DAC_Val_UB;
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when others => null;
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when others => null;
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end case;
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end case;
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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diff <= ('0' & q(DIV_WIDTH*2-2 downto DIV_WIDTH-1)) -
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diff <= ('0' & q(DIV_WIDTH*2-2 downto DIV_WIDTH-1)) -
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('0' & Divisor);
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('0' & Divisor);
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Dividend <= PADJ_2 when DACin_q >= DELTA_2_I and DACin_q < DELTA_3_I else
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Dividend <= PADJ_2 when DACin_q >= DELTA_2_I and DACin_q < DELTA_3_I else
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PADJ_3 when DACin_q >= DELTA_3_I and DACin_q < DELTA_4_I else
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PADJ_3 when DACin_q >= DELTA_3_I and DACin_q < DELTA_4_I else
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PADJ_4 when DACin_q >= DELTA_4_I and DACin_q < DELTA_5_I else
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PADJ_4 when DACin_q >= DELTA_4_I and DACin_q < DELTA_5_I else
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PADJ_5 when DACin_q >= DELTA_5_I and DACin_q < DELTA_6_I else
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PADJ_5 when DACin_q >= DELTA_5_I and DACin_q < DELTA_6_I else
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PADJ_6 when DACin_q >= DELTA_6_I and DACin_q < DELTA_7_I else
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PADJ_6 when DACin_q >= DELTA_6_I and DACin_q < DELTA_7_I else
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PADJ_7 when DACin_q >= DELTA_7_I and DACin_q < DELTA_8_I else
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PADJ_7 when DACin_q >= DELTA_7_I and DACin_q < DELTA_8_I else
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PADJ_8 when DACin_q >= DELTA_8_I and DACin_q < DELTA_9_I else
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PADJ_8 when DACin_q >= DELTA_8_I and DACin_q < DELTA_9_I else
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PADJ_9 when DACin_q >= DELTA_9_I and DACin_q < DELTA_10_I else
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PADJ_9 when DACin_q >= DELTA_9_I and DACin_q < DELTA_10_I else
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PADJ_10 when DACin_q >= DELTA_10_I else
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PADJ_10 when DACin_q >= DELTA_10_I else
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PADJ_1;
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PADJ_1;
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Next_Width <= DELTA_1 when DACin_q >= DELTA_1_I and DACin_q < DELTA_2_I else
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Next_Width <= DELTA_1 when DACin_q >= DELTA_1_I and DACin_q < DELTA_2_I else
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DELTA_2 when DACin_q >= DELTA_2_I and DACin_q < DELTA_3_I else
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DELTA_2 when DACin_q >= DELTA_2_I and DACin_q < DELTA_3_I else
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DELTA_3 when DACin_q >= DELTA_3_I and DACin_q < DELTA_4_I else
|
DELTA_3 when DACin_q >= DELTA_3_I and DACin_q < DELTA_4_I else
|
DELTA_4 when DACin_q >= DELTA_4_I and DACin_q < DELTA_5_I else
|
DELTA_4 when DACin_q >= DELTA_4_I and DACin_q < DELTA_5_I else
|
DELTA_5 when DACin_q >= DELTA_5_I and DACin_q < DELTA_6_I else
|
DELTA_5 when DACin_q >= DELTA_5_I and DACin_q < DELTA_6_I else
|
DELTA_6 when DACin_q >= DELTA_6_I and DACin_q < DELTA_7_I else
|
DELTA_6 when DACin_q >= DELTA_6_I and DACin_q < DELTA_7_I else
|
DELTA_7 when DACin_q >= DELTA_7_I and DACin_q < DELTA_8_I else
|
DELTA_7 when DACin_q >= DELTA_7_I and DACin_q < DELTA_8_I else
|
DELTA_8 when DACin_q >= DELTA_8_I and DACin_q < DELTA_9_I else
|
DELTA_8 when DACin_q >= DELTA_8_I and DACin_q < DELTA_9_I else
|
DELTA_9 when DACin_q >= DELTA_9_I and DACin_q < DELTA_10_I else
|
DELTA_9 when DACin_q >= DELTA_9_I and DACin_q < DELTA_10_I else
|
DELTA_10 when DACin_q >= DELTA_10_I else
|
DELTA_10 when DACin_q >= DELTA_10_I else
|
(others => '0');
|
(others => '0');
|
|
|
Next_Period <= q(DAC_Width-1 downto 0) - 1;
|
Next_Period <= q(DAC_Width-1 downto 0) - 1;
|
|
|
vDSM_proc: process( Clock, Reset )
|
vDSM_proc: process( Clock, Reset )
|
begin
|
begin
|
if( Reset = Reset_Level )then
|
if( Reset = Reset_Level )then
|
q <= (others => '0');
|
q <= (others => '0');
|
count <= (others => '1');
|
count <= (others => '1');
|
Divisor <= (others => '0');
|
Divisor <= (others => '0');
|
DACin_q <= (others => '0');
|
DACin_q <= (others => '0');
|
PWM_Width <= (others => '0');
|
PWM_Width <= (others => '0');
|
PWM_Period <= (others => '0');
|
PWM_Period <= (others => '0');
|
Period_Ctr <= (others => '0');
|
Period_Ctr <= (others => '0');
|
Width_Ctr <= (others => '0');
|
Width_Ctr <= (others => '0');
|
PDM_Out <= '0';
|
PDM_Out <= '0';
|
elsif( rising_edge(Clock) )then
|
elsif( rising_edge(Clock) )then
|
q <= diff(DIV_WIDTH-1 downto 0) &
|
q <= diff(DIV_WIDTH-1 downto 0) &
|
q(DIV_WIDTH-2 downto 0) & '1';
|
q(DIV_WIDTH-2 downto 0) & '1';
|
if( diff(DIV_WIDTH) = '1' )then
|
if( diff(DIV_WIDTH) = '1' )then
|
q <= q(DIV_WIDTH*2-2 downto 0) & '0';
|
q <= q(DIV_WIDTH*2-2 downto 0) & '0';
|
end if;
|
end if;
|
|
|
count <= count + 1;
|
count <= count + 1;
|
if( count = DIV_WIDTH )then
|
if( count = DIV_WIDTH )then
|
PWM_Width <= Next_Width;
|
PWM_Width <= Next_Width;
|
PWM_Period <= Next_Period;
|
PWM_Period <= Next_Period;
|
DACin_q <= DAC_val;
|
DACin_q <= DAC_val;
|
Divisor <= (others => '0');
|
Divisor <= (others => '0');
|
Divisor(DAC_Width-1 downto 0) <= DACin_q;
|
Divisor(DAC_Width-1 downto 0) <= DACin_q;
|
q <= conv_std_logic_vector(0,DIV_WIDTH) & Dividend;
|
q <= conv_std_logic_vector(0,DIV_WIDTH) & Dividend;
|
count <= (others => '0');
|
count <= (others => '0');
|
end if;
|
end if;
|
|
|
Period_Ctr <= Period_Ctr - 1;
|
Period_Ctr <= Period_Ctr - 1;
|
Width_Ctr <= Width_Ctr - 1;
|
Width_Ctr <= Width_Ctr - 1;
|
|
|
PDM_Out <= '1';
|
PDM_Out <= '1';
|
if( Width_Ctr = 0 )then
|
if( Width_Ctr = 0 )then
|
PDM_Out <= '0';
|
PDM_Out <= '0';
|
Width_Ctr <= (others => '0');
|
Width_Ctr <= (others => '0');
|
end if;
|
end if;
|
|
|
if( Period_Ctr = 0 )then
|
if( Period_Ctr = 0 )then
|
Period_Ctr <= PWM_Period;
|
Period_Ctr <= PWM_Period;
|
Width_Ctr <= PWM_Width;
|
Width_Ctr <= PWM_Width;
|
end if;
|
end if;
|
|
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
end architecture;
|
end architecture;
|
|
|
