-- Copyright (c)2020 Jeremy Seth Henry
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-- Copyright (c)2020 Jeremy Seth Henry
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-- All rights reserved.
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-- All rights reserved.
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--
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--
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-- Redistribution and use in source and binary forms, with or without
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-- Redistribution and use in source and binary forms, with or without
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-- modification, are permitted provided that the following conditions are met:
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-- modification, are permitted provided that the following conditions are met:
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-- * Redistributions of source code must retain the above copyright
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-- * Redistributions of source code must retain the above copyright
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-- notice, this list of conditions and the following disclaimer.
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-- notice, this list of conditions and the following disclaimer.
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-- * Redistributions in binary form must reproduce the above copyright
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-- * Redistributions in binary form must reproduce the above copyright
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-- notice, this list of conditions and the following disclaimer in the
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-- notice, this list of conditions and the following disclaimer in the
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-- documentation and/or other materials provided with the distribution,
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-- documentation and/or other materials provided with the distribution,
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-- where applicable (as part of a user interface, debugging port, etc.)
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-- where applicable (as part of a user interface, debugging port, etc.)
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--
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--
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-- THIS SOFTWARE IS PROVIDED BY JEREMY SETH HENRY ``AS IS'' AND ANY
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-- THIS SOFTWARE IS PROVIDED BY JEREMY SETH HENRY ``AS IS'' AND ANY
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-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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-- DISCLAIMED. IN NO EVENT SHALL JEREMY SETH HENRY BE LIABLE FOR ANY
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-- DISCLAIMED. IN NO EVENT SHALL JEREMY SETH HENRY BE LIABLE FOR ANY
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-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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-- THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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-- THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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--
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--
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-- VHDL Units : crc16_ccitt
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-- VHDL Units : crc16_ccitt
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-- Description: Implements the 16-bit CCITT CRC on byte-wide data. Logic
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-- Description: Implements the 16-bit CCITT CRC on byte-wide data. Logic
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-- equations were taken from Intel/Altera app note AN049.
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-- equations were taken from Intel/Altera app note AN049.
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--
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--
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-- Revision History
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-- Revision History
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-- Author Date Change
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-- Author Date Change
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------------------ -------- ---------------------------------------------------
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------------------ -------- ---------------------------------------------------
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-- Seth Henry 04/14/20 Code cleanup and revision section added
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-- Seth Henry 12/09/20 Created from original version
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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library work;
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use work.sdlc_serial_pkg.all;
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entity sdlc_crc16_ccitt is
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entity sdlc_crc16_ccitt is
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generic(
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generic(
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Poly_Init : std_logic_vector(15 downto 0) := x"0000";
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Poly_Init : std_logic_vector(15 downto 0) := x"0000";
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Reset_Level : std_logic := '1'
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Reset_Level : std_logic := '1'
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);
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);
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port(
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port(
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Clock : in std_logic;
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Clock : in std_logic;
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Reset : in std_logic;
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Reset : in std_logic;
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--
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--
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Clear : in std_logic;
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Clear : in std_logic;
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Wr_En : in std_logic;
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Wr_En : in std_logic;
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Wr_Data : in DATA_IN_TYPE;
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Wr_Data : in std_logic_vector(7 downto 0);
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--
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--
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CRC16_Valid : out std_logic;
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CRC16_Valid : out std_logic;
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CRC16_Out : out CRC_OUT_TYPE
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CRC16_Out : out std_logic_vector(15 downto 0)
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);
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);
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end entity;
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end entity;
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architecture behave of sdlc_crc16_ccitt is
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architecture behave of sdlc_crc16_ccitt is
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signal Calc_En : std_logic := '0';
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signal Calc_En : std_logic := '0';
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signal Buffer_En : std_logic := '0';
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signal Buffer_En : std_logic := '0';
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signal Data : DATA_IN_TYPE := x"00";
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signal Data : std_logic_vector(7 downto 0) := x"00";
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signal Exr : DATA_IN_TYPE := x"00";
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signal Exr : std_logic_vector(7 downto 0) := x"00";
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signal Reg : CRC_OUT_TYPE := x"0000";
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signal Reg : std_logic_vector(15 downto 0) := x"0000";
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begin
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begin
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Exr(0) <= Reg(0) xor Data(0);
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Exr(0) <= Reg(0) xor Data(0);
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Exr(1) <= Reg(1) xor Data(1);
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Exr(1) <= Reg(1) xor Data(1);
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Exr(2) <= Reg(2) xor Data(2);
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Exr(2) <= Reg(2) xor Data(2);
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Exr(3) <= Reg(3) xor Data(3);
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Exr(3) <= Reg(3) xor Data(3);
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Exr(4) <= Reg(4) xor Data(4);
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Exr(4) <= Reg(4) xor Data(4);
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Exr(5) <= Reg(5) xor Data(5);
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Exr(5) <= Reg(5) xor Data(5);
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Exr(6) <= Reg(6) xor Data(6);
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Exr(6) <= Reg(6) xor Data(6);
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Exr(7) <= Reg(7) xor Data(7);
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Exr(7) <= Reg(7) xor Data(7);
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CRC16_Calc: process( Clock, Reset )
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CRC16_Calc: process( Clock, Reset )
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begin
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begin
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if( Reset = Reset_Level )then
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if( Reset = Reset_Level )then
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Calc_En <= '0';
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Calc_En <= '0';
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Buffer_En <= '0';
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Buffer_En <= '0';
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Data <= x"00";
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Data <= x"00";
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Reg <= Poly_Init;
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Reg <= Poly_Init;
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CRC16_Out <= x"0000";
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CRC16_Out <= x"0000";
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CRC16_Valid <= '0';
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CRC16_Valid <= '0';
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elsif( rising_edge(Clock) )then
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elsif( rising_edge(Clock) )then
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Calc_En <= Wr_En;
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Calc_En <= Wr_En;
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if( Wr_En = '1' )then
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if( Wr_En = '1' )then
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Data <= Wr_Data;
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Data <= Wr_Data;
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end if;
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end if;
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if( Calc_En = '1' )then
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if( Calc_En = '1' )then
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Reg(0) <= Reg(8) xor Exr(4) xor Exr(0);
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Reg(0) <= Reg(8) xor Exr(4) xor Exr(0);
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Reg(1) <= Reg(9) xor Exr(5) xor Exr(1);
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Reg(1) <= Reg(9) xor Exr(5) xor Exr(1);
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Reg(2) <= Reg(10) xor Exr(6) xor Exr(2);
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Reg(2) <= Reg(10) xor Exr(6) xor Exr(2);
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Reg(3) <= Reg(11) xor Exr(0) xor Exr(7) xor Exr(3);
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Reg(3) <= Reg(11) xor Exr(0) xor Exr(7) xor Exr(3);
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Reg(4) <= Reg(12) xor Exr(1) ;
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Reg(4) <= Reg(12) xor Exr(1) ;
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Reg(5) <= Reg(13) xor Exr(2) ;
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Reg(5) <= Reg(13) xor Exr(2) ;
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Reg(6) <= Reg(14) xor Exr(3) ;
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Reg(6) <= Reg(14) xor Exr(3) ;
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Reg(7) <= Reg(15) xor Exr(4) xor Exr(0);
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Reg(7) <= Reg(15) xor Exr(4) xor Exr(0);
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Reg(8) <= Exr(0) xor Exr(5) xor Exr(1);
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Reg(8) <= Exr(0) xor Exr(5) xor Exr(1);
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Reg(9) <= Exr(1) xor Exr(6) xor Exr(2);
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Reg(9) <= Exr(1) xor Exr(6) xor Exr(2);
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Reg(10) <= Exr(2) xor Exr(7) xor Exr(3);
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Reg(10) <= Exr(2) xor Exr(7) xor Exr(3);
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Reg(11) <= Exr(3) ;
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Reg(11) <= Exr(3) ;
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Reg(12) <= Exr(4) xor Exr(0);
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Reg(12) <= Exr(4) xor Exr(0);
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Reg(13) <= Exr(5) xor Exr(1);
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Reg(13) <= Exr(5) xor Exr(1);
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Reg(14) <= Exr(6) xor Exr(2);
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Reg(14) <= Exr(6) xor Exr(2);
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Reg(15) <= Exr(7) xor Exr(3);
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Reg(15) <= Exr(7) xor Exr(3);
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end if;
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end if;
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if( Clear = '1' )then
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if( Clear = '1' )then
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Reg <= Poly_Init;
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Reg <= Poly_Init;
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end if;
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end if;
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Buffer_En <= Calc_En;
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Buffer_En <= Calc_En;
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if( Buffer_En = '1' )then
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if( Buffer_En = '1' )then
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CRC16_Out <= Reg xor x"FFFF";
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CRC16_Out <= Reg xor x"FFFF";
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end if;
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end if;
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CRC16_Valid <= Buffer_En;
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CRC16_Valid <= Buffer_En;
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end if;
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end if;
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end process;
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end process;
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end architecture;
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end architecture;
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