-- Copyright (c)2018, 2020 Jeremy Seth Henry
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-- Copyright (c)2018, 2020 Jeremy Seth Henry
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-- All rights reserved.
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-- All rights reserved.
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--
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--
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-- Redistribution and use in source and binary forms, with or without
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-- Redistribution and use in source and binary forms, with or without
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-- modification, are permitted provided that the following conditions are met:
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-- modification, are permitted provided that the following conditions are met:
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-- * Redistributions of source code must retain the above copyright
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-- * Redistributions of source code must retain the above copyright
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-- notice, this list of conditions and the following disclaimer.
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-- notice, this list of conditions and the following disclaimer.
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-- * Redistributions in binary form must reproduce the above copyright
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-- * Redistributions in binary form must reproduce the above copyright
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-- notice, this list of conditions and the following disclaimer in the
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-- notice, this list of conditions and the following disclaimer in the
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-- documentation and/or other materials provided with the distribution,
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-- documentation and/or other materials provided with the distribution,
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-- where applicable (as part of a user interface, debugging port, etc.)
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-- where applicable (as part of a user interface, debugging port, etc.)
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--
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--
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-- THIS SOFTWARE IS PROVIDED BY JEREMY SETH HENRY ``AS IS'' AND ANY
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-- THIS SOFTWARE IS PROVIDED BY JEREMY SETH HENRY ``AS IS'' AND ANY
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-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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-- DISCLAIMED. IN NO EVENT SHALL JEREMY SETH HENRY BE LIABLE FOR ANY
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-- DISCLAIMED. IN NO EVENT SHALL JEREMY SETH HENRY BE LIABLE FOR ANY
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-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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-- THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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--
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--
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-- VHDL Units : vdsm8
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-- VHDL Units : vdsm8
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-- Description: 8-bit variable delta-sigma modulator single-bit DAC
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-- Description: 8-bit variable delta-sigma modulator single-bit DAC
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--
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--
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-- Revision History
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-- Revision History
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-- Author Date Change
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-- Author Date Change
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------------------ -------- ---------------------------------------------------
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------------------ -------- ---------------------------------------------------
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-- Seth Henry 04/25/18 Initial design
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-- Seth Henry 04/25/18 Initial design
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-- Seth Henry 04/14/20 Code cleanup and revision section added
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-- Seth Henry 04/14/20 Code cleanup and revision section added
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_arith.all;
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entity vdsm8 is
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entity vdsm8 is
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generic(
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generic(
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Reset_Level : std_logic := '1';
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Reset_Level : std_logic := '1';
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-- Do not adjust alone! DELTA constants must be
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-- Do not adjust alone! DELTA constants must be
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-- changed as well.
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-- changed as well.
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DAC_Width : integer := 8
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DAC_Width : integer := 8
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);
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);
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port(
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port(
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Clock : in std_logic;
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Clock : in std_logic;
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Reset : in std_logic;
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Reset : in std_logic;
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DACin : in std_logic_vector(DAC_Width-1 downto 0);
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DACin : in std_logic_vector(DAC_Width-1 downto 0);
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DACout : out std_logic
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DACout : out std_logic
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);
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);
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end entity;
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end entity;
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architecture behave of vdsm8 is
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architecture behave of vdsm8 is
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function ceil_log2 (x : in natural) return natural is
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function ceil_log2 (x : in natural) return natural is
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variable retval : natural;
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variable retval : natural;
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begin
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begin
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retval := 1;
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retval := 1;
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while ((2**retval) - 1) < x loop
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while ((2**retval) - 1) < x loop
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retval := retval + 1;
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retval := retval + 1;
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end loop;
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end loop;
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return retval;
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return retval;
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end function;
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end function;
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constant DELTA_1_I : integer := 1;
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constant DELTA_1_I : integer := 1;
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constant DELTA_2_I : integer := 5;
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constant DELTA_2_I : integer := 5;
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constant DELTA_3_I : integer := 25;
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constant DELTA_3_I : integer := 25;
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constant DELTA_4_I : integer := 75;
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constant DELTA_4_I : integer := 75;
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constant DELTA_5_I : integer := 125;
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constant DELTA_5_I : integer := 125;
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constant DELTA_6_I : integer := 195;
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constant DELTA_6_I : integer := 195;
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constant DELTA_1 : std_logic_vector(DAC_Width-1 downto 0) :=
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constant DELTA_1 : std_logic_vector(DAC_Width-1 downto 0) :=
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conv_std_logic_vector(DELTA_1_I, DAC_Width);
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conv_std_logic_vector(DELTA_1_I, DAC_Width);
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constant DELTA_2 : std_logic_vector(DAC_Width-1 downto 0) :=
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constant DELTA_2 : std_logic_vector(DAC_Width-1 downto 0) :=
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conv_std_logic_vector(DELTA_2_I, DAC_Width);
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conv_std_logic_vector(DELTA_2_I, DAC_Width);
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constant DELTA_3 : std_logic_vector(DAC_Width-1 downto 0) :=
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constant DELTA_3 : std_logic_vector(DAC_Width-1 downto 0) :=
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conv_std_logic_vector(DELTA_3_I, DAC_Width);
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conv_std_logic_vector(DELTA_3_I, DAC_Width);
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constant DELTA_4 : std_logic_vector(DAC_Width-1 downto 0) :=
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constant DELTA_4 : std_logic_vector(DAC_Width-1 downto 0) :=
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conv_std_logic_vector(DELTA_4_I, DAC_Width);
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conv_std_logic_vector(DELTA_4_I, DAC_Width);
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constant DELTA_5 : std_logic_vector(DAC_Width-1 downto 0) :=
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constant DELTA_5 : std_logic_vector(DAC_Width-1 downto 0) :=
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conv_std_logic_vector(DELTA_5_I, DAC_Width);
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conv_std_logic_vector(DELTA_5_I, DAC_Width);
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constant DELTA_6 : std_logic_vector(DAC_Width-1 downto 0) :=
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constant DELTA_6 : std_logic_vector(DAC_Width-1 downto 0) :=
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conv_std_logic_vector(DELTA_6_I, DAC_Width);
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conv_std_logic_vector(DELTA_6_I, DAC_Width);
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constant MAX_PERIOD : integer := 2**DAC_Width;
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constant MAX_PERIOD : integer := 2**DAC_Width;
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constant DIV_WIDTH : integer := DAC_Width * 2;
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constant DIV_WIDTH : integer := DAC_Width * 2;
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constant PADJ_1_I : integer := DELTA_1_I * MAX_PERIOD;
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constant PADJ_1_I : integer := DELTA_1_I * MAX_PERIOD;
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constant PADJ_2_I : integer := DELTA_2_I * MAX_PERIOD;
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constant PADJ_2_I : integer := DELTA_2_I * MAX_PERIOD;
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constant PADJ_3_I : integer := DELTA_3_I * MAX_PERIOD;
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constant PADJ_3_I : integer := DELTA_3_I * MAX_PERIOD;
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constant PADJ_4_I : integer := DELTA_4_I * MAX_PERIOD;
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constant PADJ_4_I : integer := DELTA_4_I * MAX_PERIOD;
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constant PADJ_5_I : integer := DELTA_5_I * MAX_PERIOD;
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constant PADJ_5_I : integer := DELTA_5_I * MAX_PERIOD;
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constant PADJ_6_I : integer := DELTA_6_I * MAX_PERIOD;
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constant PADJ_6_I : integer := DELTA_6_I * MAX_PERIOD;
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constant PADJ_1 : std_logic_vector(DIV_WIDTH-1 downto 0) :=
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constant PADJ_1 : std_logic_vector(DIV_WIDTH-1 downto 0) :=
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conv_std_logic_vector(PADJ_1_I,DIV_WIDTH);
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conv_std_logic_vector(PADJ_1_I,DIV_WIDTH);
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constant PADJ_2 : std_logic_vector(DIV_WIDTH-1 downto 0) :=
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constant PADJ_2 : std_logic_vector(DIV_WIDTH-1 downto 0) :=
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conv_std_logic_vector(PADJ_2_I,DIV_WIDTH);
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conv_std_logic_vector(PADJ_2_I,DIV_WIDTH);
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constant PADJ_3 : std_logic_vector(DIV_WIDTH-1 downto 0) :=
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constant PADJ_3 : std_logic_vector(DIV_WIDTH-1 downto 0) :=
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conv_std_logic_vector(PADJ_3_I,DIV_WIDTH);
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conv_std_logic_vector(PADJ_3_I,DIV_WIDTH);
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constant PADJ_4 : std_logic_vector(DIV_WIDTH-1 downto 0) :=
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constant PADJ_4 : std_logic_vector(DIV_WIDTH-1 downto 0) :=
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conv_std_logic_vector(PADJ_4_I,DIV_WIDTH);
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conv_std_logic_vector(PADJ_4_I,DIV_WIDTH);
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constant PADJ_5 : std_logic_vector(DIV_WIDTH-1 downto 0) :=
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constant PADJ_5 : std_logic_vector(DIV_WIDTH-1 downto 0) :=
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conv_std_logic_vector(PADJ_5_I,DIV_WIDTH);
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conv_std_logic_vector(PADJ_5_I,DIV_WIDTH);
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constant PADJ_6 : std_logic_vector(DIV_WIDTH-1 downto 0) :=
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constant PADJ_6 : std_logic_vector(DIV_WIDTH-1 downto 0) :=
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conv_std_logic_vector(PADJ_6_I,DIV_WIDTH);
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conv_std_logic_vector(PADJ_6_I,DIV_WIDTH);
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signal DACin_q : std_logic_vector(DAC_Width-1 downto 0);
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signal DACin_q : std_logic_vector(DAC_Width-1 downto 0);
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signal Divisor : std_logic_vector(DIV_WIDTH-1 downto 0);
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signal Divisor : std_logic_vector(DIV_WIDTH-1 downto 0);
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signal Dividend : std_logic_vector(DIV_WIDTH-1 downto 0);
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signal Dividend : std_logic_vector(DIV_WIDTH-1 downto 0);
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signal q : std_logic_vector(DIV_WIDTH*2-1 downto 0);
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signal q : std_logic_vector(DIV_WIDTH*2-1 downto 0);
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signal diff : std_logic_vector(DIV_WIDTH downto 0);
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signal diff : std_logic_vector(DIV_WIDTH downto 0);
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constant CB : integer := ceil_log2(DIV_WIDTH);
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constant CB : integer := ceil_log2(DIV_WIDTH);
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signal count : std_logic_vector(CB-1 downto 0);
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signal count : std_logic_vector(CB-1 downto 0);
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signal Next_Width : std_logic_vector(DAC_Width-1 downto 0);
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signal Next_Width : std_logic_vector(DAC_Width-1 downto 0);
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signal Next_Period : std_logic_vector(DAC_Width-1 downto 0);
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signal Next_Period : std_logic_vector(DAC_Width-1 downto 0);
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signal PWM_Width : std_logic_vector(DAC_Width-1 downto 0);
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signal PWM_Width : std_logic_vector(DAC_Width-1 downto 0);
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signal PWM_Period : std_logic_vector(DAC_Width-1 downto 0);
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signal PWM_Period : std_logic_vector(DAC_Width-1 downto 0);
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signal Width_Ctr : std_logic_vector(DAC_Width-1 downto 0);
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signal Width_Ctr : std_logic_vector(DAC_Width-1 downto 0);
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signal Period_Ctr : std_logic_vector(DAC_Width-1 downto 0);
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signal Period_Ctr : std_logic_vector(DAC_Width-1 downto 0);
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begin
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begin
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diff <= ('0' & q(DIV_WIDTH*2-2 downto DIV_WIDTH-1)) -
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diff <= ('0' & q(DIV_WIDTH*2-2 downto DIV_WIDTH-1)) -
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('0' & Divisor);
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('0' & Divisor);
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Dividend <= PADJ_2 when DACin_q >= DELTA_2_I and DACin_q < DELTA_3_I else
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Dividend <= PADJ_2 when DACin_q >= DELTA_2_I and DACin_q < DELTA_3_I else
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PADJ_3 when DACin_q >= DELTA_3_I and DACin_q < DELTA_4_I else
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PADJ_3 when DACin_q >= DELTA_3_I and DACin_q < DELTA_4_I else
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PADJ_4 when DACin_q >= DELTA_4_I and DACin_q < DELTA_5_I else
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PADJ_4 when DACin_q >= DELTA_4_I and DACin_q < DELTA_5_I else
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PADJ_5 when DACin_q >= DELTA_5_I and DACin_q < DELTA_6_I else
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PADJ_5 when DACin_q >= DELTA_5_I and DACin_q < DELTA_6_I else
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PADJ_6 when DACin_q >= DELTA_6_I else
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PADJ_6 when DACin_q >= DELTA_6_I else
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PADJ_1;
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PADJ_1;
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Next_Width <= DELTA_1 when DACin_q >= DELTA_1_I and DACin_q < DELTA_2_I else
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Next_Width <= DELTA_1 when DACin_q >= DELTA_1_I and DACin_q < DELTA_2_I else
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DELTA_2 when DACin_q >= DELTA_2_I and DACin_q < DELTA_3_I else
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DELTA_2 when DACin_q >= DELTA_2_I and DACin_q < DELTA_3_I else
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DELTA_3 when DACin_q >= DELTA_3_I and DACin_q < DELTA_4_I else
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DELTA_3 when DACin_q >= DELTA_3_I and DACin_q < DELTA_4_I else
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DELTA_4 when DACin_q >= DELTA_4_I and DACin_q < DELTA_5_I else
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DELTA_4 when DACin_q >= DELTA_4_I and DACin_q < DELTA_5_I else
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DELTA_5 when DACin_q >= DELTA_5_I and DACin_q < DELTA_6_I else
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DELTA_5 when DACin_q >= DELTA_5_I and DACin_q < DELTA_6_I else
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DELTA_6 when DACin_q >= DELTA_6_I else
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DELTA_6 when DACin_q >= DELTA_6_I else
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(others => '0');
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(others => '0');
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Next_Period <= q(7 downto 0) - 1;
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Next_Period <= q(7 downto 0) - 1;
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vDSM_proc: process( Clock, Reset )
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vDSM_proc: process( Clock, Reset )
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begin
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begin
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if( Reset = Reset_Level )then
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if( Reset = Reset_Level )then
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q <= (others => '0');
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q <= (others => '0');
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count <= (others => '1');
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count <= (others => '1');
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Divisor <= (others => '0');
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Divisor <= (others => '0');
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DACin_q <= (others => '0');
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DACin_q <= (others => '0');
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PWM_Width <= (others => '0');
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PWM_Width <= (others => '0');
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PWM_Period <= (others => '0');
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PWM_Period <= (others => '0');
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Period_Ctr <= (others => '0');
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Period_Ctr <= (others => '0');
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Width_Ctr <= (others => '0');
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Width_Ctr <= (others => '0');
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DACout <= '0';
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DACout <= '0';
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elsif( rising_edge(Clock) )then
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elsif( rising_edge(Clock) )then
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q <= diff(DIV_WIDTH-1 downto 0) &
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q <= diff(DIV_WIDTH-1 downto 0) &
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q(DIV_WIDTH-2 downto 0) & '1';
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q(DIV_WIDTH-2 downto 0) & '1';
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if( diff(DIV_WIDTH) = '1' )then
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if( diff(DIV_WIDTH) = '1' )then
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q <= q(DIV_WIDTH*2-2 downto 0) & '0';
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q <= q(DIV_WIDTH*2-2 downto 0) & '0';
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end if;
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end if;
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count <= count + 1;
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count <= count + 1;
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if( count = DIV_WIDTH )then
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if( count = DIV_WIDTH )then
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PWM_Width <= Next_Width;
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PWM_Width <= Next_Width;
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PWM_Period <= Next_Period;
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PWM_Period <= Next_Period;
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DACin_q <= DACin;
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DACin_q <= DACin;
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Divisor <= (others => '0');
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Divisor <= (others => '0');
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Divisor(DAC_Width-1 downto 0) <= DACin_q;
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Divisor(DAC_Width-1 downto 0) <= DACin_q;
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q <= conv_std_logic_vector(0,DIV_WIDTH) & Dividend;
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q <= conv_std_logic_vector(0,DIV_WIDTH) & Dividend;
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count <= (others => '0');
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count <= (others => '0');
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end if;
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end if;
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Period_Ctr <= Period_Ctr - 1;
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Period_Ctr <= Period_Ctr - 1;
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Width_Ctr <= Width_Ctr - 1;
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Width_Ctr <= Width_Ctr - 1;
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DACout <= '1';
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DACout <= '1';
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if( Width_Ctr = 0 )then
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if( Width_Ctr = 0 )then
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DACout <= '0';
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DACout <= '0';
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Width_Ctr <= (others => '0');
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Width_Ctr <= (others => '0');
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end if;
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end if;
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if( Period_Ctr = 0 )then
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if( Period_Ctr = 0 )then
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Period_Ctr <= PWM_Period;
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Period_Ctr <= PWM_Period;
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Width_Ctr <= PWM_Width;
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Width_Ctr <= PWM_Width;
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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end architecture;
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end architecture;
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