-- Copyright (c)2020 Jeremy Seth Henry
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-- Copyright (c)2020 Jeremy Seth Henry
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-- All rights reserved.
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-- All rights reserved.
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--
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--
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-- Redistribution and use in source and binary forms, with or without
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-- Redistribution and use in source and binary forms, with or without
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-- modification, are permitted provided that the following conditions are met:
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-- modification, are permitted provided that the following conditions are met:
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-- * Redistributions of source code must retain the above copyright
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-- * Redistributions of source code must retain the above copyright
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-- notice, this list of conditions and the following disclaimer.
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-- notice, this list of conditions and the following disclaimer.
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-- * Redistributions in binary form must reproduce the above copyright
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-- * Redistributions in binary form must reproduce the above copyright
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-- notice, this list of conditions and the following disclaimer in the
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-- notice, this list of conditions and the following disclaimer in the
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-- documentation and/or other materials provided with the distribution,
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-- documentation and/or other materials provided with the distribution,
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-- where applicable (as part of a user interface, debugging port, etc.)
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-- where applicable (as part of a user interface, debugging port, etc.)
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--
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--
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-- THIS SOFTWARE IS PROVIDED BY JEREMY SETH HENRY ``AS IS'' AND ANY
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-- THIS SOFTWARE IS PROVIDED BY JEREMY SETH HENRY ``AS IS'' AND ANY
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-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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-- DISCLAIMED. IN NO EVENT SHALL JEREMY SETH HENRY BE LIABLE FOR ANY
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-- DISCLAIMED. IN NO EVENT SHALL JEREMY SETH HENRY BE LIABLE FOR ANY
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-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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--
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--
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-- VHDL Entity: vector_tx
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-- VHDL Entity: vector_tx
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-- Description: Reads the pushbuttons and switches on the DE1-SOC board and
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-- Description: Reads the pushbuttons and switches on the DE1-SOC board and
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-- sends a vector command and argument to a vector_rx receiver
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-- sends a vector command and argument to a vector_rx receiver
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-- which executes them in lieu of a parallel controller.
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-- which executes them in lieu of a parallel controller.
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--
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--
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-- Revision History
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-- Revision History
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-- Author Date Change
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-- Author Date Change
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------------------ -------- ---------------------------------------------------
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------------------ -------- ---------------------------------------------------
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-- Seth Henry 05/06/20 Added version block
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-- Seth Henry 05/06/20 Added version block
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_misc.all;
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use ieee.std_logic_misc.all;
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entity vector_tx is
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entity vector_tx is
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generic(
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generic(
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Button_Level : std_logic;
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Button_Level : std_logic;
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Bit_Rate : real;
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Bit_Rate : real;
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Enable_Parity : boolean;
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Enable_Parity : boolean;
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Parity_Odd_Even_n : std_logic;
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Parity_Odd_Even_n : std_logic;
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Sys_Freq : real;
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Sys_Freq : real;
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Reset_Level : std_logic
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Reset_Level : std_logic
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);
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);
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port(
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port(
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Clock : in std_logic;
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Clock : in std_logic;
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Reset : in std_logic;
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Reset : in std_logic;
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--
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--
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Switches : in std_logic_vector(9 downto 0);
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Switches : in std_logic_vector(9 downto 0);
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Pushbutton : in std_logic;
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Pushbutton : in std_logic;
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--
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--
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Tx_Out : out std_logic
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Tx_Out : out std_logic
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);
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);
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end entity;
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end entity;
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architecture behave of vector_tx is
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architecture behave of vector_tx is
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signal uSec_Tick : std_logic;
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signal uSec_Tick : std_logic;
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signal mSec_Tick : std_logic;
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signal mSec_Tick : std_logic;
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signal Button_Pressed : std_logic := '0';
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signal Button_Pressed : std_logic := '0';
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signal Button_CoS : std_logic := '0';
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signal Button_CoS : std_logic := '0';
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type VEC_ARG_TYPE is array(0 to 15) of std_logic_vector(15 downto 0);
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type VEC_ARG_TYPE is array(0 to 31) of std_logic_vector(15 downto 0);
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constant VEC_ARGS : VEC_ARG_TYPE := (
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constant VEC_ARGS : VEC_ARG_TYPE := (
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x"0000",
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x"0000",
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x"1111",
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x"0001",
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x"2222",
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x"0002",
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x"3333",
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x"0003",
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x"4444",
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x"0004",
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x"5555",
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x"0005",
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x"6666",
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x"0006",
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x"7777",
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x"0007",
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x"8888",
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x"0008",
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x"9999",
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x"0009",
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x"AAAA",
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x"000A",
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x"BBBB",
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x"000B",
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x"CCCC",
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x"000C",
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x"DDDD",
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x"000D",
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x"EEEE",
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x"000E",
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x"000F",
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x"0800",
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x"0866",
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x"0975",
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x"00AE",
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x"DEAD",
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x"BEEF",
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x"CAFE",
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x"BABE",
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x"DECA",
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x"A5A5",
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x"C3C3",
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x"0123",
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x"4567",
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x"89AB",
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x"CDEF",
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x"FFFF"
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x"FFFF"
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);
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);
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alias Vector_Arg_Sel is Switches(9 downto 6);
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alias Vector_Arg_Sel is Switches(9 downto 5);
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alias Vector_Cmd_Sel is Switches(5 downto 0);
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alias Vector_Cmd_Sel is Switches(4 downto 0);
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signal Vector_Cmd : std_logic_vector(7 downto 0);
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signal Vector_Cmd : std_logic_vector(7 downto 0);
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signal Vector_Arg : std_logic_vector(15 downto 0);
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signal Vector_Arg : std_logic_vector(15 downto 0);
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alias Vector_Arg_LB is Vector_Arg(7 downto 0);
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alias Vector_Arg_LB is Vector_Arg(7 downto 0);
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alias Vector_Arg_UB is Vector_Arg(15 downto 8);
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alias Vector_Arg_UB is Vector_Arg(15 downto 8);
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type VECTOR_TX_STATES is (IDLE, SEND_CMD, WAIT_CMD, SEND_ARG_LB, WAIT_ARG_LB, SEND_ARG_UB, WAIT_ARG_UB );
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type VECTOR_TX_STATES is (IDLE, SEND_CMD, WAIT_CMD, SEND_ARG_LB, WAIT_ARG_LB, SEND_ARG_UB, WAIT_ARG_UB );
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signal Vector_State : VECTOR_TX_STATES := IDLE;
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signal Vector_State : VECTOR_TX_STATES := IDLE;
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constant BAUD_RATE_DIV : integer := integer(Sys_Freq / Bit_Rate);
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constant BAUD_RATE_DIV : integer := integer(Sys_Freq / Bit_Rate);
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signal Tx_Data : std_logic_vector(7 downto 0) := x"00";
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signal Tx_Data : std_logic_vector(7 downto 0) := x"00";
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signal Tx_Valid : std_logic := '0';
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signal Tx_Valid : std_logic := '0';
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signal Tx_Done : std_logic := '0';
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signal Tx_Done : std_logic := '0';
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begin
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begin
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U_USEC : entity work.sys_tick
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U_USEC : entity work.sys_tick
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generic map(
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generic map(
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Reset_Level => Reset_Level,
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Reset_Level => Reset_Level,
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Sys_Freq => Sys_Freq
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Sys_Freq => Sys_Freq
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)
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)
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port map(
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port map(
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Clock => Clock,
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Clock => Clock,
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Reset => Reset,
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Reset => Reset,
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uSec_Tick => uSec_Tick,
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uSec_Tick => uSec_Tick,
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mSec_Tick => mSec_Tick
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mSec_Tick => mSec_Tick
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);
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);
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U_BTN : entity work.button_db
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U_BTN : entity work.button_db
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generic map(
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generic map(
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Button_Level => Button_Level,
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Button_Level => Button_Level,
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Reset_Level => Reset_Level
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Reset_Level => Reset_Level
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)
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)
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port map(
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port map(
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Clock => Clock,
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Clock => Clock,
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Reset => Reset,
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Reset => Reset,
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mSec_Tick => mSec_Tick,
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mSec_Tick => mSec_Tick,
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--
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--
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Button_In => Pushbutton,
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Button_In => Pushbutton,
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--
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--
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Button_Pressed => Button_Pressed,
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Button_Pressed => Button_Pressed,
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Button_CoS => Button_CoS
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Button_CoS => Button_CoS
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);
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);
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Input_reg_proc: process( Clock, Reset )
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Input_reg_proc: process( Clock, Reset )
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begin
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begin
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if( Reset = Reset_Level )then
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if( Reset = Reset_Level )then
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Vector_Cmd <= x"00";
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Vector_Cmd <= x"00";
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Vector_Arg <= x"0000";
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Vector_Arg <= x"0000";
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elsif( rising_edge(Clock) )then
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elsif( rising_edge(Clock) )then
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Vector_Cmd <= "00" & Vector_Cmd_Sel;
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Vector_Cmd <= "000" & Vector_Cmd_Sel;
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Vector_Arg <= VEC_ARGS(conv_integer(Vector_Arg_Sel));
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Vector_Arg <= VEC_ARGS(conv_integer(Vector_Arg_Sel));
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end if;
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end if;
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end process;
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end process;
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TX_FSM_proc: process( Clock, Reset )
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TX_FSM_proc: process( Clock, Reset )
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begin
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begin
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if( Reset = Reset_Level )then
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if( Reset = Reset_Level )then
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Vector_State <= IDLE;
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Vector_State <= IDLE;
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Tx_Data <= x"00";
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Tx_Data <= x"00";
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Tx_Valid <= '0';
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Tx_Valid <= '0';
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elsif( rising_edge(Clock) )then
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elsif( rising_edge(Clock) )then
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Tx_Data <= x"00";
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Tx_Data <= x"00";
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Tx_Valid <= '0';
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Tx_Valid <= '0';
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case( Vector_State )is
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case( Vector_State )is
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when IDLE =>
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when IDLE =>
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if( Button_CoS = '1' and Button_Pressed = '1' )then
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if( Button_CoS = '1' and Button_Pressed = '1' )then
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Vector_State <= SEND_CMD;
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Vector_State <= SEND_CMD;
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end if;
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end if;
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when SEND_CMD =>
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when SEND_CMD =>
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Tx_Data <= Vector_Cmd;
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Tx_Data <= Vector_Cmd;
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Tx_Valid <= '1';
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Tx_Valid <= '1';
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Vector_State <= WAIT_CMD;
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Vector_State <= WAIT_CMD;
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when WAIT_CMD =>
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when WAIT_CMD =>
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if( Tx_Done = '1' )then
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if( Tx_Done = '1' )then
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Vector_State <= SEND_ARG_LB;
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Vector_State <= SEND_ARG_LB;
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end if;
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end if;
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when SEND_ARG_LB =>
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when SEND_ARG_LB =>
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Tx_Data <= Vector_Arg_LB;
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Tx_Data <= Vector_Arg_LB;
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Tx_Valid <= '1';
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Tx_Valid <= '1';
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Vector_State <= WAIT_ARG_LB;
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Vector_State <= WAIT_ARG_LB;
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when WAIT_ARG_LB =>
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when WAIT_ARG_LB =>
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if( Tx_Done = '1' )then
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if( Tx_Done = '1' )then
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Vector_State <= SEND_ARG_UB;
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Vector_State <= SEND_ARG_UB;
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end if;
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end if;
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when SEND_ARG_UB =>
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when SEND_ARG_UB =>
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Tx_Data <= Vector_Arg_UB;
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Tx_Data <= Vector_Arg_UB;
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Tx_Valid <= '1';
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Tx_Valid <= '1';
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Vector_State <= WAIT_ARG_UB;
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Vector_State <= WAIT_ARG_UB;
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when WAIT_ARG_UB =>
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when WAIT_ARG_UB =>
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if( Tx_Done = '1' )then
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if( Tx_Done = '1' )then
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Vector_State <= IDLE;
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Vector_State <= IDLE;
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end if;
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end if;
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end case;
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end case;
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end if;
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end if;
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end process;
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end process;
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U_TX : entity work.async_ser_tx
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U_TX : entity work.async_ser_tx
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generic map(
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generic map(
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Reset_Level => Reset_Level,
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Reset_Level => Reset_Level,
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Enable_Parity => Enable_Parity,
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Enable_Parity => Enable_Parity,
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Parity_Odd_Even_n => Parity_Odd_Even_n,
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Parity_Odd_Even_n => Parity_Odd_Even_n,
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Clock_Divider => BAUD_RATE_DIV
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Clock_Divider => BAUD_RATE_DIV
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)
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)
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port map(
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port map(
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Clock => Clock,
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Clock => Clock,
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Reset => Reset,
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Reset => Reset,
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--
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--
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Tx_Data => Tx_Data,
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Tx_Data => Tx_Data,
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Tx_Valid => Tx_Valid,
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Tx_Valid => Tx_Valid,
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--
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--
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Tx_Out => Tx_Out,
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Tx_Out => Tx_Out,
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Tx_Done => Tx_Done
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Tx_Done => Tx_Done
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);
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);
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