-- Copyright (c)2020 Jeremy Seth Henry
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-- Copyright (c)2021 Jeremy Seth Henry
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-- All rights reserved.
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-- All rights reserved.
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--
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--
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-- Redistribution and use in source and binary forms, with or without
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-- Redistribution and use in source and binary forms, with or without
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-- modification, are permitted provided that the following conditions are met:
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-- modification, are permitted provided that the following conditions are met:
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-- * Redistributions of source code must retain the above copyright
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-- * Redistributions of source code must retain the above copyright
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-- notice, this list of conditions and the following disclaimer.
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-- notice, this list of conditions and the following disclaimer.
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-- * Redistributions in binary form must reproduce the above copyright
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-- * Redistributions in binary form must reproduce the above copyright
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-- notice, this list of conditions and the following disclaimer in the
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-- notice, this list of conditions and the following disclaimer in the
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-- documentation and/or other materials provided with the distribution,
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-- documentation and/or other materials provided with the distribution,
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-- where applicable (as part of a user interface, debugging port, etc.)
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-- where applicable (as part of a user interface, debugging port, etc.)
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--
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--
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-- THIS SOFTWARE IS PROVIDED BY JEREMY SETH HENRY ``AS IS'' AND ANY
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-- THIS SOFTWARE IS PROVIDED BY JEREMY SETH HENRY ``AS IS'' AND ANY
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-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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-- DISCLAIMED. IN NO EVENT SHALL JEREMY SETH HENRY BE LIABLE FOR ANY
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-- DISCLAIMED. IN NO EVENT SHALL JEREMY SETH HENRY BE LIABLE FOR ANY
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-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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--
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--
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-- VHDL Entity: vector_tx
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-- VHDL Entity: vector_tx
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-- Description: Reads the pushbuttons and switches on the DE1-SOC board and
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-- Description: Reads the pushbuttons and switches on the DE1-SOC board and
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-- sends a vector command and argument to a vector_rx receiver
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-- sends a vector command and argument to a vector_rx receiver
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-- which executes them in lieu of a parallel controller.
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-- which executes them in lieu of a parallel controller.
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--
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--
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-- Revision History
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-- Revision History
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-- Author Date Change
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-- Author Date Change
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------------------ -------- ---------------------------------------------------
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------------------ -------- ---------------------------------------------------
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-- Seth Henry 05/06/20 Added version block
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-- Seth Henry 05/06/20 Added version block
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-- Seth Henry 04/07/21 Modified to replace hard-coded blocks with true
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-- Seth Henry 04/07/21 Modified to replace hard-coded blocks with true
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-- argument inputs.
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-- argument inputs.
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-- Seth Henry 09/15/21 Added flow control and made the Magic_Num a generic
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_misc.all;
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use ieee.std_logic_misc.all;
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library work;
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library work;
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use work.open8_pkg.all;
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use work.open8_pkg.all;
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entity vector_tx is
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entity vector_tx is
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generic(
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generic(
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Button_Level : std_logic;
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Magic_Num : DATA_TYPE := x"4D";
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Bit_Rate : real;
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Bit_Rate : real;
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Enable_Parity : boolean;
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Enable_Parity : boolean;
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Parity_Odd_Even_n : std_logic;
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Parity_Odd_Even_n : std_logic;
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Sys_Freq : real;
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Clock_Frequency : real;
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Reset_Level : std_logic
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Reset_Level : std_logic
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);
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);
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port(
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port(
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Clock : in std_logic;
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Clock : in std_logic;
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Reset : in std_logic;
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Reset : in std_logic;
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--
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--
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Tx_Enable : in std_logic;
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Tx_Enable : in std_logic;
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Tx_Command : in DATA_TYPE;
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Tx_Command : in DATA_TYPE;
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Tx_Arg_Lower : in DATA_TYPE;
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Tx_Arg_Lower : in DATA_TYPE;
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Tx_Arg_Upper : in DATA_TYPE;
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Tx_Arg_Upper : in DATA_TYPE;
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--
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--
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Tx_Busy : out std_logic;
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Tx_Busy : out std_logic;
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--
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--
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Tx_Out : out std_logic;
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Tx_Out : out std_logic;
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Tx_FC : in std_logic := '1'
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Tx_FC : in std_logic := '1'
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);
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);
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end entity;
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end entity;
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architecture behave of vector_tx is
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architecture behave of vector_tx is
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signal Command_Buffer : DATA_TYPE := x"00";
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signal Command_Buffer : DATA_TYPE := x"00";
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signal Arg_Lower_Buffer : DATA_TYPE := x"00";
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signal Arg_Lower_Buffer : DATA_TYPE := x"00";
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signal Arg_Upper_Buffer : DATA_TYPE := x"00";
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signal Arg_Upper_Buffer : DATA_TYPE := x"00";
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type VECTOR_TX_STATES is (IDLE,
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type VECTOR_TX_STATES is (IDLE, WAIT_FC,
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SEND_CMD, WAIT_CMD,
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SEND_CMD, WAIT_CMD,
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SEND_ARG_LB, WAIT_ARG_LB,
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SEND_ARG_LB, WAIT_ARG_LB,
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SEND_ARG_UB, WAIT_ARG_UB,
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SEND_ARG_UB, WAIT_ARG_UB,
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SEND_SUM, WAIT_SUM );
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SEND_SUM_LB, WAIT_SUM_LB,
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SEND_SUM_UB, WAIT_SUM_UB );
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signal Vector_State : VECTOR_TX_STATES := IDLE;
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signal Vector_State : VECTOR_TX_STATES := IDLE;
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constant BAUD_RATE_DIV : integer := integer(Sys_Freq / Bit_Rate);
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constant BAUD_RATE_DIV : integer := integer(Clock_Frequency / Bit_Rate);
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constant MAGIC_NUM : DATA_TYPE := x"4D";
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signal Checksum : ADDRESS_TYPE := x"0000";
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signal Checksum : DATA_TYPE := x"00";
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alias Checksum_LB is Checksum(7 downto 0);
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alias Checksum_UB is Checksum(15 downto 8);
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signal Tx_Data : DATA_TYPE := x"00";
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signal Tx_Data : DATA_TYPE := x"00";
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signal Tx_Valid : std_logic := '0';
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signal Tx_Valid : std_logic := '0';
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signal Tx_Done : std_logic := '0';
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signal Tx_Done : std_logic := '0';
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begin
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begin
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TX_FSM_proc: process( Clock, Reset )
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TX_FSM_proc: process( Clock, Reset )
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begin
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begin
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if( Reset = Reset_Level )then
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if( Reset = Reset_Level )then
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Vector_State <= IDLE;
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Vector_State <= IDLE;
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Command_Buffer <= x"00";
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Command_Buffer <= x"00";
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Arg_Lower_Buffer <= x"00";
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Arg_Lower_Buffer <= x"00";
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Arg_Upper_Buffer <= x"00";
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Arg_Upper_Buffer <= x"00";
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Tx_Busy <= '0';
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Tx_Busy <= '0';
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Tx_Data <= x"00";
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Tx_Data <= x"00";
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Tx_Valid <= '0';
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Tx_Valid <= '0';
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elsif( rising_edge(Clock) )then
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elsif( rising_edge(Clock) )then
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Tx_Busy <= '1';
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Tx_Busy <= '1';
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Tx_Data <= x"00";
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Tx_Data <= x"00";
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Tx_Valid <= '0';
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Tx_Valid <= '0';
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case( Vector_State )is
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case( Vector_State )is
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when IDLE =>
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when IDLE =>
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Tx_Busy <= '0';
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Tx_Busy <= '0';
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Checksum <= MAGIC_NUM;
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Checksum <= x"00" & MAGIC_NUM;
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if( Tx_Enable = '1' )then
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if( Tx_Enable = '1' )then
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Command_Buffer <= Tx_Command;
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Command_Buffer <= Tx_Command;
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Arg_Lower_Buffer <= Tx_Arg_Lower;
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Arg_Lower_Buffer <= Tx_Arg_Lower;
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Arg_Upper_Buffer <= Tx_Arg_Upper;
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Arg_Upper_Buffer <= Tx_Arg_Upper;
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Vector_State <= WAIT_FC;
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end if;
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when WAIT_FC =>
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if( Tx_FC = '1' )then
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Vector_State <= SEND_CMD;
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Vector_State <= SEND_CMD;
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end if;
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end if;
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when SEND_CMD =>
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when SEND_CMD =>
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Tx_Data <= Command_Buffer;
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Tx_Data <= Command_Buffer;
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Tx_Valid <= '1';
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Tx_Valid <= '1';
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Checksum <= Checksum + Command_Buffer;
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Checksum <= Checksum + Command_Buffer;
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Vector_State <= WAIT_CMD;
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Vector_State <= WAIT_CMD;
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when WAIT_CMD =>
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when WAIT_CMD =>
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if( Tx_Done = '1' )then
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if( Tx_Done = '1' )then
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Vector_State <= SEND_ARG_LB;
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Vector_State <= SEND_ARG_LB;
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end if;
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end if;
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when SEND_ARG_LB =>
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when SEND_ARG_LB =>
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Tx_Data <= Arg_Lower_Buffer;
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Tx_Data <= Arg_Lower_Buffer;
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Tx_Valid <= '1';
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Tx_Valid <= '1';
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Checksum <= Checksum + Arg_Lower_Buffer;
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Checksum <= Checksum + Arg_Lower_Buffer;
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Vector_State <= WAIT_ARG_LB;
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Vector_State <= WAIT_ARG_LB;
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when WAIT_ARG_LB =>
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when WAIT_ARG_LB =>
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if( Tx_Done = '1' )then
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if( Tx_Done = '1' )then
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Vector_State <= SEND_ARG_UB;
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Vector_State <= SEND_ARG_UB;
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end if;
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end if;
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when SEND_ARG_UB =>
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when SEND_ARG_UB =>
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Tx_Data <= Arg_Upper_Buffer;
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Tx_Data <= Arg_Upper_Buffer;
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Tx_Valid <= '1';
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Tx_Valid <= '1';
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Checksum <= Checksum + Arg_Upper_Buffer;
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Checksum <= Checksum + Arg_Upper_Buffer;
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Vector_State <= WAIT_ARG_UB;
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Vector_State <= WAIT_ARG_UB;
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when WAIT_ARG_UB =>
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when WAIT_ARG_UB =>
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if( Tx_Done = '1' )then
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if( Tx_Done = '1' )then
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Vector_State <= SEND_SUM;
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Vector_State <= SEND_SUM_LB;
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end if;
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when SEND_SUM_LB =>
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Tx_Data <= Checksum_LB;
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Tx_Valid <= '1';
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Vector_State <= WAIT_SUM_LB;
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when WAIT_SUM_LB =>
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if( Tx_Done = '1' )then
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Vector_State <= SEND_SUM_UB;
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end if;
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end if;
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when SEND_SUM =>
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when SEND_SUM_UB =>
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Tx_Data <= Checksum;
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Tx_Data <= Checksum_UB;
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Tx_Valid <= '1';
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Tx_Valid <= '1';
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Vector_State <= WAIT_SUM;
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Vector_State <= WAIT_SUM_UB;
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when WAIT_SUM =>
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when WAIT_SUM_UB =>
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if( Tx_Done = '1' )then
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if( Tx_Done = '1' )then
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Vector_State <= IDLE;
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Vector_State <= IDLE;
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end if;
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end if;
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end case;
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end case;
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end if;
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end if;
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end process;
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end process;
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U_TX : entity work.async_ser_tx
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U_TX : entity work.async_ser_tx
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generic map(
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generic map(
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Reset_Level => Reset_Level,
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Reset_Level => Reset_Level,
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Enable_Parity => Enable_Parity,
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Enable_Parity => Enable_Parity,
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Parity_Odd_Even_n => Parity_Odd_Even_n,
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Parity_Odd_Even_n => Parity_Odd_Even_n,
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Clock_Divider => BAUD_RATE_DIV
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Clock_Divider => BAUD_RATE_DIV
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)
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)
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port map(
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port map(
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Clock => Clock,
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Clock => Clock,
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Reset => Reset,
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Reset => Reset,
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--
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--
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Tx_Data => Tx_Data,
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Tx_Data => Tx_Data,
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Tx_Valid => Tx_Valid,
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Tx_Valid => Tx_Valid,
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--
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--
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Tx_Out => Tx_Out,
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Tx_Out => Tx_Out,
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Tx_Done => Tx_Done
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Tx_Done => Tx_Done
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);
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);
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