/* This file defines the interface between the m32c simulator and gdb.
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/* This file defines the interface between the m32c simulator and gdb.
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Copyright (C) 2005, 2007, 2008, 2009, 2010, 2011
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Copyright (C) 2005, 2007-2012 Free Software Foundation, Inc.
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Free Software Foundation, Inc.
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This file is part of GDB.
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This file is part of GDB.
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This program is free software; you can redistribute it and/or modify
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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#ifndef SIM_M32C_H
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#ifndef SIM_M32C_H
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#define SIM_M32C_H
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#define SIM_M32C_H
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enum m32c_sim_reg {
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enum m32c_sim_reg {
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m32c_sim_reg_r0_bank0,
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m32c_sim_reg_r0_bank0,
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m32c_sim_reg_r1_bank0,
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m32c_sim_reg_r1_bank0,
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m32c_sim_reg_r2_bank0,
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m32c_sim_reg_r2_bank0,
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m32c_sim_reg_r3_bank0,
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m32c_sim_reg_r3_bank0,
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m32c_sim_reg_a0_bank0,
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m32c_sim_reg_a0_bank0,
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m32c_sim_reg_a1_bank0,
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m32c_sim_reg_a1_bank0,
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m32c_sim_reg_fb_bank0,
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m32c_sim_reg_fb_bank0,
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m32c_sim_reg_sb_bank0,
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m32c_sim_reg_sb_bank0,
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m32c_sim_reg_r0_bank1,
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m32c_sim_reg_r0_bank1,
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m32c_sim_reg_r1_bank1,
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m32c_sim_reg_r1_bank1,
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m32c_sim_reg_r2_bank1,
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m32c_sim_reg_r2_bank1,
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m32c_sim_reg_r3_bank1,
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m32c_sim_reg_r3_bank1,
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m32c_sim_reg_a0_bank1,
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m32c_sim_reg_a0_bank1,
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m32c_sim_reg_a1_bank1,
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m32c_sim_reg_a1_bank1,
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m32c_sim_reg_fb_bank1,
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m32c_sim_reg_fb_bank1,
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m32c_sim_reg_sb_bank1,
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m32c_sim_reg_sb_bank1,
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m32c_sim_reg_usp,
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m32c_sim_reg_usp,
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m32c_sim_reg_isp,
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m32c_sim_reg_isp,
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m32c_sim_reg_pc,
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m32c_sim_reg_pc,
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m32c_sim_reg_intb,
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m32c_sim_reg_intb,
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m32c_sim_reg_flg,
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m32c_sim_reg_flg,
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m32c_sim_reg_svf,
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m32c_sim_reg_svf,
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m32c_sim_reg_svp,
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m32c_sim_reg_svp,
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m32c_sim_reg_vct,
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m32c_sim_reg_vct,
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m32c_sim_reg_dmd0,
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m32c_sim_reg_dmd0,
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m32c_sim_reg_dmd1,
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m32c_sim_reg_dmd1,
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m32c_sim_reg_dct0,
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m32c_sim_reg_dct0,
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m32c_sim_reg_dct1,
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m32c_sim_reg_dct1,
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m32c_sim_reg_drc0,
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m32c_sim_reg_drc0,
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m32c_sim_reg_drc1,
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m32c_sim_reg_drc1,
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m32c_sim_reg_dma0,
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m32c_sim_reg_dma0,
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m32c_sim_reg_dma1,
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m32c_sim_reg_dma1,
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m32c_sim_reg_dsa0,
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m32c_sim_reg_dsa0,
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m32c_sim_reg_dsa1,
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m32c_sim_reg_dsa1,
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m32c_sim_reg_dra0,
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m32c_sim_reg_dra0,
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m32c_sim_reg_dra1,
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m32c_sim_reg_dra1,
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m32c_sim_reg_num_regs
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m32c_sim_reg_num_regs
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};
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};
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#endif /* SIM_M32C_H */
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#endif /* SIM_M32C_H */
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