module open_free_list #(parameter RAM_W = 128, RAM_E = 0, RAM_S = 64, CNK_S = 128, RAM_TYPE = "MRAM", FL_AEMPTY_LVL=2) (
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module open_free_list #(parameter RAM_W = 128, RAM_E = 0, RAM_S = 64, CNK_S = 128, RAM_TYPE = "MRAM", FL_AEMPTY_LVL=2) (
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input wire reset_n,
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input wire reset_n,
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input wire clk,
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input wire clk,
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// Write side
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// Write side
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output wire [clog2((RAM_S*1024)/CNK_S)-1:0] fl_q,
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output wire [clog2((RAM_S*1024)/CNK_S)-1:0] fl_q,
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output wire fl_aempty,
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output wire fl_aempty,
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output wire fl_empty,
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output wire fl_empty,
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input wire wren,
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input wire wren,
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input wire [RAM_W+RAM_E-1:0] din,
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input wire [RAM_W+RAM_E-1:0] din,
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input wire eop,
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input wire eop,
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// Read side
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// Read side
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input wire [clog2((RAM_S*1024)/CNK_S)-1:0] chunk_num,
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input wire [clog2((RAM_S*1024)/CNK_S)-1:0] chunk_num,
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input wire load_req,
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input wire load_req,
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input wire rel_req,
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input wire rel_req,
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output reg load_rel_ack,
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output reg load_rel_ack,
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input wire rden,
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input wire rden,
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output wire [RAM_W+RAM_E-1:0] dout
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output wire [RAM_W+RAM_E-1:0] dout
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);
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);
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localparam FL_S = (RAM_S*1024)/CNK_S;
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localparam FL_S = (RAM_S*1024)/CNK_S;
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localparam FL_W = clog2(FL_S);
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localparam FL_W = clog2(FL_S);
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localparam FL_ADDR_W = FL_W;
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localparam FL_ADDR_W = FL_W;
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localparam LL_W = FL_W+1;
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localparam LL_W = FL_W+1;
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localparam RAM_ADDR_W = clog2((RAM_S*1024)/(RAM_W/8));
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localparam RAM_ADDR_W = clog2((RAM_S*1024)/(RAM_W/8));
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localparam LINES_IN_CNK = CNK_S/(RAM_W/8);
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localparam LINES_IN_CNK = CNK_S/(RAM_W/8);
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localparam IN_CNK_ADDR_W = clog2(LINES_IN_CNK);
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localparam IN_CNK_ADDR_W = clog2(LINES_IN_CNK);
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wire [RAM_W+RAM_E-1:0] ram_q;
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wire [RAM_W+RAM_E-1:0] ram_q;
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reg [RAM_ADDR_W-1:0] ram_rd_addr;
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reg [RAM_ADDR_W-1:0] ram_rd_addr;
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wire [RAM_ADDR_W-1:0] ram_wr_addr;
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wire [RAM_ADDR_W-1:0] ram_wr_addr;
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reg [RAM_ADDR_W-1:0] ram_wr_addr_lat;
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reg [RAM_ADDR_W-1:0] ram_wr_addr_lat;
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reg wr_eop_while_ll;
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reg wr_eop_while_ll;
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reg [FL_W-1:0] fl_data;
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reg [FL_W-1:0] fl_data;
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wire [FL_ADDR_W-1:0] fl_lvl;
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wire [FL_ADDR_W-1:0] fl_lvl;
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reg fl_rden;
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reg fl_rden;
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reg fl_wren;
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reg fl_wren;
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wire [FL_W:0] ll_data;
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wire [FL_W:0] ll_data;
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wire [FL_W:0] ll_q;
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wire [FL_W:0] ll_q;
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reg [FL_ADDR_W-1:0] ll_rd_addr;
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reg [FL_ADDR_W-1:0] ll_rd_addr;
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wire [FL_ADDR_W-1:0] ll_wr_addr;
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wire [FL_ADDR_W-1:0] ll_wr_addr;
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wire ll_wren;
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wire ll_wren;
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wire ll_eop;
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wire ll_eop;
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reg [FL_ADDR_W-1:0] fl_init_cnt;
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reg [FL_ADDR_W-1:0] fl_init_cnt;
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reg fl_init;
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reg fl_init;
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reg fl_init_r1;
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reg fl_init_r1;
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reg fl_init_r2;
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reg fl_init_r2;
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reg fl_init_r3;
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reg fl_init_r3;
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reg fl_init_wr;
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reg fl_init_wr;
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reg int_sop;
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reg int_sop;
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reg rel_req_from_idle;
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reg rel_req_from_idle;
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wire load_req_p;
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wire load_req_p;
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wire [FL_ADDR_W-1:0] nxt_chunk_ptr;
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wire [FL_ADDR_W-1:0] nxt_chunk_ptr;
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reg [2:0] ns_rd_sm;
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reg [2:0] ns_rd_sm;
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reg [2:0] cs_rd_sm;
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reg [2:0] cs_rd_sm;
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parameter IDLE = 3'd0,
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parameter IDLE = 3'd0,
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PREFETCH = 3'd1,
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PREFETCH = 3'd1,
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RD = 3'd2,
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RD = 3'd2,
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WAIT_REL = 3'd3,
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WAIT_REL = 3'd3,
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REL_DELAY1 = 3'd4,
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REL_DELAY1 = 3'd4,
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REL_DELAY2 = 3'd5,
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REL_DELAY2 = 3'd5,
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REL_WR2FL = 3'd6;
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REL_WR2FL = 3'd6;
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reg sm_rel_ctrl;
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reg sm_rel_ctrl;
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reg sm_rel_wren;
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reg sm_rel_wren;
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reg sm_rel_ctrl_mask;
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reg sm_rel_ctrl_mask_clr;
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reg sm_rel_ctrl_mask_set;
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reg rden_r1;
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reg int_rden;
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reg int_rden;
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reg int_rden_r1;
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reg load_req_r1;
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reg load_req_r1;
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reg [RAM_ADDR_W-1:0] usr_ram_rd_addr_r1;
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reg [RAM_ADDR_W-1:0] usr_ram_rd_addr_r1;
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altsyncram3 ram (
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altsyncram3 ram (
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.data (din),
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.data (din),
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.rd_aclr (~reset_n),
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.rd_aclr (~reset_n),
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.rdaddress (ram_rd_addr),
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.rdaddress (ram_rd_addr),
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.rdclock (clk),
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.rdclock (clk),
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.rdclocken (int_rden | rden),
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.rdclocken (int_rden | rden),
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.wraddress (ram_wr_addr),
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.wraddress (ram_wr_addr),
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.wrclock (clk),
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.wrclock (clk),
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.wrclocken (1'b1),
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.wrclocken (1'b1),
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.wren (wren),
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.wren (wren),
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.q (dout)
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.q (dout)
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);
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);
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defparam
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defparam
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ram.A_WIDTH = RAM_W+RAM_E,
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ram.A_WIDTH = RAM_W+RAM_E,
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ram.A_WIDTHAD = RAM_ADDR_W,
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ram.A_WIDTHAD = RAM_ADDR_W,
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ram.RAM_TYPE = RAM_TYPE,
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ram.RAM_TYPE = RAM_TYPE,
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ram.USE_RDEN = 0;
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ram.USE_RDEN = 0;
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alt_scfifo free_list(
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alt_scfifo free_list(
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.aclr (~reset_n),
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.aclr (~reset_n),
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.clock (clk),
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.clock (clk),
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.data (fl_init_wr ? fl_init_cnt : fl_data),
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.data (fl_init_wr ? fl_init_cnt : fl_data),
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.rdreq (fl_rden),
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.rdreq (fl_rden),
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.sclr (1'b0),
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.sclr (1'b0),
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.wrreq (fl_init_wr | fl_wren),
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.wrreq (fl_init_wr | fl_wren),
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.almost_empty (fl_aempty),
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.almost_empty (fl_aempty),
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.almost_full (),
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.almost_full (),
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.empty (fl_empty),
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.empty (fl_empty),
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.full (),
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.full (),
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.q (fl_q),
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.q (fl_q),
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.usedw (fl_lvl)
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.usedw (fl_lvl)
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);
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);
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defparam
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defparam
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free_list.FIFO_WIDTH = FL_W,
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free_list.FIFO_WIDTH = FL_W,
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free_list.FIFO_DEPTH = FL_ADDR_W,
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free_list.FIFO_DEPTH = FL_ADDR_W,
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free_list.FIFO_TYPE = "M4K",
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free_list.FIFO_TYPE = "M4K",
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free_list.FIFO_SHOW = "ON",
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free_list.FIFO_SHOW = "ON",
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free_list.FIFO_AEMPTY = FL_AEMPTY_LVL;
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free_list.FIFO_AEMPTY = FL_AEMPTY_LVL;
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altsyncram3 link_list(
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altsyncram3 link_list(
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.data (ll_data),
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.data (ll_data),
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.rd_aclr (~reset_n),
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.rd_aclr (~reset_n),
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.rdaddress (sm_rel_ctrl ? nxt_chunk_ptr : ll_rd_addr),
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.rdaddress (sm_rel_ctrl ? nxt_chunk_ptr : ll_rd_addr),
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.rdclock (clk),
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.rdclock (clk),
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.rdclocken (1'b1),
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.rdclocken (1'b1),
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.wraddress (ll_wr_addr),
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.wraddress (ll_wr_addr),
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.wrclock (clk),
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.wrclock (clk),
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.wrclocken (1'b1),
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.wrclocken (1'b1),
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.wren (ll_wren),
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.wren (ll_wren),
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.q (ll_q)
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.q (ll_q)
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);
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);
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defparam
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defparam
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link_list.A_WIDTH = LL_W,
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link_list.A_WIDTH = LL_W,
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link_list.A_WIDTHAD = FL_ADDR_W,
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link_list.A_WIDTHAD = FL_ADDR_W,
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link_list.RAM_TYPE = "M4K",
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link_list.RAM_TYPE = "M4K",
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link_list.USE_RDEN = 0;
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link_list.USE_RDEN = 0;
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// Free list init
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// Free list init
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always @ (posedge clk, negedge reset_n)
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always @ (posedge clk, negedge reset_n)
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begin
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begin
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if (reset_n==1'b0)
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if (reset_n==1'b0)
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begin
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begin
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fl_init_cnt <= {FL_ADDR_W{1'b0}};
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fl_init_cnt <= {FL_ADDR_W{1'b0}};
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fl_init <= 1'b0;
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fl_init <= 1'b0;
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fl_init_r1 <= 1'b0;
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fl_init_r1 <= 1'b0;
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fl_init_r2 <= 1'b0;
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fl_init_r2 <= 1'b0;
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fl_init_r3 <= 1'b0;
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fl_init_r3 <= 1'b0;
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fl_init_wr <= 1'b0;
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fl_init_wr <= 1'b0;
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end
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end
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else
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else
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begin
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begin
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fl_init_cnt <= fl_init_wr ? fl_init_cnt + 1'b1 : {FL_ADDR_W{1'b0}};
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fl_init_cnt <= fl_init_wr ? fl_init_cnt + 1'b1 : {FL_ADDR_W{1'b0}};
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fl_init <= 1'b1;
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fl_init <= 1'b1;
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fl_init_r1 <= fl_init;
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fl_init_r1 <= fl_init;
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fl_init_r2 <= fl_init_r1;
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fl_init_r2 <= fl_init_r1;
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fl_init_r3 <= fl_init_r2;
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fl_init_r3 <= fl_init_r2;
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fl_init_wr <= !fl_init_r3 && fl_init_r2 ? 1'b1 : fl_init_cnt=={FL_ADDR_W{1'b1}} ? 1'b0 : fl_init_wr;
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fl_init_wr <= !fl_init_r3 && fl_init_r2 ? 1'b1 : fl_init_cnt=={FL_ADDR_W{1'b1}} ? 1'b0 : fl_init_wr;
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end
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end
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end
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end
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// Write side
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// Write side
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assign ram_wr_addr = int_sop || (wren && ram_wr_addr_lat[IN_CNK_ADDR_W-1:0]==(LINES_IN_CNK-1)) ? {fl_q, {IN_CNK_ADDR_W{1'b0}}}
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assign ram_wr_addr = int_sop || (wren && ram_wr_addr_lat[IN_CNK_ADDR_W-1:0]==(LINES_IN_CNK-1)) ? {fl_q, {IN_CNK_ADDR_W{1'b0}}}
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: wren ? ram_wr_addr_lat + 1'b1
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: wren ? ram_wr_addr_lat + 1'b1
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: ram_wr_addr_lat;
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: ram_wr_addr_lat;
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assign ll_eop = wren && ram_wr_addr[IN_CNK_ADDR_W-1:0]==0 && eop ? 1'b0 : eop | wr_eop_while_ll;
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assign ll_eop = wren && ram_wr_addr[IN_CNK_ADDR_W-1:0]==0 && eop ? 1'b0 : eop | wr_eop_while_ll;
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assign ll_wr_addr = ram_wr_addr_lat[RAM_ADDR_W-1:IN_CNK_ADDR_W];
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assign ll_wr_addr = ram_wr_addr_lat[RAM_ADDR_W-1:IN_CNK_ADDR_W];
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assign ll_data = {fl_q, ll_eop};
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assign ll_data = {fl_q, ll_eop};
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assign ll_wren = (wren && ((ram_wr_addr[IN_CNK_ADDR_W-1:0]==0) || eop)) || wr_eop_while_ll ? 1'b1 : 1'b0;
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assign ll_wren = (wren && ((ram_wr_addr[IN_CNK_ADDR_W-1:0]==0) || eop)) || wr_eop_while_ll ? 1'b1 : 1'b0;
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always @ (posedge clk, negedge reset_n)
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always @ (posedge clk, negedge reset_n)
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begin
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begin
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if (reset_n==1'b0)
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if (reset_n==1'b0)
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begin
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begin
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fl_rden <= 1'b0;
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fl_rden <= 1'b0;
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int_sop <= 1'b1;
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int_sop <= 1'b1;
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ram_wr_addr_lat <= {RAM_ADDR_W{1'b0}};
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ram_wr_addr_lat <= {RAM_ADDR_W{1'b0}};
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wr_eop_while_ll <= 1'b0;
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wr_eop_while_ll <= 1'b0;
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end
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end
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else
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else
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begin
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begin
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fl_rden <= wren && (ram_wr_addr[IN_CNK_ADDR_W-1:0]==0) ? 1'b1 : 1'b0;
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fl_rden <= wren && (ram_wr_addr[IN_CNK_ADDR_W-1:0]==0) ? 1'b1 : 1'b0;
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int_sop <= wren && eop ? 1'b1 :
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int_sop <= wren && eop ? 1'b1 :
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wren ? 1'b0 :
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wren ? 1'b0 :
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int_sop;
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int_sop;
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ram_wr_addr_lat <= ram_wr_addr;
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ram_wr_addr_lat <= ram_wr_addr;
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wr_eop_while_ll <= wren && ram_wr_addr[IN_CNK_ADDR_W-1:0]==0 && eop ? 1'b1 : 1'b0;
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wr_eop_while_ll <= wren && ram_wr_addr[IN_CNK_ADDR_W-1:0]==0 && eop ? 1'b1 : 1'b0;
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end
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end
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end
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end
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// Read side
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// Read side
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assign load_req_p = ~load_req_r1 & load_req;
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assign load_req_p = ~load_req_r1 & load_req;
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assign nxt_chunk_ptr = ll_q[FL_W:1]; //can be sampled
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assign nxt_chunk_ptr = ll_q[FL_W:1]; //can be sampled
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always @*
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always @*
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begin
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begin
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case(cs_rd_sm)
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case(cs_rd_sm)
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IDLE:
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IDLE:
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ns_rd_sm = fl_init_wr ? IDLE :
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ns_rd_sm = fl_init_wr ? IDLE :
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rel_req ? REL_DELAY1 :
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rel_req ? REL_DELAY1 :
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load_req ? PREFETCH :
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load_req ? PREFETCH :
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IDLE;
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IDLE;
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PREFETCH:
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PREFETCH:
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ns_rd_sm = RD;
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ns_rd_sm = RD;
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RD:
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RD:
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ns_rd_sm = load_req ? PREFETCH :
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ns_rd_sm = load_req ? PREFETCH :
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rden && (usr_ram_rd_addr_r1[IN_CNK_ADDR_W-1:0]==(LINES_IN_CNK-1)) && ll_q[0] ? WAIT_REL : // true if the current chunk is the last chunk and was reached to its end and is released now : REL_WR2FL // true if the current chunk was reached to its end and is released now and is the last one
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rden && (usr_ram_rd_addr_r1[IN_CNK_ADDR_W-1:0]==(LINES_IN_CNK-1)) && ll_q[0] ? WAIT_REL : // true if the current chunk is the last chunk and was reached to its end and is released now : REL_WR2FL // true if the current chunk was reached to its end and is released now and is the last one
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rel_req ? REL_WR2FL :
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rel_req ? REL_WR2FL :
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RD;
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RD;
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WAIT_REL:
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WAIT_REL:
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ns_rd_sm = rel_req ? IDLE : WAIT_REL;
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ns_rd_sm = rel_req ? IDLE : WAIT_REL;
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REL_DELAY1:
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REL_DELAY1:
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ns_rd_sm = REL_DELAY2;
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ns_rd_sm = REL_DELAY2;
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REL_DELAY2:
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REL_DELAY2:
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ns_rd_sm = REL_WR2FL;
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ns_rd_sm = REL_WR2FL;
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REL_WR2FL:
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REL_WR2FL:
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ns_rd_sm = ll_q[0] ? IDLE : REL_DELAY2;
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ns_rd_sm = ll_q[0] ? IDLE : REL_DELAY2;
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endcase
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endcase
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end
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end
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always @*
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always @*
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begin
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begin
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rel_req_from_idle = 1'b0;
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rel_req_from_idle = 1'b0;
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int_rden = 1'b0;
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int_rden = 1'b0;
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load_rel_ack = 1'b0;
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load_rel_ack = 1'b0;
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sm_rel_ctrl_mask_set = 1'b0;
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sm_rel_ctrl_mask_clr = 1'b0;
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sm_rel_ctrl = 1'b1;
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sm_rel_ctrl = 1'b1;
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sm_rel_wren = 1'b0;
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sm_rel_wren = 1'b0;
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case(cs_rd_sm)
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case(cs_rd_sm)
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IDLE:
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IDLE:
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begin
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begin
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rel_req_from_idle = rel_req;
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rel_req_from_idle = rel_req;
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sm_rel_ctrl = rel_req;
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sm_rel_ctrl_mask_set = rel_req;
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sm_rel_ctrl = 1'b0;
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end
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end
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PREFETCH:
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PREFETCH:
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begin
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begin
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int_rden = 1'b1;
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int_rden = 1'b1;
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load_rel_ack = 1'b1;
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load_rel_ack = 1'b1;
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sm_rel_ctrl = 1'b0;
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sm_rel_ctrl = 1'b0;
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end
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end
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RD:
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RD:
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begin
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begin
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sm_rel_ctrl = 1'b0;
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sm_rel_ctrl = 1'b0;
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end
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end
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WAIT_REL:
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WAIT_REL:
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begin
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begin
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load_rel_ack = rel_req;
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load_rel_ack = rel_req;
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end
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end
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REL_DELAY1:
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REL_DELAY1:
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begin
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begin
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sm_rel_ctrl = ~sm_rel_ctrl_mask;
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end
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end
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REL_DELAY2:
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REL_DELAY2:
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begin
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begin
|
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sm_rel_ctrl = ~sm_rel_ctrl_mask;
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end
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end
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REL_WR2FL:
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REL_WR2FL:
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begin
|
begin
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sm_rel_wren = 1'b1;
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sm_rel_wren = 1'b1;
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load_rel_ack = ll_q[0];
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load_rel_ack = ll_q[0];
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sm_rel_ctrl_mask_clr = 1'b1;
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end
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end
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endcase
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endcase
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end
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end
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|
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always @ (posedge clk, negedge reset_n)
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always @ (posedge clk, negedge reset_n)
|
begin
|
begin
|
if (reset_n==1'b0)
|
if (reset_n==1'b0)
|
begin
|
begin
|
cs_rd_sm <= 3'd0;
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cs_rd_sm <= 3'd0;
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rden_r1 <= 1'b0;
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int_rden_r1 <= 1'b0;
|
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load_req_r1 <= 1'b0;
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load_req_r1 <= 1'b0;
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sm_rel_ctrl_mask <= 1'b0;
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ll_rd_addr <= {FL_ADDR_W{1'b0}};
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ll_rd_addr <= {FL_ADDR_W{1'b0}};
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ram_rd_addr <= {RAM_ADDR_W{1'b0}};
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ram_rd_addr <= {RAM_ADDR_W{1'b0}};
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usr_ram_rd_addr_r1 <= {RAM_ADDR_W{1'b0}};
|
usr_ram_rd_addr_r1 <= {RAM_ADDR_W{1'b0}};
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fl_wren <= 1'b0;
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fl_wren <= 1'b0;
|
fl_data <= {FL_W{1'b0}};
|
fl_data <= {FL_W{1'b0}};
|
end
|
end
|
else
|
else
|
begin
|
begin
|
cs_rd_sm <= ns_rd_sm;
|
cs_rd_sm <= ns_rd_sm;
|
rden_r1 <= rden;
|
|
int_rden_r1 <= int_rden;
|
|
load_req_r1 <= load_req;
|
load_req_r1 <= load_req;
|
|
sm_rel_ctrl_mask <= sm_rel_ctrl_mask_set ? 1'b1 :
|
|
sm_rel_ctrl_mask_clr ? 1'b0 :
|
|
sm_rel_ctrl_mask;
|
|
|
ll_rd_addr <= load_req_p || rel_req_from_idle ? chunk_num :
|
ll_rd_addr <= load_req_p || rel_req_from_idle ? chunk_num :
|
sm_rel_wren || ((!sm_rel_ctrl && rden && (usr_ram_rd_addr_r1[IN_CNK_ADDR_W-1:0]==(LINES_IN_CNK-1)))) ? nxt_chunk_ptr :
|
sm_rel_wren || ((!sm_rel_ctrl && rden && (usr_ram_rd_addr_r1[IN_CNK_ADDR_W-1:0]==(LINES_IN_CNK-1)))) ? nxt_chunk_ptr :
|
ll_rd_addr;
|
ll_rd_addr;
|
ram_rd_addr <= load_req_p ? {chunk_num, {IN_CNK_ADDR_W{1'b0}}} :
|
ram_rd_addr <= load_req_p ? {chunk_num, {IN_CNK_ADDR_W{1'b0}}} :
|
rden && (ram_rd_addr[IN_CNK_ADDR_W-1:0]==(LINES_IN_CNK-1)) ? {nxt_chunk_ptr, {IN_CNK_ADDR_W{1'b0}}} :
|
rden && (ram_rd_addr[IN_CNK_ADDR_W-1:0]==(LINES_IN_CNK-1)) ? {nxt_chunk_ptr, {IN_CNK_ADDR_W{1'b0}}} :
|
rden || int_rden ? ram_rd_addr + 1'b1 :
|
rden || int_rden ? ram_rd_addr + 1'b1 :
|
ram_rd_addr;
|
ram_rd_addr;
|
usr_ram_rd_addr_r1 <= !sm_rel_ctrl && (rden || int_rden) ? ram_rd_addr : usr_ram_rd_addr_r1;
|
usr_ram_rd_addr_r1 <= !sm_rel_ctrl && (rden || int_rden) ? ram_rd_addr : usr_ram_rd_addr_r1;
|
fl_wren <= (!sm_rel_ctrl && rden && (usr_ram_rd_addr_r1[IN_CNK_ADDR_W-1:0]==(LINES_IN_CNK-1))) || sm_rel_wren ? 1'b1 : 1'b0;
|
fl_wren <= (!sm_rel_ctrl && rden && (usr_ram_rd_addr_r1[IN_CNK_ADDR_W-1:0]==(LINES_IN_CNK-1))) || sm_rel_wren ? 1'b1 : 1'b0;
|
fl_data <= rel_req_from_idle ? chunk_num :
|
fl_data <= rel_req_from_idle ? chunk_num :
|
sm_rel_wren ? ll_rd_addr :
|
sm_rel_wren ? ll_rd_addr :
|
usr_ram_rd_addr_r1[RAM_ADDR_W-1:IN_CNK_ADDR_W];
|
usr_ram_rd_addr_r1[RAM_ADDR_W-1:IN_CNK_ADDR_W];
|
|
|
end
|
end
|
end
|
end
|
|
|
/********************************************************
|
/********************************************************
|
clog2 - function that returns log2 of a value rounded up
|
clog2 - function that returns log2 of a value rounded up
|
- min return value is 1 (in case of clog2(1)=1)
|
- min return value is 1 (in case of clog2(1)=1)
|
********************************************************/
|
********************************************************/
|
function integer clog2(input integer value);
|
function integer clog2(input integer value);
|
begin
|
begin
|
value = value-1;
|
value = value-1;
|
for (clog2=0; value>0; clog2=clog2+1)
|
for (clog2=0; value>0; clog2=clog2+1)
|
value = value>>1;
|
value = value>>1;
|
if (clog2 == 0)
|
if (clog2 == 0)
|
clog2 = 1;
|
clog2 = 1;
|
end
|
end
|
endfunction
|
endfunction
|
|
|
endmodule
|
endmodule
|
|
|