////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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// Filename: bigadd.v
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// Filename: bigadd.v
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//
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//
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// Project: OpenArty, an entirely open SoC based upon the Arty platform
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// Project: OpenArty, an entirely open SoC based upon the Arty platform
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//
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//
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// Purpose:
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// Purpose:
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//
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//
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// Creator: Dan Gisselquist, Ph.D.
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// Creator: Dan Gisselquist, Ph.D.
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// Gisselquist Technology, LLC
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// Gisselquist Technology, LLC
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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// Copyright (C) 2016, Gisselquist Technology, LLC
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// Copyright (C) 2016, Gisselquist Technology, LLC
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//
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//
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// This program is free software (firmware): you can redistribute it and/or
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of the GNU General Public License as published
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// modify it under the terms of the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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// your option) any later version.
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//
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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// for more details.
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//
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//
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// You should have received a copy of the GNU General Public License along
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// You should have received a copy of the GNU General Public License along
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// with this program. (It's in the $(ROOT)/doc directory, run make with no
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// with this program. (It's in the $(ROOT)/doc directory, run make with no
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// target there if the PDF file isn't present.) If not, see
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// target there if the PDF file isn't present.) If not, see
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// <http://www.gnu.org/licenses/> for a copy.
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// <http://www.gnu.org/licenses/> for a copy.
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//
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//
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// License: GPL, v3, as defined and found on www.gnu.org,
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// License: GPL, v3, as defined and found on www.gnu.org,
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// http://www.gnu.org/licenses/gpl.html
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// http://www.gnu.org/licenses/gpl.html
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//
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//
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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//
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//
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module bigadd(i_clk, i_sync, i_a, i_b, o_r, o_sync);
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module bigadd(i_clk, i_sync, i_a, i_b, o_r, o_sync);
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parameter NCLOCKS = 1;
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input i_clk, i_sync;
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input i_clk, i_sync;
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input [63:0] i_a, i_b;
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input [63:0] i_a, i_b;
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output reg [63:0] o_r;
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output wire [63:0] o_r;
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output reg o_sync;
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output wire o_sync;
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generate
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if (NCLOCKS == 0)
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begin
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assign o_sync= i_sync;
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assign o_r = i_a + i_b;
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end else if (NCLOCKS == 1)
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begin
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reg r_sync;
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reg [63:0] r_out;
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always @(posedge i_clk)
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r_sync <= i_sync;
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always @(posedge i_clk)
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r_out <= i_a+i_b;
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assign o_sync = r_sync;
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assign o_r = r_out;
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end else // if (NCLOCKS == 2)
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begin
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reg r_sync, r_pps;
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reg r_sync, r_pps;
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reg [31:0] r_hi_a, r_hi_b, r_low;
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reg [31:0] r_hi, r_low;
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reg f_sync;
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reg [63:0] f_r;
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initial r_sync = 1'b0;
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initial r_sync = 1'b0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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r_sync <= i_sync;
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r_sync <= i_sync;
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always @(posedge i_clk)
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always @(posedge i_clk)
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{ r_pps, r_low } <= i_a[31:0] + i_b[31:0];
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{ r_pps, r_low } <= i_a[31:0] + i_b[31:0];
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always @(posedge i_clk)
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always @(posedge i_clk)
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r_hi_a <= i_a[63:32];
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r_hi <= i_a[63:32] + i_b[63:32];
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always @(posedge i_clk)
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r_hi_b <= i_b[63:32];
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initial o_sync = 1'b0;
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initial f_sync = 1'b0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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o_sync <= r_sync;
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f_sync <= r_sync;
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always @(posedge i_clk)
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always @(posedge i_clk)
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o_r[31:0] <= r_low;
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f_r[31:0] <= r_low;
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always @(posedge i_clk)
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always @(posedge i_clk)
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o_r[63:32] <= r_hi_a + r_hi_b + { 31'h00, r_pps };
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f_r[63:32] <= r_hi + { 31'h00, r_pps };
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assign o_sync = f_sync;
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assign o_r = f_r;
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end endgenerate
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endmodule
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endmodule
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