////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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// Filename: fasttop.v
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// Filename: fasttop.v
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//
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//
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// Project: OpenArty, an entirely open SoC based upon the Arty platform
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// Project: OpenArty, an entirely open SoC based upon the Arty platform
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//
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//
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// Purpose: This is the top level Verilog file. It is so named as fasttop,
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// Purpose: This is the top level Verilog file. It is so named as fasttop,
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// because my purpose will be to run the Arty at 200MHz, just to
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// because my purpose will be to run the Arty at 200MHz, just to
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// prove that I can get it up to that frequency.
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// prove that I can get it up to that frequency.
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//
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//
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// Creator: Dan Gisselquist, Ph.D.
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// Creator: Dan Gisselquist, Ph.D.
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// Gisselquist Technology, LLC
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// Gisselquist Technology, LLC
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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// Copyright (C) 2015-2016, Gisselquist Technology, LLC
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// Copyright (C) 2015-2016, Gisselquist Technology, LLC
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//
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//
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// This program is free software (firmware): you can redistribute it and/or
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of the GNU General Public License as published
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// modify it under the terms of the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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// your option) any later version.
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//
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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// for more details.
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//
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//
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// You should have received a copy of the GNU General Public License along
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// You should have received a copy of the GNU General Public License along
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// with this program. (It's in the $(ROOT)/doc directory, run make with no
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// with this program. (It's in the $(ROOT)/doc directory, run make with no
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// target there if the PDF file isn't present.) If not, see
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// target there if the PDF file isn't present.) If not, see
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// <http://www.gnu.org/licenses/> for a copy.
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// <http://www.gnu.org/licenses/> for a copy.
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//
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//
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// License: GPL, v3, as defined and found on www.gnu.org,
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// License: GPL, v3, as defined and found on www.gnu.org,
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// http://www.gnu.org/licenses/gpl.html
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// http://www.gnu.org/licenses/gpl.html
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//
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//
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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//
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//
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module fasttop(i_clk_100mhz, i_reset_btn,
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module fasttop(i_clk_100mhz, i_reset_btn,
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i_sw, // Switches
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i_sw, // Switches
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i_btn, // Buttons
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i_btn, // Buttons
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o_led, // Single color LEDs
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o_led, // Single color LEDs
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o_clr_led0, o_clr_led1, o_clr_led2, o_clr_led3, // Color LEDs
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o_clr_led0, o_clr_led1, o_clr_led2, o_clr_led3, // Color LEDs
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// RS232 UART
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// RS232 UART
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i_uart_rx, o_uart_tx,
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i_uart_rx, o_uart_tx,
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// Quad-SPI Flash control
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// Quad-SPI Flash control
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o_qspi_sck, o_qspi_cs_n, io_qspi_dat,
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o_qspi_sck, o_qspi_cs_n, io_qspi_dat,
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// Missing: Ethernet
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// Missing: Ethernet
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o_eth_mdclk, io_eth_mdio,
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o_eth_mdclk, io_eth_mdio,
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// Memory
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// Memory
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o_ddr_reset_n, o_ddr_cke, o_ddr_ck_p, o_ddr_ck_n,
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o_ddr_reset_n, o_ddr_cke, o_ddr_ck_p, o_ddr_ck_n,
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o_ddr_cs_n, o_ddr_ras_n, o_ddr_cas_n, o_ddr_we_n,
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o_ddr_cs_n, o_ddr_ras_n, o_ddr_cas_n, o_ddr_we_n,
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io_ddr_dqs_p, io_ddr_dqs_n,
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io_ddr_dqs_p, io_ddr_dqs_n,
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o_ddr_addr, o_ddr_ba,
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o_ddr_addr, o_ddr_ba,
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io_ddr_data, o_ddr_dm, o_ddr_odt,
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io_ddr_data, o_ddr_dm, o_ddr_odt,
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// SD Card
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// SD Card
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o_sd_sck, io_sd_cmd, io_sd, i_sd_cs, i_sd_wp,
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o_sd_sck, io_sd_cmd, io_sd, i_sd_cs, i_sd_wp,
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// GPS Pmod
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// GPS Pmod
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i_gps_pps, i_gps_3df, i_gps_rx, o_gps_tx,
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i_gps_pps, i_gps_3df, i_gps_rx, o_gps_tx,
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// OLED Pmod
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// OLED Pmod
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o_oled_sck, o_oled_cs_n, o_oled_mosi, o_oled_dcn, o_oled_reset_n,
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o_oled_sck, o_oled_cs_n, o_oled_mosi, o_oled_dcn, o_oled_reset_n,
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o_oled_vccen, o_oled_pmoden,
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o_oled_vccen, o_oled_pmoden,
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// PMod I/O
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// PMod I/O
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i_aux_rx, i_aux_rts, o_aux_tx, o_aux_cts
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i_aux_rx, i_aux_rts, o_aux_tx, o_aux_cts
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);
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);
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input i_clk_100mhz, i_reset_btn;
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input i_clk_100mhz, i_reset_btn;
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input [3:0] i_sw; // Switches
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input [3:0] i_sw; // Switches
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input [3:0] i_btn; // Buttons
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input [3:0] i_btn; // Buttons
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output wire [3:0] o_led; // LED
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output wire [3:0] o_led; // LED
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output wire [2:0] o_clr_led0, o_clr_led1, o_clr_led2, o_clr_led3;
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output wire [2:0] o_clr_led0, o_clr_led1, o_clr_led2, o_clr_led3;
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// UARTs
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// UARTs
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input i_uart_rx;
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input i_uart_rx;
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output wire o_uart_tx;
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output wire o_uart_tx;
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// Quad SPI flash
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// Quad SPI flash
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output wire o_qspi_sck, o_qspi_cs_n;
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output wire o_qspi_sck, o_qspi_cs_n;
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inout [3:0] io_qspi_dat;
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inout [3:0] io_qspi_dat;
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// Ethernet // Not yet implemented
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// Ethernet // Not yet implemented
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// Ethernet control (MDIO)
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// Ethernet control (MDIO)
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output wire o_eth_mdclk;
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output wire o_eth_mdclk;
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inout wire io_eth_mdio;
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inout wire io_eth_mdio;
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// DDR3 SDRAM
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// DDR3 SDRAM
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output wire o_ddr_reset_n;
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output wire o_ddr_reset_n;
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output wire o_ddr_cke;
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output wire o_ddr_cke;
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output wire o_ddr_ck_p, o_ddr_ck_n;
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output wire o_ddr_ck_p, o_ddr_ck_n;
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output wire o_ddr_cs_n, o_ddr_ras_n, o_ddr_cas_n, o_ddr_we_n;
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output wire o_ddr_cs_n, o_ddr_ras_n, o_ddr_cas_n, o_ddr_we_n;
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inout [1:0] io_ddr_dqs_p, io_ddr_dqs_n;
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inout [1:0] io_ddr_dqs_p, io_ddr_dqs_n;
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output wire [13:0] o_ddr_addr;
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output wire [13:0] o_ddr_addr;
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output wire [2:0] o_ddr_ba;
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output wire [2:0] o_ddr_ba;
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inout [15:0] io_ddr_data;
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inout [15:0] io_ddr_data;
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//
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//
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output wire [1:0] o_ddr_dm;
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output wire [1:0] o_ddr_dm;
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output wire o_ddr_odt;
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output wire o_ddr_odt;
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// SD Card
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// SD Card
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output wire o_sd_sck;
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output wire o_sd_sck;
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inout io_sd_cmd;
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inout io_sd_cmd;
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inout [3:0] io_sd;
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inout [3:0] io_sd;
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input i_sd_cs;
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input i_sd_cs;
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input i_sd_wp;
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input i_sd_wp;
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// GPS PMod
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// GPS PMod
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input i_gps_pps, i_gps_3df, i_gps_rx;
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input i_gps_pps, i_gps_3df, i_gps_rx;
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output wire o_gps_tx;
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output wire o_gps_tx;
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// OLEDRGB PMod
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// OLEDRGB PMod
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output wire o_oled_sck, o_oled_cs_n, o_oled_mosi,
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output wire o_oled_sck, o_oled_cs_n, o_oled_mosi,
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o_oled_dcn, o_oled_reset_n, o_oled_vccen,
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o_oled_dcn, o_oled_reset_n, o_oled_vccen,
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o_oled_pmoden;
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o_oled_pmoden;
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// Aux UART
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// Aux UART
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input i_aux_rx, i_aux_rts;
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input i_aux_rx, i_aux_rts;
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output wire o_aux_tx, o_aux_cts;
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output wire o_aux_tx, o_aux_cts;
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`define FULLCLOCK
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`define FULLCLOCK
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// Build our master clock
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// Build our master clock
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wire i_clk, clk_for_ddr, clk2_unused, enet_clk, clk_analyzer,
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wire i_clk, clk_for_ddr, clk2_unused, enet_clk, clk_analyzer,
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clk_feedback, clk_locked, clk_analyzer_b;
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clk_feedback, clk_locked, clk_analyzer_b;
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PLLE2_BASE #(
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PLLE2_BASE #(
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.BANDWIDTH("OPTIMIZED"), // OPTIMIZED, HIGH, LOW
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.BANDWIDTH("OPTIMIZED"), // OPTIMIZED, HIGH, LOW
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.CLKFBOUT_PHASE(0.0), // Phase offset in degrees of CLKFB, (-360-360)
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.CLKFBOUT_PHASE(0.0), // Phase offset in degrees of CLKFB, (-360-360)
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.CLKIN1_PERIOD(10.0), // Input clock period in ns to ps resolution
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.CLKIN1_PERIOD(10.0), // Input clock period in ns to ps resolution
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`ifdef FULLCLOCK
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`ifdef FULLCLOCK
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// CLKOUT0_DIVIDE - CLKOUT5_DIVIDE: divide amount for each CLKOUT(1-128)
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// CLKOUT0_DIVIDE - CLKOUT5_DIVIDE: divide amount for each CLKOUT(1-128)
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.CLKFBOUT_MULT(8), // Multiply value for all CLKOUT (2-64)
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.CLKFBOUT_MULT(8), // Multiply value for all CLKOUT (2-64)
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.CLKOUT0_DIVIDE(4), // 200 MHz
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.CLKOUT0_DIVIDE(4), // 200 MHz
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.CLKOUT1_DIVIDE(4), // 200 MHz clock for DDR memory
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.CLKOUT1_DIVIDE(4), // 200 MHz clock for DDR memory
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.CLKOUT2_DIVIDE(8), // 100 MHz
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.CLKOUT2_DIVIDE(8), // 100 MHz
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.CLKOUT3_DIVIDE(32), // 25 MHz
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.CLKOUT3_DIVIDE(32), // 25 MHz
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.CLKOUT4_DIVIDE(1), // 800 MHz
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.CLKOUT4_DIVIDE(1), // 800 MHz
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.CLKOUT5_DIVIDE(1),
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.CLKOUT5_DIVIDE(1),
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`else
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`else
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// 100*64/40 = 160 -- the fastest speed where the UART will
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// 100*64/40 = 160 -- the fastest speed where the UART will
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// still work at 4MBaud. Others will still support 115200
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// still work at 4MBaud. Others will still support 115200
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// Baud
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// Baud
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// 100*64/36 = 177.78
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// 100*64/36 = 177.78
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// 100*64/34 = 188.24
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// 100*64/34 = 188.24
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// 100*64/33 = 193.94
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// 100*64/33 = 193.94
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.CLKFBOUT_MULT(8), // Multiply value for all CLKOUT (2-64)
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.CLKFBOUT_MULT(8), // Multiply value for all CLKOUT (2-64)
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.CLKOUT0_DIVIDE(5), // 160 MHz
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.CLKOUT0_DIVIDE(5), // 160 MHz
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.CLKOUT1_DIVIDE(5), // 160 MHz //Clock too slow for DDR mem
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.CLKOUT1_DIVIDE(5), // 160 MHz //Clock too slow for DDR mem
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.CLKOUT2_DIVIDE(10), // 80 MHz
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.CLKOUT2_DIVIDE(10), // 80 MHz
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.CLKOUT3_DIVIDE(40), // 20 MHz
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.CLKOUT3_DIVIDE(40), // 20 MHz
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.CLKOUT4_DIVIDE(1), // 40 MHz
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.CLKOUT4_DIVIDE(1), // 40 MHz
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.CLKOUT5_DIVIDE(1),
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.CLKOUT5_DIVIDE(1),
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`endif
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`endif
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// CLKOUT0_DUTY_CYCLE -- Duty cycle for each CLKOUT
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// CLKOUT0_DUTY_CYCLE -- Duty cycle for each CLKOUT
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.CLKOUT0_DUTY_CYCLE(0.5),
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.CLKOUT0_DUTY_CYCLE(0.5),
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.CLKOUT1_DUTY_CYCLE(0.5),
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.CLKOUT1_DUTY_CYCLE(0.5),
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.CLKOUT2_DUTY_CYCLE(0.5),
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.CLKOUT2_DUTY_CYCLE(0.5),
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.CLKOUT3_DUTY_CYCLE(0.5),
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.CLKOUT3_DUTY_CYCLE(0.5),
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.CLKOUT4_DUTY_CYCLE(0.5),
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.CLKOUT4_DUTY_CYCLE(0.5),
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.CLKOUT5_DUTY_CYCLE(0.5),
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.CLKOUT5_DUTY_CYCLE(0.5),
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// CLKOUT0_PHASE -- phase offset for each CLKOUT
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// CLKOUT0_PHASE -- phase offset for each CLKOUT
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.CLKOUT0_PHASE(0.0),
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.CLKOUT0_PHASE(0.0),
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.CLKOUT1_PHASE(270.0),
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.CLKOUT1_PHASE(270.0),
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.CLKOUT2_PHASE(0.0),
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.CLKOUT2_PHASE(0.0),
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.CLKOUT3_PHASE(0.0),
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.CLKOUT3_PHASE(0.0),
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.CLKOUT4_PHASE(0.0),
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.CLKOUT4_PHASE(0.0),
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.CLKOUT5_PHASE(180.0),
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.CLKOUT5_PHASE(180.0),
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.DIVCLK_DIVIDE(1), // Master division value , (1-56)
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.DIVCLK_DIVIDE(1), // Master division value , (1-56)
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.REF_JITTER1(0.0), // Reference input jitter in UI (0.000-0.999)
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.REF_JITTER1(0.0), // Reference input jitter in UI (0.000-0.999)
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.STARTUP_WAIT("FALSE") // Delayu DONE until PLL Locks, ("TRUE"/"FALSE")
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.STARTUP_WAIT("FALSE") // Delayu DONE until PLL Locks, ("TRUE"/"FALSE")
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) genclock(
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) genclock(
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// Clock outputs: 1-bit (each) output
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// Clock outputs: 1-bit (each) output
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.CLKOUT0(i_clk),
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.CLKOUT0(i_clk),
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.CLKOUT1(clk_for_ddr),
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.CLKOUT1(clk_for_ddr),
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.CLKOUT2(clk2_unused), // Reserved for flash, should we need it
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.CLKOUT2(clk2_unused), // Reserved for flash, should we need it
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.CLKOUT3(enet_clk),
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.CLKOUT3(enet_clk),
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.CLKOUT4(clk_analyzer),
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.CLKOUT4(clk_analyzer),
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.CLKOUT5(clk_analyzer_b),
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.CLKOUT5(clk_analyzer_b),
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.CLKFBOUT(clk_feedback), // 1-bit output, feedback clock
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.CLKFBOUT(clk_feedback), // 1-bit output, feedback clock
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.LOCKED(clk_locked),
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.LOCKED(clk_locked),
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.CLKIN1(i_clk_100mhz),
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.CLKIN1(i_clk_100mhz),
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.PWRDWN(1'b0),
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.PWRDWN(1'b0),
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.RST(1'b0),
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.RST(1'b0),
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.CLKFBIN(clk_feedback) // 1-bit input, feedback clock
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.CLKFBIN(clk_feedback) // 1-bit input, feedback clock
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);
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);
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// UART interface
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// UART interface
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wire [29:0] bus_uart_setup;
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wire [29:0] bus_uart_setup;
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`ifdef FULLCLOCK
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`ifdef FULLCLOCK
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assign bus_uart_setup = 30'h10000032; // 4MBaud, 7 bits
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assign bus_uart_setup = 30'h10000032; // 4MBaud, 7 bits
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`else
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`else
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assign bus_uart_setup = 30'h10000028;//4MBaud,7 bits,@160MHzClk
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assign bus_uart_setup = 30'h10000028;//4MBaud,7 bits,@160MHzClk
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//assign bus_uart_setup = 30'h10000019;//4MBaud,7 bits,@100MHzClk
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//assign bus_uart_setup = 30'h10000019;//4MBaud,7 bits,@100MHzClk
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`endif
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`endif
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wire [7:0] rx_data, tx_data;
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wire [7:0] rx_data, tx_data;
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wire rx_break, rx_parity_err, rx_frame_err, rx_stb;
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wire rx_break, rx_parity_err, rx_frame_err, rx_stb;
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wire tx_stb, tx_busy;
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wire tx_stb, tx_busy;
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reg pwr_reset, pre_reset;
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reg pwr_reset, pre_reset;
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initial pwr_reset = 1'b1;
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initial pwr_reset = 1'b1;
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initial pre_reset = 1'b0;
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initial pre_reset = 1'b0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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pre_reset <= ~i_reset_btn;
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pre_reset <= ~i_reset_btn;
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always @(posedge i_clk)
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always @(posedge i_clk)
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pwr_reset <= pre_reset;
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pwr_reset <= pre_reset;
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wire w_ck_uart, w_uart_tx;
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wire w_ck_uart, w_uart_tx;
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rxuart rcv(i_clk, pwr_reset, bus_uart_setup, i_uart_rx,
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rxuart rcv(i_clk, pwr_reset, bus_uart_setup, i_uart_rx,
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rx_stb, rx_data, rx_break,
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rx_stb, rx_data, rx_break,
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rx_parity_err, rx_frame_err, w_ck_uart);
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rx_parity_err, rx_frame_err, w_ck_uart);
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txuart txv(i_clk, pwr_reset, bus_uart_setup, 1'b0,
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txuart txv(i_clk, pwr_reset, bus_uart_setup, 1'b0,
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tx_stb, tx_data, o_uart_tx, tx_busy);
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tx_stb, tx_data, o_uart_tx, tx_busy);
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//////
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//////
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//
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//
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//
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//
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// The WB bus interconnect, herein called fastmaster, which handles
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// The WB bus interconnect, herein called fastmaster, which handles
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// just about ... everything.
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// just about ... everything.
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//
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//
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//
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//
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//////
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//////
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wire w_qspi_sck;
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wire w_qspi_sck, w_qspi_cs_n;
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wire [1:0] qspi_bmod;
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wire [1:0] qspi_bmod;
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wire [3:0] qspi_dat;
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wire [3:0] qspi_dat;
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wire [3:0] i_qspi_dat;
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wire [3:0] i_qspi_dat;
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//
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//
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wire [31:0] wo_ddr_data, wi_ddr_data;
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wire [31:0] wo_ddr_data, wi_ddr_data;
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wire w_ddr_dqs, w_ddr_dm, w_ddr_bus_oe, w_ddr_odt;
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wire w_ddr_dqs, w_ddr_dm, w_ddr_bus_oe, w_ddr_odt;
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wire [2:0] w_ddr_ba;
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wire [2:0] w_ddr_ba;
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wire w_ddr_cs_n, w_ddr_ras_n, w_ddr_cas_n, w_ddr_we_n;
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wire w_ddr_cs_n, w_ddr_ras_n, w_ddr_cas_n, w_ddr_we_n;
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wire [13:0] w_ddr_addr;
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wire [13:0] w_ddr_addr;
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reg [31:0] r_ddr_data;
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reg [31:0] r_ddr_data;
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//
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//
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wire w_mdio, w_mdwe;
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wire w_mdio, w_mdwe;
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//
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//
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wire w_sd_cmd;
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wire w_sd_cmd;
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wire [3:0] w_sd_data;
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wire [3:0] w_sd_data;
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fastmaster wbbus(i_clk, pwr_reset,
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fastmaster wbbus(i_clk, pwr_reset,
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// External USB-UART bus control
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// External USB-UART bus control
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rx_stb, rx_data, tx_stb, tx_data, tx_busy,
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rx_stb, rx_data, tx_stb, tx_data, tx_busy,
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// Board lights and switches
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// Board lights and switches
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i_sw, i_btn, o_led,
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i_sw, i_btn, o_led,
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o_clr_led0, o_clr_led1, o_clr_led2, o_clr_led3,
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o_clr_led0, o_clr_led1, o_clr_led2, o_clr_led3,
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// Board level PMod I/O
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// Board level PMod I/O
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i_aux_rx, o_aux_tx, o_aux_cts, i_gps_rx, o_gps_tx,
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i_aux_rx, o_aux_tx, o_aux_cts, i_gps_rx, o_gps_tx,
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// Quad SPI flash
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// Quad SPI flash
|
o_qspi_cs_n, w_qspi_sck, qspi_dat, io_qspi_dat, qspi_bmod,
|
w_qspi_cs_n, w_qspi_sck, qspi_dat, i_qspi_dat, qspi_bmod,
|
// DDR3 SDRAM
|
// DDR3 SDRAM
|
o_ddr_reset_n, o_ddr_cke,
|
o_ddr_reset_n, o_ddr_cke,
|
w_ddr_cs_n, w_ddr_ras_n, w_ddr_cas_n, w_ddr_we_n,
|
w_ddr_cs_n, w_ddr_ras_n, w_ddr_cas_n, w_ddr_we_n,
|
w_ddr_dqs, w_ddr_dm, w_ddr_odt, w_ddr_bus_oe,
|
w_ddr_dqs, w_ddr_dm, w_ddr_odt, w_ddr_bus_oe,
|
w_ddr_addr, w_ddr_ba, wo_ddr_data, r_ddr_data,
|
w_ddr_addr, w_ddr_ba, wo_ddr_data, r_ddr_data,
|
// SD Card
|
// SD Card
|
o_sd_sck, w_sd_cmd, w_sd_data, io_sd_cmd, io_sd, i_sd_cs,
|
o_sd_sck, w_sd_cmd, w_sd_data, io_sd_cmd, io_sd, i_sd_cs,
|
// Ethernet control (MDIO) lines
|
// Ethernet control (MDIO) lines
|
o_eth_mdclk, w_mdio, w_mdwe, io_eth_mdio,
|
o_eth_mdclk, w_mdio, w_mdwe, io_eth_mdio,
|
// OLEDRGB PMod wires
|
// OLEDRGB PMod wires
|
o_oled_sck, o_oled_cs_n, o_oled_mosi, o_oled_dcn,
|
o_oled_sck, o_oled_cs_n, o_oled_mosi, o_oled_dcn,
|
o_oled_reset_n, o_oled_vccen, o_oled_pmoden,
|
o_oled_reset_n, o_oled_vccen, o_oled_pmoden,
|
// GPS PMod
|
// GPS PMod
|
i_gps_pps, i_gps_3df
|
i_gps_pps, i_gps_3df
|
);
|
);
|
|
|
//////
|
//////
|
//
|
//
|
//
|
//
|
// Some wires need special treatment, and so are not quite completely
|
// Some wires need special treatment, and so are not quite completely
|
// handled by the bus master. These are handled below.
|
// handled by the bus master. These are handled below.
|
//
|
//
|
//
|
//
|
//////
|
//////
|
|
|
//
|
//
|
//
|
//
|
// QSPI)BMOD, Quad SPI bus mode, Bus modes are:
|
// QSPI)BMOD, Quad SPI bus mode, Bus modes are:
|
// 0? Normal serial mode, one bit in one bit out
|
// 0? Normal serial mode, one bit in one bit out
|
// 10 Quad SPI mode, going out
|
// 10 Quad SPI mode, going out
|
// 11 Quad SPI mode coming from the device (read mode)
|
// 11 Quad SPI mode coming from the device (read mode)
|
//
|
//
|
// ?? Dual mode in (not yet)
|
// ?? Dual mode in (not yet)
|
// ?? Dual mode out (not yet)
|
// ?? Dual mode out (not yet)
|
//
|
//
|
//
|
//
|
`define QSPI_OUT_VERSION_ONE
|
// `define QSPI_OUT_VERSION_ONE
|
`ifdef QSPI_OUT_VERSION_ONE
|
`ifdef QSPI_OUT_VERSION_ONE
|
assign io_qspi_dat = (~qspi_bmod[1])?({2'b11,1'bz,qspi_dat[0]})
|
assign io_qspi_dat = (~qspi_bmod[1])?({2'b11,1'bz,qspi_dat[0]})
|
:((qspi_bmod[0])?(4'bzzzz):(qspi_dat[3:0]));
|
:((qspi_bmod[0])?(4'bzzzz):(qspi_dat[3:0]));
|
assign i_qspi_dat = io_qspi_dat;
|
assign i_qspi_dat = io_qspi_dat;
|
assign o_qspi_sck = w_qspi_sck;
|
assign o_qspi_sck = w_qspi_sck;
|
`else
|
`else
|
wire [3:0] i_qspi_ignore;
|
wire [3:0] i_qspi_pedge, i_qspi_nedge;
|
|
|
xoddr xqspi_sck( i_clk, { w_qspi_sck, w_qspi_sck }, o_qspi_sck);
|
xoddr xqspi_sck( i_clk, { w_qspi_sck, w_qspi_sck }, o_qspi_sck);
|
|
xoddr xqspi_csn( i_clk, { w_qspi_cs_n, w_qspi_cs_n },o_qspi_cs_n);
|
//
|
//
|
xioddr xqspi_d0( i_clk, (~qspi_bmod[0])||(~qspi_bmod[1]),
|
xioddr xqspi_d0( i_clk, (qspi_bmod != 2'b11),
|
{ qspi_dat[0], qspi_dat[0] },
|
{ qspi_dat[0], qspi_dat[0] },
|
{ i_qspi_ignore[0], i_qspi_dat[0] }, io_qspi_dat[0]);
|
{ i_qspi_pedge[0], i_qspi_nedge[0] }, io_qspi_dat[0]);
|
xioddr xqspi_d1( i_clk, (qspi_bmod==2'b10),
|
xioddr xqspi_d1( i_clk, (qspi_bmod==2'b10),
|
{ qspi_dat[1], qspi_dat[1] },
|
{ qspi_dat[1], qspi_dat[1] },
|
{ i_qspi_ignore[1], i_qspi_dat[1] }, io_qspi_dat[1]);
|
{ i_qspi_pedge[1], i_qspi_nedge[1] }, io_qspi_dat[1]);
|
xioddr xqspi_d2( i_clk, (qspi_bmod!=2'b11),
|
xioddr xqspi_d2( i_clk, (qspi_bmod!=2'b11),
|
(qspi_bmod[1])?{ qspi_dat[2], qspi_dat[2] }:2'b11,
|
(qspi_bmod[1])?{ qspi_dat[2], qspi_dat[2] }:2'b11,
|
{ i_qspi_ignore[2], i_qspi_dat[2] }, io_qspi_dat[2]);
|
{ i_qspi_pedge[2], i_qspi_nedge[2] }, io_qspi_dat[2]);
|
xioddr xqspi_d3( i_clk, (qspi_bmod!=2'b11),
|
xioddr xqspi_d3( i_clk, (qspi_bmod!=2'b11),
|
(qspi_bmod[1])?{ qspi_dat[3], qspi_dat[3] }:2'b11,
|
(qspi_bmod[1])?{ qspi_dat[3], qspi_dat[3] }:2'b11,
|
{ i_qspi_ignore[3], i_qspi_dat[3] }, io_qspi_dat[3]);
|
{ i_qspi_pedge[3], i_qspi_nedge[3] }, io_qspi_dat[3]);
|
`endif
|
|
|
|
//
|
|
// Proposed QSPI mode select, to allow dual I/O mode
|
|
// 000 Normal SPI mode
|
|
// 001 Dual mode input
|
|
// 010 Dual mode, output
|
|
// 101 Quad I/O mode input
|
|
// 110 Quad I/O mode output
|
|
//
|
|
//
|
|
// assign io_qspi_dat[3:2] = (~qspi_bmod[2]) ? 2'b11
|
|
// : (qspi_bmod[0])?2'bzz : qspi_dat[3:2];
|
|
// assign io_qspi_dat[1] = (~qspi_bmod[1])?qspi_dat[1]:1'bz;
|
|
// assign io_qspi_dat[0] = (qspi_bmod[0])?1'bz : qspi_dat[0];
|
|
|
|
//
|
|
//
|
|
// The following primitive is necessary on other boards in order to
|
|
// gain access to the o_qspi_sck pin. On the Arty, however, there is
|
|
// a clock PIN, so we don't need this primitive.
|
|
//
|
|
//
|
|
/*
|
|
wire [3:0] su_nc; // Startup primitive, no connect
|
|
STARTUPE2 #(
|
|
// Leave PROG_USR false to avoid activating the program
|
|
// event security feature. Notes state that such a feature
|
|
// requires encrypted bitstreams.
|
|
.PROG_USR("FALSE"),
|
|
// Sets the configuration clock frequency (in ns) for
|
|
// simulation.
|
|
.SIM_CCLK_FREQ(0.0)
|
|
) STARTUPE2_inst (
|
|
// CFGCLK, 1'b output: Configuration main clock output -- no connect
|
|
.CFGCLK(su_nc[0]),
|
|
// CFGMCLK, 1'b output: Configuration internal oscillator clock output
|
|
.CFGMCLK(su_nc[1]),
|
|
// EOS, 1'b output: Active high output indicating the End Of Startup.
|
|
.EOS(su_nc[2]),
|
|
// PREQ, 1'b output: PROGRAM request to fabric output
|
|
// Only enabled if PROG_USR is set. This lets the fabric know
|
|
// that a request has been made (either JTAG or pin pulled low)
|
|
// to program the device
|
|
.PREQ(su_nc[3]),
|
|
// CLK, 1'b input: User start-up clock input
|
|
.CLK(1'b0),
|
|
// GSR, 1'b input: Global Set/Reset input
|
|
.GSR(1'b0),
|
|
// GTS, 1'b input: Global 3-state input
|
|
.GTS(1'b0),
|
|
// KEYCLEARB, 1'b input: Clear AES Decrypter Key input from BBRAM
|
|
.KEYCLEARB(1'b0),
|
|
// PACK, 1-bit input: PROGRAM acknowledge input
|
|
// This pin is only enabled if PROG_USR is set. This allows the
|
|
// FPGA to acknowledge a request for reprogram to allow the FPGA
|
|
// to get itself into a reprogrammable state first.
|
|
.PACK(1'b0),
|
|
// USRCLKO, 1-bit input: User CCLK input -- This is why I am using this
|
|
// module at all.
|
|
.USRCCLKO(qspi_sck),
|
|
// USRCCLKTS, 1'b input: User CCLK 3-state enable input
|
|
// An active high here places the clock into a high impedence
|
|
// state. Since we wish to use the clock as an active output
|
|
// always, we drive this pin low.
|
|
.USRCCLKTS(1'b0),
|
|
// USRDONEO, 1'b input: User DONE pin output control
|
|
// Set this to "high" to make sure that the DONE LED pin is
|
|
// high.
|
|
.USRDONEO(1'b1),
|
|
// USRDONETS, 1'b input: User DONE 3-state enable output
|
|
// This enables the FPGA DONE pin to be active. Setting this
|
|
// active high sets the DONE pin to high impedence, setting it
|
|
// low allows the output of this pin to be as stated above.
|
|
.USRDONETS(1'b1)
|
|
);
|
|
*/
|
|
|
|
|
|
|
assign i_qspi_dat = i_qspi_pedge;
|
|
`endif
|
|
|
//
|
//
|
//
|
//
|
// Wires for setting up the SD Card Controller
|
// Wires for setting up the SD Card Controller
|
//
|
//
|
//
|
//
|
assign io_sd_cmd = w_sd_cmd ? 1'bz:1'b0;
|
assign io_sd_cmd = w_sd_cmd ? 1'bz:1'b0;
|
assign io_sd[0] = w_sd_data[0]? 1'bz:1'b0;
|
assign io_sd[0] = w_sd_data[0]? 1'bz:1'b0;
|
assign io_sd[1] = w_sd_data[1]? 1'bz:1'b0;
|
assign io_sd[1] = w_sd_data[1]? 1'bz:1'b0;
|
assign io_sd[2] = w_sd_data[2]? 1'bz:1'b0;
|
assign io_sd[2] = w_sd_data[2]? 1'bz:1'b0;
|
assign io_sd[3] = w_sd_data[3]? 1'bz:1'b0;
|
assign io_sd[3] = w_sd_data[3]? 1'bz:1'b0;
|
|
|
|
|
//
|
//
|
//
|
//
|
// Wire(s) for setting up the MDIO ethernet control structure
|
// Wire(s) for setting up the MDIO ethernet control structure
|
//
|
//
|
//
|
//
|
assign io_eth_mdio = (w_mdwe)?w_mdio : 1'bz;
|
assign io_eth_mdio = (w_mdwe)?w_mdio : 1'bz;
|
|
|
//
|
//
|
//
|
//
|
// Wires for setting up the DDR3 memory
|
// Wires for setting up the DDR3 memory
|
//
|
//
|
//
|
//
|
`ifdef SDRAM_ACCESS
|
`ifdef SDRAM_ACCESS
|
reg [15:0] bottom_half_data;
|
reg [15:0] bottom_half_data;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
bottom_half_data <= wo_ddr_data[15:0];
|
bottom_half_data <= wo_ddr_data[15:0];
|
xioddr p0(i_clk, w_ddr_bus_oe, { wo_ddr_data[16], wo_ddr_data[0] },
|
xioddr p0(i_clk, w_ddr_bus_oe, { wo_ddr_data[16], wo_ddr_data[0] },
|
{ wi_ddr_data[16], wi_ddr_data[0] }, io_ddr_data[0]);
|
{ wi_ddr_data[16], wi_ddr_data[0] }, io_ddr_data[0]);
|
|
|
xioddr p1(i_clk, w_ddr_bus_oe, { wo_ddr_data[17], wo_ddr_data[1] },
|
xioddr p1(i_clk, w_ddr_bus_oe, { wo_ddr_data[17], wo_ddr_data[1] },
|
{ wi_ddr_data[17], wi_ddr_data[1] }, io_ddr_data[1]);
|
{ wi_ddr_data[17], wi_ddr_data[1] }, io_ddr_data[1]);
|
|
|
xioddr p2(i_clk, w_ddr_bus_oe, { wo_ddr_data[18], wo_ddr_data[2] },
|
xioddr p2(i_clk, w_ddr_bus_oe, { wo_ddr_data[18], wo_ddr_data[2] },
|
{ wi_ddr_data[18], wi_ddr_data[2] }, io_ddr_data[2]);
|
{ wi_ddr_data[18], wi_ddr_data[2] }, io_ddr_data[2]);
|
|
|
xioddr p3(i_clk, w_ddr_bus_oe, { wo_ddr_data[19], wo_ddr_data[3] },
|
xioddr p3(i_clk, w_ddr_bus_oe, { wo_ddr_data[19], wo_ddr_data[3] },
|
{ wi_ddr_data[19], wi_ddr_data[3] }, io_ddr_data[3]);
|
{ wi_ddr_data[19], wi_ddr_data[3] }, io_ddr_data[3]);
|
|
|
xioddr p4(i_clk, w_ddr_bus_oe, { wo_ddr_data[20], wo_ddr_data[4] },
|
xioddr p4(i_clk, w_ddr_bus_oe, { wo_ddr_data[20], wo_ddr_data[4] },
|
{ wi_ddr_data[20], wi_ddr_data[4] }, io_ddr_data[4]);
|
{ wi_ddr_data[20], wi_ddr_data[4] }, io_ddr_data[4]);
|
|
|
xioddr p5(i_clk, w_ddr_bus_oe, { wo_ddr_data[21], wo_ddr_data[5] },
|
xioddr p5(i_clk, w_ddr_bus_oe, { wo_ddr_data[21], wo_ddr_data[5] },
|
{ wi_ddr_data[21], wi_ddr_data[5] }, io_ddr_data[5]);
|
{ wi_ddr_data[21], wi_ddr_data[5] }, io_ddr_data[5]);
|
|
|
xioddr p6(i_clk, w_ddr_bus_oe, { wo_ddr_data[22], wo_ddr_data[6] },
|
xioddr p6(i_clk, w_ddr_bus_oe, { wo_ddr_data[22], wo_ddr_data[6] },
|
{ wi_ddr_data[22], wi_ddr_data[6] }, io_ddr_data[6]);
|
{ wi_ddr_data[22], wi_ddr_data[6] }, io_ddr_data[6]);
|
|
|
xioddr p7(i_clk, w_ddr_bus_oe, { wo_ddr_data[23], wo_ddr_data[7] },
|
xioddr p7(i_clk, w_ddr_bus_oe, { wo_ddr_data[23], wo_ddr_data[7] },
|
{ wi_ddr_data[23], wi_ddr_data[7] }, io_ddr_data[7]);
|
{ wi_ddr_data[23], wi_ddr_data[7] }, io_ddr_data[7]);
|
|
|
xioddr p8(i_clk, w_ddr_bus_oe, { wo_ddr_data[24], wo_ddr_data[8] },
|
xioddr p8(i_clk, w_ddr_bus_oe, { wo_ddr_data[24], wo_ddr_data[8] },
|
{ wi_ddr_data[24], wi_ddr_data[8] }, io_ddr_data[8]);
|
{ wi_ddr_data[24], wi_ddr_data[8] }, io_ddr_data[8]);
|
|
|
xioddr p9(i_clk, w_ddr_bus_oe, { wo_ddr_data[25], wo_ddr_data[9] },
|
xioddr p9(i_clk, w_ddr_bus_oe, { wo_ddr_data[25], wo_ddr_data[9] },
|
{ wi_ddr_data[25], wi_ddr_data[9] }, io_ddr_data[9]);
|
{ wi_ddr_data[25], wi_ddr_data[9] }, io_ddr_data[9]);
|
|
|
xioddr pa(i_clk, w_ddr_bus_oe, { wo_ddr_data[26], wo_ddr_data[10] },
|
xioddr pa(i_clk, w_ddr_bus_oe, { wo_ddr_data[26], wo_ddr_data[10] },
|
{ wi_ddr_data[26], wi_ddr_data[10] }, io_ddr_data[10]);
|
{ wi_ddr_data[26], wi_ddr_data[10] }, io_ddr_data[10]);
|
|
|
xioddr pb(i_clk, w_ddr_bus_oe, { wo_ddr_data[27], wo_ddr_data[11] },
|
xioddr pb(i_clk, w_ddr_bus_oe, { wo_ddr_data[27], wo_ddr_data[11] },
|
{ wi_ddr_data[27], wi_ddr_data[11] }, io_ddr_data[11]);
|
{ wi_ddr_data[27], wi_ddr_data[11] }, io_ddr_data[11]);
|
|
|
xioddr pc(i_clk, w_ddr_bus_oe, { wo_ddr_data[28], wo_ddr_data[12] },
|
xioddr pc(i_clk, w_ddr_bus_oe, { wo_ddr_data[28], wo_ddr_data[12] },
|
{ wi_ddr_data[28], wi_ddr_data[12] }, io_ddr_data[12]);
|
{ wi_ddr_data[28], wi_ddr_data[12] }, io_ddr_data[12]);
|
|
|
xioddr pd(i_clk, w_ddr_bus_oe, { wo_ddr_data[29], wo_ddr_data[13] },
|
xioddr pd(i_clk, w_ddr_bus_oe, { wo_ddr_data[29], wo_ddr_data[13] },
|
{ wi_ddr_data[29], wi_ddr_data[13] }, io_ddr_data[13]);
|
{ wi_ddr_data[29], wi_ddr_data[13] }, io_ddr_data[13]);
|
|
|
xioddr pe(i_clk, w_ddr_bus_oe, { wo_ddr_data[30], wo_ddr_data[14] },
|
xioddr pe(i_clk, w_ddr_bus_oe, { wo_ddr_data[30], wo_ddr_data[14] },
|
{ wi_ddr_data[30], wi_ddr_data[14] }, io_ddr_data[14]);
|
{ wi_ddr_data[30], wi_ddr_data[14] }, io_ddr_data[14]);
|
|
|
xioddr pf(i_clk, w_ddr_bus_oe, { wo_ddr_data[31], wo_ddr_data[15] },
|
xioddr pf(i_clk, w_ddr_bus_oe, { wo_ddr_data[31], wo_ddr_data[15] },
|
{ wi_ddr_data[31], wi_ddr_data[15] }, io_ddr_data[15]);
|
{ wi_ddr_data[31], wi_ddr_data[15] }, io_ddr_data[15]);
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
r_ddr_data <= wi_ddr_data;
|
r_ddr_data <= wi_ddr_data;
|
|
|
wire [7:0] w_dqs_ignore;
|
wire [7:0] w_dqs_ignore;
|
xioddrds dqs0(clk_for_ddr, w_ddr_dqs, { 1'b0, 1'b1 },
|
xioddrds dqs0(clk_for_ddr, w_ddr_dqs, { 1'b0, 1'b1 },
|
{ w_dqs_ignore[0], w_dqs_ignore[1] },
|
{ w_dqs_ignore[0], w_dqs_ignore[1] },
|
io_ddr_dqs_p[0], io_ddr_dqs_n[0]);
|
io_ddr_dqs_p[0], io_ddr_dqs_n[0]);
|
xioddrds dqs1(clk_for_ddr, w_ddr_dqs, { 1'b0, 1'b1 },
|
xioddrds dqs1(clk_for_ddr, w_ddr_dqs, { 1'b0, 1'b1 },
|
{ w_dqs_ignore[2], w_dqs_ignore[3] },
|
{ w_dqs_ignore[2], w_dqs_ignore[3] },
|
io_ddr_dqs_p[1], io_ddr_dqs_n[1]);
|
io_ddr_dqs_p[1], io_ddr_dqs_n[1]);
|
|
|
xoddr xcs_n( i_clk, { w_ddr_cs_n, w_ddr_cs_n }, o_ddr_cs_n);
|
xoddr xcs_n( i_clk, { w_ddr_cs_n, w_ddr_cs_n }, o_ddr_cs_n);
|
xoddr xras_n(i_clk, { w_ddr_ras_n, w_ddr_ras_n }, o_ddr_ras_n);
|
xoddr xras_n(i_clk, { w_ddr_ras_n, w_ddr_ras_n }, o_ddr_ras_n);
|
xoddr xcas_n(i_clk, { w_ddr_cas_n, w_ddr_cas_n }, o_ddr_cas_n);
|
xoddr xcas_n(i_clk, { w_ddr_cas_n, w_ddr_cas_n }, o_ddr_cas_n);
|
xoddr xwe_n( i_clk, { w_ddr_we_n, w_ddr_we_n }, o_ddr_we_n);
|
xoddr xwe_n( i_clk, { w_ddr_we_n, w_ddr_we_n }, o_ddr_we_n);
|
xoddr xba0( i_clk, { w_ddr_ba[0], w_ddr_ba[0] }, o_ddr_ba[0]);
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xoddr xba0( i_clk, { w_ddr_ba[0], w_ddr_ba[0] }, o_ddr_ba[0]);
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xoddr xba1( i_clk, { w_ddr_ba[1], w_ddr_ba[1] }, o_ddr_ba[1]);
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xoddr xba1( i_clk, { w_ddr_ba[1], w_ddr_ba[1] }, o_ddr_ba[1]);
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xoddr xba2( i_clk, { w_ddr_ba[2], w_ddr_ba[2] }, o_ddr_ba[2]);
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xoddr xba2( i_clk, { w_ddr_ba[2], w_ddr_ba[2] }, o_ddr_ba[2]);
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xoddr xaddr0(i_clk, { w_ddr_addr[0], w_ddr_addr[0] }, o_ddr_addr[0]);
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xoddr xaddr0(i_clk, { w_ddr_addr[0], w_ddr_addr[0] }, o_ddr_addr[0]);
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xoddr xaddr1(i_clk, { w_ddr_addr[1], w_ddr_addr[1] }, o_ddr_addr[1]);
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xoddr xaddr1(i_clk, { w_ddr_addr[1], w_ddr_addr[1] }, o_ddr_addr[1]);
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xoddr xaddr2(i_clk, { w_ddr_addr[2], w_ddr_addr[2] }, o_ddr_addr[2]);
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xoddr xaddr2(i_clk, { w_ddr_addr[2], w_ddr_addr[2] }, o_ddr_addr[2]);
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xoddr xaddr3(i_clk, { w_ddr_addr[3], w_ddr_addr[3] }, o_ddr_addr[3]);
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xoddr xaddr3(i_clk, { w_ddr_addr[3], w_ddr_addr[3] }, o_ddr_addr[3]);
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xoddr xaddr4(i_clk, { w_ddr_addr[4], w_ddr_addr[4] }, o_ddr_addr[4]);
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xoddr xaddr4(i_clk, { w_ddr_addr[4], w_ddr_addr[4] }, o_ddr_addr[4]);
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xoddr xaddr5(i_clk, { w_ddr_addr[5], w_ddr_addr[5] }, o_ddr_addr[5]);
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xoddr xaddr5(i_clk, { w_ddr_addr[5], w_ddr_addr[5] }, o_ddr_addr[5]);
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xoddr xaddr6(i_clk, { w_ddr_addr[6], w_ddr_addr[6] }, o_ddr_addr[6]);
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xoddr xaddr6(i_clk, { w_ddr_addr[6], w_ddr_addr[6] }, o_ddr_addr[6]);
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xoddr xaddr7(i_clk, { w_ddr_addr[7], w_ddr_addr[7] }, o_ddr_addr[7]);
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xoddr xaddr7(i_clk, { w_ddr_addr[7], w_ddr_addr[7] }, o_ddr_addr[7]);
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xoddr xaddr8(i_clk, { w_ddr_addr[8], w_ddr_addr[8] }, o_ddr_addr[8]);
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xoddr xaddr8(i_clk, { w_ddr_addr[8], w_ddr_addr[8] }, o_ddr_addr[8]);
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xoddr xaddr9(i_clk, { w_ddr_addr[9], w_ddr_addr[9] }, o_ddr_addr[9]);
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xoddr xaddr9(i_clk, { w_ddr_addr[9], w_ddr_addr[9] }, o_ddr_addr[9]);
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xoddr xaddr10(i_clk,{ w_ddr_addr[10],w_ddr_addr[10]}, o_ddr_addr[10]);
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xoddr xaddr10(i_clk,{ w_ddr_addr[10],w_ddr_addr[10]}, o_ddr_addr[10]);
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xoddr xaddr11(i_clk,{ w_ddr_addr[11],w_ddr_addr[11]}, o_ddr_addr[11]);
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xoddr xaddr11(i_clk,{ w_ddr_addr[11],w_ddr_addr[11]}, o_ddr_addr[11]);
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xoddr xaddr12(i_clk,{ w_ddr_addr[12],w_ddr_addr[12]}, o_ddr_addr[12]);
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xoddr xaddr12(i_clk,{ w_ddr_addr[12],w_ddr_addr[12]}, o_ddr_addr[12]);
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xoddr xaddr13(i_clk,{ w_ddr_addr[13],w_ddr_addr[13]}, o_ddr_addr[13]);
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xoddr xaddr13(i_clk,{ w_ddr_addr[13],w_ddr_addr[13]}, o_ddr_addr[13]);
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wire w_clk_for_ddr;
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wire w_clk_for_ddr;
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ODDR #(.DDR_CLK_EDGE("SAME_EDGE"))
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ODDR #(.DDR_CLK_EDGE("SAME_EDGE"))
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memclkddr(.Q(w_clk_for_ddr), .C(clk_for_ddr), .CE(1'b1),
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memclkddr(.Q(w_clk_for_ddr), .C(clk_for_ddr), .CE(1'b1),
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.D1(1'b0), .D2(1'b1), .R(1'b0), .S(1'b0));
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.D1(1'b0), .D2(1'b1), .R(1'b0), .S(1'b0));
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OBUFDS #(.IOSTANDARD("DIFF_SSTL135"), .SLEW("FAST"))
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OBUFDS #(.IOSTANDARD("DIFF_SSTL135"), .SLEW("FAST"))
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clkbuf(.O(o_ddr_ck_p), .OB(o_ddr_ck_n), .I(w_clk_for_ddr));
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clkbuf(.O(o_ddr_ck_p), .OB(o_ddr_ck_n), .I(w_clk_for_ddr));
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// assign o_ddr_dm[0] = w_ddr_dm;
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// assign o_ddr_dm[0] = w_ddr_dm;
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// assign o_ddr_dm[1] = w_ddr_dm;
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// assign o_ddr_dm[1] = w_ddr_dm;
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xoddr xdm0(i_clk,{ w_ddr_dm, w_ddr_dm }, o_ddr_dm[0]);
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xoddr xdm0(i_clk,{ w_ddr_dm, w_ddr_dm }, o_ddr_dm[0]);
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xoddr xdm1(i_clk,{ w_ddr_dm, w_ddr_dm }, o_ddr_dm[1]);
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xoddr xdm1(i_clk,{ w_ddr_dm, w_ddr_dm }, o_ddr_dm[1]);
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assign o_ddr_odt = (~o_ddr_reset_n)? 1'bz : w_ddr_odt;
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assign o_ddr_odt = (~o_ddr_reset_n)? 1'bz : w_ddr_odt;
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// xlogicanalyzer ladata(i_clk, io_ddr_data[0], w_ddr_debug[3:0]);
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// xlogicanalyzer ladata(i_clk, io_ddr_data[0], w_ddr_debug[3:0]);
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// xlogicanalyzer ladclk(clk_analyzer, clk_analyzer_b,
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// xlogicanalyzer ladclk(clk_analyzer, clk_analyzer_b,
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// i_clk, o_ddr_ck_p, w_ddr_debug[7:4]);
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// i_clk, o_ddr_ck_p, w_ddr_debug[7:4]);
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assign w_ddr_debug[7:4] = 4'h0;
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assign w_ddr_debug[7:4] = 4'h0;
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assign w_ddr_debug[3:0] = 4'h0;
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assign w_ddr_debug[3:0] = 4'h0;
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`else
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`else
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assign o_ddr_cs_n = w_ddr_cs_n;
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assign o_ddr_cs_n = w_ddr_cs_n;
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assign o_ddr_ras_n = w_ddr_ras_n;
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assign o_ddr_ras_n = w_ddr_ras_n;
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assign o_ddr_cas_n = w_ddr_cas_n;
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assign o_ddr_cas_n = w_ddr_cas_n;
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assign o_ddr_we_n = w_ddr_we_n;
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assign o_ddr_we_n = w_ddr_we_n;
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//
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//
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assign o_ddr_ba = w_ddr_ba;
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assign o_ddr_ba = w_ddr_ba;
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assign o_ddr_addr = w_ddr_addr;
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assign o_ddr_addr = w_ddr_addr;
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//
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//
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assign o_ddr_dm[1:0] = 2'b00;
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assign o_ddr_dm[1:0] = 2'b00;
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assign o_ddr_odt = 1'b0;
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assign o_ddr_odt = 1'b0;
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//
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//
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assign io_ddr_data = 16'bzzzz_zzzz_zzzz_zzzz;
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assign io_ddr_data = 16'bzzzz_zzzz_zzzz_zzzz;
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always @(posedge i_clk)
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always @(posedge i_clk)
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r_ddr_data = 16'h0000;
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r_ddr_data = 16'h0000;
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//wire w_clk_for_ddr;
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//wire w_clk_for_ddr;
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//ODDR #(.DDR_CLK_EDGE("SAME_EDGE"))
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//ODDR #(.DDR_CLK_EDGE("SAME_EDGE"))
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//memclkddr(.Q(w_clk_for_ddr), .C(clk_for_ddr), .CE(1'b1),
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//memclkddr(.Q(w_clk_for_ddr), .C(clk_for_ddr), .CE(1'b1),
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//.D1(1'b0), .D2(1'b1), .R(1'b0), .S(1'b0));
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//.D1(1'b0), .D2(1'b1), .R(1'b0), .S(1'b0));
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OBUFDS #(.IOSTANDARD("DIFF_SSTL135"), .SLEW("FAST"))
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OBUFDS #(.IOSTANDARD("DIFF_SSTL135"), .SLEW("FAST"))
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clkbuf(.O(o_ddr_ck_p), .OB(o_ddr_ck_n), .I(1'b1));
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clkbuf(.O(o_ddr_ck_p), .OB(o_ddr_ck_n), .I(1'b1));
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wire [7:0] w_dqs_ignore;
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wire [7:0] w_dqs_ignore;
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xioddrds dqs0(clk_for_ddr, w_ddr_dqs, { 1'b0, 1'b1 },
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xioddrds dqs0(clk_for_ddr, w_ddr_dqs, { 1'b0, 1'b1 },
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{ w_dqs_ignore[0], w_dqs_ignore[1] },
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{ w_dqs_ignore[0], w_dqs_ignore[1] },
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io_ddr_dqs_p[0], io_ddr_dqs_n[0]);
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io_ddr_dqs_p[0], io_ddr_dqs_n[0]);
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xioddrds dqs1(clk_for_ddr, w_ddr_dqs, { 1'b0, 1'b1 },
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xioddrds dqs1(clk_for_ddr, w_ddr_dqs, { 1'b0, 1'b1 },
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{ w_dqs_ignore[2], w_dqs_ignore[3] },
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{ w_dqs_ignore[2], w_dqs_ignore[3] },
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io_ddr_dqs_p[1], io_ddr_dqs_n[1]);
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io_ddr_dqs_p[1], io_ddr_dqs_n[1]);
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|
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`endif
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`endif
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endmodule
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endmodule
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