////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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// Filename: gpsclock.v
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// Filename: gpsclock.v
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//
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//
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// Project: A GPS Schooled Clock Core
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// Project: A GPS Schooled Clock Core
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//
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//
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// Purpose: The purpose of this module is to school a counter, run off of
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// Purpose: The purpose of this module is to school a counter, run off of
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// the FPGA's local oscillator, to match a GPS 1PPS signal. Should
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// the FPGA's local oscillator, to match a GPS 1PPS signal. Should
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// the GPS 1PPS vanish, the result will flywheel with its last
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// the GPS 1PPS vanish, the result will flywheel with its last
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// solution (both frequency and phase) until GPS is available
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// solution (both frequency and phase) until GPS is available
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// again.
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// again.
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//
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//
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// This approach can be used to measure the speed of the
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// This approach can be used to measure the speed of the
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// local oscillator, although there may be other more appropriate
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// local oscillator, although there may be other more appropriate
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// means to do this.
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// means to do this.
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//
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//
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// Note that this core does not produce anything more than
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// Note that this core does not produce anything more than
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// subsecond timing resolution.
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// subsecond timing resolution.
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//
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//
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// Parameters: This core needs two parameters set below, the DEFAULT_STEP
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// Parameters: This core needs two parameters set below, the DEFAULT_STEP
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// and the DEFAULT_WORD_STEP. The first must be set to
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// and the DEFAULT_WORD_STEP. The first must be set to
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// 2^RW / (nominal local clock rate), whereas the second must be
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// 2^RW / (nominal local clock rate), whereas the second must be
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// set to 2^(RW/2) / (nominal clock rate), where RW is the register
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// set to 2^(RW/2) / (nominal clock rate), where RW is the register
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// width used for our computations. (64 is sufficient for up to
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// width used for our computations. (64 is sufficient for up to
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// 4 GHz clock speeds, 56 is minimum for 100 MHz.) Although
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// 4 GHz clock speeds, 56 is minimum for 100 MHz.) Although
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// RW is listed as a variable parameter, I have no plans to
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// RW is listed as a variable parameter, I have no plans to
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// test values other than 64. So your mileage might vary there.
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// test values other than 64. So your mileage might vary there.
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//
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//
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// Other parameters, alpha, beta, and gamma are specific to the
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// Other parameters, alpha, beta, and gamma are specific to the
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// loop bandwidth you would like to choose. Please see the
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// loop bandwidth you would like to choose. Please see the
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// accompanying specification for a selection of what values
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// accompanying specification for a selection of what values
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// may be useful.
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// may be useful.
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//
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//
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// Inputs:
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// Inputs:
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// i_clk A synchronous clock signal for all logic. Must be slow enough
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// i_clk A synchronous clock signal for all logic. Must be slow enough
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// that the FPGA can accomplish 64 bit math.
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// that the FPGA can accomplish 64 bit math.
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//
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//
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// i_rst Resets the clock speed / counter step to be the nominal
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// i_rst Resets the clock speed / counter step to be the nominal
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// value given by our parameter. This is useful in case the
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// value given by our parameter. This is useful in case the
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// control loop has gone off into never never land and doesn't
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// control loop has gone off into never never land and doesn't
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// seem to be returning.
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// seem to be returning.
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//
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//
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// i_pps The 1PPS signal from the GPS chip.
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// i_pps The 1PPS signal from the GPS chip.
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//
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//
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// Wishbone bus
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// Wishbone bus
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//
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//
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// Outputs:
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// Outputs:
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// o_led No circuit would be complete without a properly blinking LED.
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// o_led No circuit would be complete without a properly blinking LED.
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// This one blinks an LED at the top of the GPS 1PPS and the
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// This one blinks an LED at the top of the GPS 1PPS and the
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// internal 1PPS. When the two match, the LED will be on for
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// internal 1PPS. When the two match, the LED will be on for
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// 1/16th of a second. When no GPS 1PPS is present, the LED
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// 1/16th of a second. When no GPS 1PPS is present, the LED
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// will blink with a 50% duty cycle.
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// will blink with a 50% duty cycle.
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//
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//
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// o_tracking A boolean value indicating whether the control loop
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// o_tracking A boolean value indicating whether the control loop
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// is open (0) or closed (1). Does not indicate performance.
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// is open (0) or closed (1). Does not indicate performance.
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//
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//
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// o_count A counter, from zero to 2^RW-1, indicating the position
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// o_count A counter, from zero to 2^RW-1, indicating the position
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// of the current clock within a second. (This'll be off by
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// of the current clock within a second. (This'll be off by
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// two clocks due to internal latencies.)
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// two clocks due to internal latencies.)
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//
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//
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// o_step The amount the counter, o_count, is stepped each clock.
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// o_step The amount the counter, o_count, is stepped each clock.
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// This is related to the actual speed of the oscillator (when
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// This is related to the actual speed of the oscillator (when
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// locked) by f_XO = 2^(RW) / o_step.
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// locked) by f_XO = 2^(RW) / o_step.
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//
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//
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// o_err For those interested in how well this device is performing,
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// o_err For those interested in how well this device is performing,
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// this is the error signal coming out of the device.
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// this is the error signal coming out of the device.
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//
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//
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// o_locked Indicates a locked condition. While it should work,
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// o_locked Indicates a locked condition. While it should work,
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// it isn't the best and most versatile lock indicator. A better
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// it isn't the best and most versatile lock indicator. A better
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// indicator should be based upon how good the user wants the
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// indicator should be based upon how good the user wants the
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// lock indicator to be. This isn't that.
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// lock indicator to be. This isn't that.
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//
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//
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//
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//
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// Creator: Dan Gisselquist, Ph.D.
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// Creator: Dan Gisselquist, Ph.D.
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// Gisselquist Technology, LLC
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// Gisselquist Technology, LLC
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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// Copyright (C) 2015, Gisselquist Technology, LLC
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// Copyright (C) 2015, Gisselquist Technology, LLC
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//
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//
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// This program is free software (firmware): you can redistribute it and/or
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of the GNU General Public License as published
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// modify it under the terms of the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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// your option) any later version.
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//
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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// for more details.
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//
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//
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// You should have received a copy of the GNU General Public License along
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// You should have received a copy of the GNU General Public License along
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// with this program. (It's in the $(ROOT)/doc directory. Run make with no
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// with this program. (It's in the $(ROOT)/doc directory. Run make with no
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// target there if the PDF file isn't present.) If not, see
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// target there if the PDF file isn't present.) If not, see
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// <http://www.gnu.org/licenses/> for a copy.
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// <http://www.gnu.org/licenses/> for a copy.
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//
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//
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// License: GPL, v3, as defined and found on www.gnu.org,
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// License: GPL, v3, as defined and found on www.gnu.org,
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// http://www.gnu.org/licenses/gpl.html
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// http://www.gnu.org/licenses/gpl.html
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//
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//
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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module gpsclock(i_clk, i_rst, i_pps, o_pps, o_led,
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module gpsclock(i_clk, i_rst, i_pps, o_pps, o_led,
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i_wb_cyc_stb, i_wb_we, i_wb_addr, i_wb_data,
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i_wb_cyc_stb, i_wb_we, i_wb_addr, i_wb_data,
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o_wb_ack, o_wb_stall, o_wb_data,
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o_wb_ack, o_wb_stall, o_wb_data,
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o_tracking, o_count, o_step, o_err, o_locked, o_dbg);
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o_tracking, o_count, o_step, o_err, o_locked, o_dbg);
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parameter RW=64, // Needs to be 2ceil(Log_2(i_clk frequency))
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parameter RW=64, // Needs to be 2ceil(Log_2(i_clk frequency))
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DW=32, // The width of our data bus
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DW=32, // The width of our data bus
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ONE_SECOND = 0,
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ONE_SECOND = 0,
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NPW=RW-DW, // Width of non-parameter data
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NPW=RW-DW, // Width of non-parameter data
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HRW=RW/2; // Half of RW
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HRW=RW/2; // Half of RW
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input i_clk, i_rst;
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input i_clk, i_rst;
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input i_pps; // From the GPS device
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input i_pps; // From the GPS device
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output reg o_pps; // To our local circuitry
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output reg o_pps; // To our local circuitry
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output reg o_led; // A blinky light showing how well we're doing
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output reg o_led; // A blinky light showing how well we're doing
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// Wishbone Configuration interface
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// Wishbone Configuration interface
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input i_wb_cyc_stb, i_wb_we;
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input i_wb_cyc_stb, i_wb_we;
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input [1:0] i_wb_addr;
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input [1:0] i_wb_addr;
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input [(DW-1):0] i_wb_data;
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input [(DW-1):0] i_wb_data;
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output reg o_wb_ack;
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output reg o_wb_ack;
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output wire o_wb_stall;
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output wire o_wb_stall;
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output reg [(DW-1):0] o_wb_data;
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output reg [(DW-1):0] o_wb_data;
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// Status and timing outputs
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// Status and timing outputs
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output reg o_tracking; // 1=closed loop, 0=open
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output reg o_tracking; // 1=closed loop, 0=open
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output reg [(RW-1):0] o_count, // Fraction of a second
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output reg [(RW-1):0] o_count, // Fraction of a second
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o_step, // 2^RW / clock speed (in Hz)
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o_step, // 2^RW / clock speed (in Hz)
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o_err; // Fraction of a second err
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o_err; // Fraction of a second err
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output reg o_locked; // 1 if Locked, 0 o.w.
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output reg o_locked; // 1 if Locked, 0 o.w.
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output wire [1:0] o_dbg;
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output wire [1:0] o_dbg;
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|
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// Clock resynchronization variables
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// Clock resynchronization variables
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reg pps_d, ck_pps, lst_pps;
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reg pps_d, ck_pps, lst_pps;
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wire tick; // And a variable indicating the top of GPS 1PPS
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wire tick; // And a variable indicating the top of GPS 1PPS
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//
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//
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// Configuration variables. These control the loop bandwidth, the speed
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// Configuration variables. These control the loop bandwidth, the speed
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// of convergence, the speed of adaptation to changes, and more. If
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// of convergence, the speed of adaptation to changes, and more. If
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// you adjust these outside of what the specification recommends,
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// you adjust these outside of what the specification recommends,
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// be careful that the control loop still synchronizes!
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// be careful that the control loop still synchronizes!
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reg new_config;
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reg new_config;
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reg [5:0] r_alpha;
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reg [5:0] r_alpha;
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reg [(DW-1):0] r_beta, r_gamma, r_def_step;
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reg [(DW-1):0] r_beta, r_gamma, r_def_step;
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reg [(RW-1):0] pre_step;
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reg [(RW-1):0] pre_step;
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|
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//
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//
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// This core really operates rather slowly, in FPGA time. Of the
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// This core really operates rather slowly, in FPGA time. Of the
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// millions of ticks per second, we only do things on about less than
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// millions of ticks per second, we only do things on about less than
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// a handful. These timing signals below help us to determine when
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// a handful. These timing signals below help us to determine when
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// our data is valid during those handful.
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// our data is valid during those handful.
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//
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//
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// Timing
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// Timing
|
reg err_tick, mpy_aux, mpy_sync_two, delay_step_clk;
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reg err_tick, mpy_aux, mpy_sync_two, delay_step_clk;
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wire sub_tick, fltr_tick;
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wire sub_tick, fltr_tick;
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|
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//
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//
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// When tracking, each second we'll produce a lowpass filtered_err
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// When tracking, each second we'll produce a lowpass filtered_err
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// (via a recursive average), a count_correction and a step_correction.
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// (via a recursive average), a count_correction and a step_correction.
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// The two _correction terms then get applied at the top of the second.
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// The two _correction terms then get applied at the top of the second.
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// Here's the declaration of those parameters. The
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// Here's the declaration of those parameters. The
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// 'pre_count_correction' parameter allows us to avoid adding three
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// 'pre_count_correction' parameter allows us to avoid adding three
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// 64-bit numbers in a single clock, splitting part of that amount into
|
// 64-bit numbers in a single clock, splitting part of that amount into
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// an earlier clock.
|
// an earlier clock.
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//
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//
|
// Tracking
|
// Tracking
|
reg [(RW-1):0] count_correction, pre_count_correction;
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reg [(RW-1):0] count_correction, pre_count_correction;
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reg [(HRW-1):0] step_correction;
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reg [(HRW-1):0] step_correction;
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reg [(HRW-1):0] delayed_step_correction, delayed_step;
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reg [(HRW-1):0] delayed_step_correction, delayed_step;
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reg signed [(HRW-1):0] mpy_input;
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reg signed [(HRW-1):0] mpy_input;
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wire [(RW-1):0] w_mpy_out;
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wire [(RW-1):0] w_mpy_out;
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wire signed [(RW-1):0] filter_sub_count, filtered_err;
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wire signed [(RW-1):0] filter_sub_count, filtered_err;
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|
|
|
|
|
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//
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//
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//
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//
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//
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//
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// Wishbone access ... adjust our tracking parameters
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// Wishbone access ... adjust our tracking parameters
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//
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//
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//
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//
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//
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//
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// DEFAULT_STEP = 64'h0000_002a_f31d_c461, // 2^64 / 100 MHz
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// DEFAULT_STEP = 64'h0000_002a_f31d_c461, // 2^64 / 100 MHz
|
initial r_def_step = 32'h8_2af_31dc;
|
initial r_def_step = 32'h8_2af_31dc;
|
always @(posedge i_clk)
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always @(posedge i_clk)
|
pre_step <= { 16'h00,
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pre_step <= { 16'h00,
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(({ r_def_step[27:0], 20'h00 })>>r_def_step[31:28])};
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(({ r_def_step[27:0], 20'h00 })>>r_def_step[31:28])};
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|
|
|
// Delay writes by one clock
|
|
wire [1:0] wb_addr;
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wire [31:0] wb_data;
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reg wb_write;
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reg [1:0] r_wb_addr;
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reg [31:0] r_wb_data;
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always @(posedge i_clk)
|
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wb_write <= (i_wb_cyc_stb)&&(i_wb_we);
|
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always @(posedge i_clk)
|
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r_wb_data <= i_wb_data;
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always @(posedge i_clk)
|
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r_wb_addr <= i_wb_addr;
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|
assign wb_data = r_wb_data;
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assign wb_addr = r_wb_addr;
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|
|
initial new_config = 1'b0;
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initial new_config = 1'b0;
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always @(posedge i_clk)
|
always @(posedge i_clk)
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if ((i_wb_cyc_stb)&&(i_wb_we))
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if (wb_write)
|
begin
|
begin
|
new_config = 1'b1;
|
new_config = 1'b1;
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case(i_wb_addr)
|
case(wb_addr)
|
2'b00: r_alpha <= i_wb_data[5:0];
|
2'b00: r_alpha <= wb_data[5:0];
|
2'b01: r_beta <= i_wb_data;
|
2'b01: r_beta <= wb_data;
|
2'b10: r_gamma <= i_wb_data;
|
2'b10: r_gamma <= wb_data;
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2'b11: r_def_step <= i_wb_data;
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2'b11: r_def_step <= wb_data;
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default: begin end
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default: begin end
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// r_defstep <= i_wb_data;
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// r_defstep <= i_wb_data;
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endcase
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endcase
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end else
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end else
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new_config = 1'b0;
|
new_config = 1'b0;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
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case (i_wb_addr)
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case (i_wb_addr)
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2'b00: o_wb_data <= { 26'h00, r_alpha };
|
2'b00: o_wb_data <= { 26'h00, r_alpha };
|
2'b01: o_wb_data <= r_beta;
|
2'b01: o_wb_data <= r_beta;
|
2'b10: o_wb_data <= r_gamma;
|
2'b10: o_wb_data <= r_gamma;
|
2'b11: o_wb_data <= r_def_step;
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2'b11: o_wb_data <= r_def_step;
|
default: o_wb_data <= 0;
|
default: o_wb_data <= 0;
|
endcase
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endcase
|
|
|
reg dly_config;
|
reg dly_config;
|
initial dly_config = 1'b0;
|
initial dly_config = 1'b0;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
dly_config <= new_config;
|
dly_config <= new_config;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
o_wb_ack <= i_wb_cyc_stb;
|
o_wb_ack <= i_wb_cyc_stb;
|
assign o_wb_stall = 1'b0;
|
assign o_wb_stall = 1'b0;
|
|
|
|
|
//
|
//
|
//
|
//
|
// Deal with the realities of an unsynchronized 1PPS signal:
|
// Deal with the realities of an unsynchronized 1PPS signal:
|
// register it with two flip flops to avoid metastability issues.
|
// register it with two flip flops to avoid metastability issues.
|
// Create a 'tick' variable to note the top of a second.
|
// Create a 'tick' variable to note the top of a second.
|
//
|
//
|
//
|
//
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
begin
|
begin
|
pps_d <= i_pps;
|
pps_d <= i_pps;
|
ck_pps <= pps_d;
|
ck_pps <= pps_d;
|
lst_pps <= ck_pps;
|
lst_pps <= ck_pps;
|
end
|
end
|
|
|
// Provide a touch of debounce protection ... equal to about
|
// Provide a touch of debounce protection ... equal to about
|
// one quarter of a second.
|
// one quarter of a second.
|
reg [(RW-3):0] tick_enable_counter;
|
reg [(RW-3):0] tick_enable_counter;
|
wire [(RW-1):0] w_tick_enable_sum;
|
wire [(RW-1):0] w_tick_enable_sum;
|
wire w_tick_enable, w_tick_enable_unused;
|
wire w_tick_enable, w_tick_enable_unused;
|
bigadd enabler(i_clk, 1'b0, o_step, { 2'b0, tick_enable_counter },
|
bigadd enabler(i_clk, 1'b0, o_step, { 2'b0, tick_enable_counter },
|
w_tick_enable_sum, w_tick_enable_unused);
|
w_tick_enable_sum, w_tick_enable_unused);
|
initial tick_enable_counter = 0;
|
initial tick_enable_counter = 0;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
begin
|
begin
|
if (tick)
|
if (tick)
|
tick_enable_counter <= 0;
|
tick_enable_counter <= 0;
|
else if (|w_tick_enable_sum[(RW-1):(RW-2)])
|
else if (|w_tick_enable_sum[(RW-1):(RW-2)])
|
tick_enable_counter <= {(RW-2){1'b1}};
|
tick_enable_counter <= {(RW-2){1'b1}};
|
else
|
else
|
tick_enable_counter <= w_tick_enable_sum[(RW-3):0];
|
tick_enable_counter <= w_tick_enable_sum[(RW-3):0];
|
end
|
end
|
assign w_tick_enable = tick_enable_counter[(RW-3)];
|
assign w_tick_enable = tick_enable_counter[(RW-3)];
|
|
|
assign tick= (ck_pps)&&(~lst_pps)&&(w_tick_enable);
|
assign tick= (ck_pps)&&(~lst_pps)&&(w_tick_enable);
|
assign o_dbg[0] = tick;
|
assign o_dbg[0] = tick;
|
assign o_dbg[1] = w_tick_enable;
|
assign o_dbg[1] = w_tick_enable;
|
|
|
//
|
//
|
//
|
//
|
// Here's our counter proper: Add o_step to o_count each clock tick
|
// Here's our counter proper: Add o_step to o_count each clock tick
|
// to have a current time value. Corrections are applied at the top
|
// to have a current time value. Corrections are applied at the top
|
// of the second if we are in tracking mode. The 'o_pps' signal is
|
// of the second if we are in tracking mode. The 'o_pps' signal is
|
// generated from the carry/overflow of the o_count addition.
|
// generated from the carry/overflow of the o_count addition.
|
//
|
//
|
//
|
//
|
reg cnt_carry;
|
reg cnt_carry;
|
reg [31:0] p_count;
|
reg [31:0] p_count;
|
initial o_count = 0;
|
initial o_count = 0;
|
initial o_pps = 1'b0;
|
initial o_pps = 1'b0;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if ((o_tracking)&&(tick))
|
if ((o_tracking)&&(tick))
|
begin
|
begin
|
{ cnt_carry, p_count } <= p_count[31:0] + count_correction[31:0];
|
{ cnt_carry, p_count } <= p_count[31:0] + count_correction[31:0];
|
if (~count_correction[(RW-1)])
|
if (~count_correction[(RW-1)])
|
begin
|
begin
|
// Note that we don't create an o_pps just
|
// Note that we don't create an o_pps just
|
// because the gps_pps states that there should
|
// because the gps_pps states that there should
|
// be one. Instead, we hold to the normal
|
// be one. Instead, we hold to the normal
|
// means of business. At the tick, however,
|
// means of business. At the tick, however,
|
// we add both the step and the correction to
|
// we add both the step and the correction to
|
// the current count.
|
// the current count.
|
{ o_pps, o_count[63:32] } <= o_count[63:32] +count_correction[63:32]+ { 31'h00, cnt_carry };
|
{ o_pps, o_count[63:32] } <= o_count[63:32] +count_correction[63:32]+ { 31'h00, cnt_carry };
|
end else begin
|
end else begin
|
// If the count correction is negative, it means
|
// If the count correction is negative, it means
|
// we need to go backwards. In this case,
|
// we need to go backwards. In this case,
|
// there shouldn't be any o_pps, least we get
|
// there shouldn't be any o_pps, least we get
|
// two of them.
|
// two of them.
|
o_pps <= 1'b0;
|
o_pps <= 1'b0;
|
o_count[63:32] <= o_count[63:32] + count_correction[63:32];
|
o_count[63:32] <= o_count[63:32] + count_correction[63:32];
|
end
|
end
|
end else begin
|
end else begin
|
// The difference between count_correction and
|
// The difference between count_correction and
|
// o_step is the phase correction from the last tick.
|
// o_step is the phase correction from the last tick.
|
// If we aren't tracking, we don't want to use the
|
// If we aren't tracking, we don't want to use the
|
// correction. Likewise, even if we are, we only
|
// correction. Likewise, even if we are, we only
|
// want to use it on the ticks.
|
// want to use it on the ticks.
|
{ cnt_carry, p_count } <= p_count + o_step[31:0];
|
{ cnt_carry, p_count } <= p_count + o_step[31:0];
|
{ o_pps, o_count[63:32] } <= o_count[63:32] + o_step[63:32];
|
{ o_pps, o_count[63:32] } <= o_count[63:32] + o_step[63:32];
|
end
|
end
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
o_count[31:0] <= p_count;
|
o_count[31:0] <= p_count;
|
|
|
reg [(HRW):0] step_correction_plus_carry;
|
reg [(HRW):0] step_correction_plus_carry;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
step_correction_plus_carry = step_correction + { 31'h00, delayed_carry };
|
step_correction_plus_carry = step_correction + { 31'h00, delayed_carry };
|
|
|
wire w_step_correct_unused;
|
wire w_step_correct_unused;
|
wire [(RW-1):0] new_step;
|
wire [(RW-1):0] new_step;
|
bigadd getnewstep(i_clk, 1'b0, o_step,
|
bigadd getnewstep(i_clk, 1'b0, o_step,
|
{ { (HRW-1){step_correction_plus_carry[HRW]} },
|
{ { (HRW-1){step_correction_plus_carry[HRW]} },
|
step_correction_plus_carry},
|
step_correction_plus_carry},
|
new_step, w_step_correct_unused);
|
new_step, w_step_correct_unused);
|
|
|
reg delayed_carry;
|
reg delayed_carry;
|
initial delayed_carry = 0;
|
initial delayed_carry = 0;
|
initial o_step = 64'h002af31dc461;
|
initial o_step = 64'h002af31dc461;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if ((i_rst)||(dly_config))
|
if ((i_rst)||(dly_config))
|
o_step <= pre_step;
|
o_step <= pre_step;
|
else if ((o_tracking) && (tick))
|
else if ((o_tracking) && (tick))
|
o_step <= new_step;
|
o_step <= new_step;
|
|
|
initial delayed_step = 0;
|
initial delayed_step = 0;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if ((i_rst)||(dly_config))
|
if ((i_rst)||(dly_config))
|
delayed_step <= 0;
|
delayed_step <= 0;
|
else if (delay_step_clk)
|
else if (delay_step_clk)
|
{ delayed_carry, delayed_step } <= delayed_step
|
{ delayed_carry, delayed_step } <= delayed_step
|
+ delayed_step_correction;
|
+ delayed_step_correction;
|
|
|
|
|
|
|
//
|
//
|
//
|
//
|
// Now to start our tracking loop. The steps are:
|
// Now to start our tracking loop. The steps are:
|
// 1. Measure our error
|
// 1. Measure our error
|
// 2. Filter our error (lowpass, recursive averager)
|
// 2. Filter our error (lowpass, recursive averager)
|
// 3. Multiply the filtered error by two user-supplied constants
|
// 3. Multiply the filtered error by two user-supplied constants
|
// (beta and gamma)
|
// (beta and gamma)
|
// 4. The results of this multiply then become the new
|
// 4. The results of this multiply then become the new
|
// count and step corrections.
|
// count and step corrections.
|
//
|
//
|
//
|
//
|
// A negative error means we were too fast ... the count rolled over
|
// A negative error means we were too fast ... the count rolled over
|
// and is near zero, the o_err is then the negation of this when the
|
// and is near zero, the o_err is then the negation of this when the
|
// tick does show up.
|
// tick does show up.
|
//
|
//
|
initial o_err = 0;
|
initial o_err = 0;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (tick)
|
if (tick)
|
o_err <= ONE_SECOND - o_count;
|
o_err <= ONE_SECOND - o_count;
|
|
|
initial err_tick = 1'b0;
|
initial err_tick = 1'b0;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
err_tick <= tick;
|
err_tick <= tick;
|
|
|
bigsub suberri(i_clk, err_tick, o_err,
|
bigsub suberri(i_clk, err_tick, o_err,
|
filtered_err, filter_sub_count, sub_tick);
|
filtered_err, filter_sub_count, sub_tick);
|
|
|
//
|
//
|
// This shouldn't be required: We only want to shift our
|
// This shouldn't be required: We only want to shift our
|
// filter_sub_count by r_alpha bits, why the extra struggles?
|
// filter_sub_count by r_alpha bits, why the extra struggles?
|
// Why is because Verilator decides that these values are unsigned,
|
// Why is because Verilator decides that these values are unsigned,
|
// and so despite being told that they are signed values, verilator
|
// and so despite being told that they are signed values, verilator
|
// doesn't sign extend them upon shifting. Put together,
|
// doesn't sign extend them upon shifting. Put together,
|
// { shift_hi[low-bits], shift_lo[low-bits] } make up a full RW
|
// { shift_hi[low-bits], shift_lo[low-bits] } make up a full RW
|
// bit correction factor.
|
// bit correction factor.
|
reg signed [(RW-1):0] shift_hi, shift_lo;
|
reg signed [(RW-1):0] shift_hi, shift_lo;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
begin
|
begin
|
shift_hi <= { {(HRW){filter_sub_count[(RW-1)]}},
|
shift_hi <= { {(HRW){filter_sub_count[(RW-1)]}},
|
filter_sub_count[(RW-1):HRW] }>>r_alpha;
|
filter_sub_count[(RW-1):HRW] }>>r_alpha;
|
shift_lo <= filter_sub_count[(RW-1):0]>>r_alpha;
|
shift_lo <= filter_sub_count[(RW-1):0]>>r_alpha;
|
end
|
end
|
|
|
bigadd adderr(i_clk, sub_tick, filtered_err,
|
bigadd adderr(i_clk, sub_tick, filtered_err,
|
{ shift_hi[(HRW-1):0], shift_lo[(HRW-1):0] },
|
{ shift_hi[(HRW-1):0], shift_lo[(HRW-1):0] },
|
filtered_err, fltr_tick);
|
filtered_err, fltr_tick);
|
/*
|
/*
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if ((o_tracking)&&(sub_tick))
|
if ((o_tracking)&&(sub_tick))
|
filtered_err<= filtered_err
|
filtered_err<= filtered_err
|
+ { shift_hi[(HRW-1):0], shift_lo[(HRW-1):0] };
|
+ { shift_hi[(HRW-1):0], shift_lo[(HRW-1):0] };
|
*/
|
*/
|
|
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (fltr_tick)
|
if (fltr_tick)
|
mpy_input <= r_beta;
|
mpy_input <= r_beta;
|
else
|
else
|
mpy_input <= r_gamma;
|
mpy_input <= r_gamma;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
mpy_aux <= fltr_tick;
|
mpy_aux <= fltr_tick;
|
|
|
//
|
//
|
// The multiply
|
// The multiply
|
//
|
//
|
wire mpy_sync;
|
wire mpy_sync;
|
wire [(RW-1):0] mpy_out;
|
wire [(RW-1):0] mpy_out;
|
initial mpy_sync_two = 1'b0;
|
initial mpy_sync_two = 1'b0;
|
// Sign extend all inputs to RW bits
|
// Sign extend all inputs to RW bits
|
wire signed [(RW-1):0] w_mpy_input, w_mpy_err;
|
wire signed [(RW-1):0] w_mpy_input, w_mpy_err;
|
assign w_mpy_input = { {(RW-DW){mpy_input[(DW-1)]}}, mpy_input[(DW-1):0]};
|
assign w_mpy_input = { {(RW-DW){mpy_input[(DW-1)]}}, mpy_input[(DW-1):0]};
|
assign w_mpy_err = { {(RW-NPW){filtered_err[(RW-1)]}}, filtered_err[(RW-1):(RW-NPW)]};
|
assign w_mpy_err = { {(RW-NPW){filtered_err[(RW-1)]}}, filtered_err[(RW-1):(RW-NPW)]};
|
bigsmpy mpyi(i_clk, mpy_aux, 1'b1, w_mpy_input[31:0], w_mpy_err[31:0],
|
bigsmpy mpyi(i_clk, mpy_aux, 1'b1, w_mpy_input[31:0], w_mpy_err[31:0],
|
mpy_out, mpy_sync);
|
mpy_out, mpy_sync);
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
mpy_sync_two <= mpy_sync;
|
mpy_sync_two <= mpy_sync;
|
assign w_mpy_out = mpy_out;
|
assign w_mpy_out = mpy_out;
|
|
|
// The post-multiply
|
// The post-multiply
|
initial pre_count_correction = 0;
|
initial pre_count_correction = 0;
|
initial step_correction = 0;
|
initial step_correction = 0;
|
initial delayed_step_correction = 0;
|
initial delayed_step_correction = 0;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (mpy_sync)
|
if (mpy_sync)
|
pre_count_correction <= w_mpy_out;
|
pre_count_correction <= w_mpy_out;
|
else if (mpy_sync_two) begin
|
else if (mpy_sync_two) begin
|
step_correction <= w_mpy_out[(RW-1):HRW];
|
step_correction <= w_mpy_out[(RW-1):HRW];
|
delayed_step_correction <= w_mpy_out[(HRW-1):0];
|
delayed_step_correction <= w_mpy_out[(HRW-1):0];
|
end
|
end
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
count_correction <= pre_count_correction + o_step;
|
count_correction <= pre_count_correction + o_step;
|
|
|
initial delay_step_clk = 1'b0;
|
initial delay_step_clk = 1'b0;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
delay_step_clk <= mpy_sync_two;
|
delay_step_clk <= mpy_sync_two;
|
|
|
//
|
//
|
//
|
//
|
// LED Logic -- Note that this is where we tell if we've had a GPS
|
// LED Logic -- Note that this is where we tell if we've had a GPS
|
// 1PPS pulse or not. To have had such a pulse, it needs to have
|
// 1PPS pulse or not. To have had such a pulse, it needs to have
|
// been within the last two seconds.
|
// been within the last two seconds.
|
//
|
//
|
//
|
//
|
reg no_pulse;
|
reg no_pulse;
|
reg [32:0] time_since_pps;
|
reg [32:0] time_since_pps;
|
initial no_pulse = 1'b1;
|
initial no_pulse = 1'b1;
|
initial time_since_pps = 33'hffffffff;
|
initial time_since_pps = 33'hffffffff;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (tick)
|
if (tick)
|
begin
|
begin
|
time_since_pps <= 0;
|
time_since_pps <= 0;
|
no_pulse <= 0;
|
no_pulse <= 0;
|
end else if (time_since_pps[32:29] == 4'hf)
|
end else if (time_since_pps[32:29] == 4'hf)
|
begin
|
begin
|
time_since_pps <= 33'hffffffff;
|
time_since_pps <= 33'hffffffff;
|
no_pulse <= 1'b1;
|
no_pulse <= 1'b1;
|
end else
|
end else
|
time_since_pps <= time_since_pps + pre_step[(RW-1):HRW];
|
time_since_pps <= time_since_pps + pre_step[(RW-1):HRW];
|
|
|
//
|
//
|
// 1. Pulse with a 50% duty cycle every second if no GPS is available.
|
// 1. Pulse with a 50% duty cycle every second if no GPS is available.
|
// 2. Pulse with a 6% duty cycle any time a pulse is present, and any
|
// 2. Pulse with a 6% duty cycle any time a pulse is present, and any
|
// time we think (when a pulse is present) that we have time.
|
// time we think (when a pulse is present) that we have time.
|
//
|
//
|
// This should produce a set of conflicting pulses when out of lock,
|
// This should produce a set of conflicting pulses when out of lock,
|
// and a nice short once per second pulse when locked. Further, you
|
// and a nice short once per second pulse when locked. Further, you
|
// should be able to tell when the core is flywheeling by the duration
|
// should be able to tell when the core is flywheeling by the duration
|
// of the pulses (50% vs 6%).
|
// of the pulses (50% vs 6%).
|
//
|
//
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (no_pulse)
|
if (no_pulse)
|
o_led <= o_count[(RW-1)];
|
o_led <= o_count[(RW-1)];
|
else
|
else
|
o_led <= ((time_since_pps[31:28] == 4'h0)
|
o_led <= ((time_since_pps[31:28] == 4'h0)
|
||(o_count[(RW-1):(RW-4)]== 4'h0));
|
||(o_count[(RW-1):(RW-4)]== 4'h0));
|
|
|
//
|
//
|
//
|
//
|
// Now, are we tracking or not?
|
// Now, are we tracking or not?
|
// We'll attempt to close the loop after seeing 7 valid GPS 1PPS
|
// We'll attempt to close the loop after seeing 7 valid GPS 1PPS
|
// rising edges.
|
// rising edges.
|
//
|
//
|
//
|
//
|
reg [2:0] count_valid_ticks;
|
reg [2:0] count_valid_ticks;
|
initial count_valid_ticks = 3'h0;
|
initial count_valid_ticks = 3'h0;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if ((tick)&&(count_valid_ticks < 3'h7))
|
if ((tick)&&(count_valid_ticks < 3'h7))
|
count_valid_ticks <= count_valid_ticks+1;
|
count_valid_ticks <= count_valid_ticks+1;
|
else if (no_pulse)
|
else if (no_pulse)
|
count_valid_ticks <= 3'h0;
|
count_valid_ticks <= 3'h0;
|
initial o_tracking = 1'b0;
|
initial o_tracking = 1'b0;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if ((tick)&&(&count_valid_ticks))
|
if ((tick)&&(&count_valid_ticks))
|
o_tracking <= 1'b1;
|
o_tracking <= 1'b1;
|
else if ((tick)||(count_valid_ticks == 0))
|
else if ((tick)||(count_valid_ticks == 0))
|
o_tracking <= 1'b0;
|
o_tracking <= 1'b0;
|
|
|
//
|
//
|
//
|
//
|
// Are we locked or not?
|
// Are we locked or not?
|
// We'll use the top eight bits of our error to tell. If the top eight
|
// We'll use the top eight bits of our error to tell. If the top eight
|
// bits are all ones or all zeros, then we'll call ourselves locked.
|
// bits are all ones or all zeros, then we'll call ourselves locked.
|
// This is equivalent to calling ourselves locked if, at the top of
|
// This is equivalent to calling ourselves locked if, at the top of
|
// the second, we are within 1/128th of a second of the GPS 1PPS.
|
// the second, we are within 1/128th of a second of the GPS 1PPS.
|
//
|
//
|
initial o_locked = 1'b0;
|
initial o_locked = 1'b0;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if ((o_tracking)&&(tick)&&(
|
if ((o_tracking)&&(tick)&&(
|
(( o_err[(RW-1)])&&(o_err[(RW-1):(RW-8)]==8'hff))
|
(( o_err[(RW-1)])&&(o_err[(RW-1):(RW-8)]==8'hff))
|
||((~o_err[(RW-1)])&&(o_err[(RW-1):(RW-8)]==8'h00))))
|
||((~o_err[(RW-1)])&&(o_err[(RW-1):(RW-8)]==8'h00))))
|
o_locked <= 1'b1;
|
o_locked <= 1'b1;
|
else if (tick)
|
else if (tick)
|
o_locked <= 1'b0;
|
o_locked <= 1'b0;
|
|
|
endmodule
|
endmodule
|
|
|
|
|