////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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// Filename: toplevel.v
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// Filename: toplevel.v
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//
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//
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// Project: OpenArty, an entirely open SoC based upon the Arty platform
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// Project: OpenArty, an entirely open SoC based upon the Arty platform
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//
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//
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// Purpose: This is the top level Verilog file. It is to be contrasted
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// Purpose: This is the top level Verilog file. It is to be contrasted
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// with the other top level Verilog file in this same project in
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// with the other top level Verilog file in this same project in
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// that *this* top level is designed to create a *safe*, low-speed
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// that *this* top level is designed to create a *safe*, low-speed
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// (80MHz), configuration that can be used to test peripherals and other
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// (80MHz), configuration that can be used to test peripherals and other
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// things on the way to building a full featured high speed (160MHz)
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// things on the way to building a full featured high speed (160MHz)
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// configuration.
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// configuration.
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//
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//
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// Differences between this file and fasttop.v should be limited to speed
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// Differences between this file and fasttop.v should be limited to speed
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// related differences (such as the number of counts per UART baud), and
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// related differences (such as the number of counts per UART baud), and
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// the different daughter module: fastmaster.v (for 200MHz designs) vs
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// the different daughter module: fastmaster.v (for 200MHz designs) vs
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// busmaster.v (for 100MHz designs).
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// busmaster.v (for 100MHz designs).
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//
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//
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// Creator: Dan Gisselquist, Ph.D.
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// Creator: Dan Gisselquist, Ph.D.
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// Gisselquist Technology, LLC
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// Gisselquist Technology, LLC
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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// Copyright (C) 2015-2016, Gisselquist Technology, LLC
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// Copyright (C) 2015-2016, Gisselquist Technology, LLC
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//
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//
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// This program is free software (firmware): you can redistribute it and/or
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of the GNU General Public License as published
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// modify it under the terms of the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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// your option) any later version.
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//
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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// for more details.
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//
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//
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// You should have received a copy of the GNU General Public License along
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// You should have received a copy of the GNU General Public License along
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// with this program. (It's in the $(ROOT)/doc directory, run make with no
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// with this program. (It's in the $(ROOT)/doc directory, run make with no
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// target there if the PDF file isn't present.) If not, see
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// target there if the PDF file isn't present.) If not, see
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// <http://www.gnu.org/licenses/> for a copy.
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// <http://www.gnu.org/licenses/> for a copy.
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//
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//
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// License: GPL, v3, as defined and found on www.gnu.org,
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// License: GPL, v3, as defined and found on www.gnu.org,
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// http://www.gnu.org/licenses/gpl.html
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// http://www.gnu.org/licenses/gpl.html
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//
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//
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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//
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//
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module toplevel(sys_clk_i, i_reset_btn,
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module toplevel(sys_clk_i, i_reset_btn,
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i_sw, // Switches
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i_sw, // Switches
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i_btn, // Buttons
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i_btn, // Buttons
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o_led, // Single color LEDs
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o_led, // Single color LEDs
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o_clr_led0, o_clr_led1, o_clr_led2, o_clr_led3, // Color LEDs
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o_clr_led0, o_clr_led1, o_clr_led2, o_clr_led3, // Color LEDs
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// RS232 UART
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// RS232 UART
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i_uart_rx, o_uart_tx,
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i_uart_rx, o_uart_tx,
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// Quad-SPI Flash control
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// Quad-SPI Flash control
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o_qspi_sck, o_qspi_cs_n, io_qspi_dat,
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o_qspi_sck, o_qspi_cs_n, io_qspi_dat,
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// Missing: Ethernet
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// Ethernet
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o_eth_rstn, o_eth_ref_clk,
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i_eth_rx_clk, i_eth_col, i_eth_crs, i_eth_rx_dv, i_eth_rxd, i_eth_rxerr,
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i_eth_tx_clk, o_eth_tx_en, o_eth_txd,
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// Ethernet (MDIO)
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o_eth_mdclk, io_eth_mdio,
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o_eth_mdclk, io_eth_mdio,
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// Memory
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// Memory
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ddr3_reset_n, ddr3_cke, ddr3_ck_p, ddr3_ck_n,
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ddr3_reset_n, ddr3_cke, ddr3_ck_p, ddr3_ck_n,
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ddr3_cs_n, ddr3_ras_n, ddr3_cas_n, ddr3_we_n,
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ddr3_cs_n, ddr3_ras_n, ddr3_cas_n, ddr3_we_n,
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ddr3_dqs_p, ddr3_dqs_n,
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ddr3_dqs_p, ddr3_dqs_n,
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ddr3_addr, ddr3_ba,
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ddr3_addr, ddr3_ba,
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ddr3_dq, ddr3_dm, ddr3_odt,
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ddr3_dq, ddr3_dm, ddr3_odt,
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// SD Card
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// SD Card
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o_sd_sck, io_sd_cmd, io_sd, i_sd_cs, i_sd_wp,
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o_sd_sck, io_sd_cmd, io_sd, i_sd_cs, i_sd_wp,
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// GPS Pmod
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// GPS Pmod
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i_gps_pps, i_gps_3df, i_gps_rx, o_gps_tx,
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i_gps_pps, i_gps_3df, i_gps_rx, o_gps_tx,
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// OLED Pmod
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// OLED Pmod
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o_oled_sck, o_oled_cs_n, o_oled_mosi, o_oled_dcn, o_oled_reset_n,
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o_oled_sck, o_oled_cs_n, o_oled_mosi, o_oled_dcn, o_oled_reset_n,
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o_oled_vccen, o_oled_pmoden,
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o_oled_vccen, o_oled_pmoden,
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// PMod I/O
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// PMod I/O
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i_aux_rx, i_aux_rts, o_aux_tx, o_aux_cts
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i_aux_rx, i_aux_rts, o_aux_tx, o_aux_cts
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);
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);
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input [0:0] sys_clk_i;
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input [0:0] sys_clk_i;
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input i_reset_btn;
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input i_reset_btn;
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input [3:0] i_sw; // Switches
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input [3:0] i_sw; // Switches
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input [3:0] i_btn; // Buttons
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input [3:0] i_btn; // Buttons
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output wire [3:0] o_led; // LED
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output wire [3:0] o_led; // LED
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output wire [2:0] o_clr_led0, o_clr_led1, o_clr_led2, o_clr_led3;
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output wire [2:0] o_clr_led0, o_clr_led1, o_clr_led2, o_clr_led3;
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// UARTs
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// UARTs
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input i_uart_rx;
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input i_uart_rx;
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output wire o_uart_tx;
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output wire o_uart_tx;
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// Quad SPI flash
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// Quad SPI flash
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output wire o_qspi_sck, o_qspi_cs_n;
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output wire o_qspi_sck, o_qspi_cs_n;
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inout [3:0] io_qspi_dat;
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inout [3:0] io_qspi_dat;
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// Ethernet // Not yet implemented
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// Ethernet
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output wire o_eth_rstn, o_eth_ref_clk;
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input i_eth_rx_clk, i_eth_col, i_eth_crs, i_eth_rx_dv;
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input [3:0] i_eth_rxd;
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input i_eth_rxerr;
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input i_eth_tx_clk;
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output wire o_eth_tx_en;
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output [3:0] o_eth_txd;
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// Ethernet control (MDIO)
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// Ethernet control (MDIO)
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output wire o_eth_mdclk;
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output wire o_eth_mdclk;
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inout wire io_eth_mdio;
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inout wire io_eth_mdio;
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// DDR3 SDRAM
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// DDR3 SDRAM
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output wire ddr3_reset_n;
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output wire ddr3_reset_n;
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output wire [0:0] ddr3_cke;
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output wire [0:0] ddr3_cke;
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output wire [0:0] ddr3_ck_p, ddr3_ck_n;
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output wire [0:0] ddr3_ck_p, ddr3_ck_n;
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output wire [0:0] ddr3_cs_n;
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output wire [0:0] ddr3_cs_n;
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output wire ddr3_ras_n, ddr3_cas_n, ddr3_we_n;
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output wire ddr3_ras_n, ddr3_cas_n, ddr3_we_n;
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output wire [2:0] ddr3_ba;
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output wire [2:0] ddr3_ba;
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output wire [13:0] ddr3_addr;
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output wire [13:0] ddr3_addr;
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output wire [0:0] ddr3_odt;
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output wire [0:0] ddr3_odt;
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output wire [1:0] ddr3_dm;
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output wire [1:0] ddr3_dm;
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inout [1:0] ddr3_dqs_p, ddr3_dqs_n;
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inout [1:0] ddr3_dqs_p, ddr3_dqs_n;
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inout [15:0] ddr3_dq;
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inout [15:0] ddr3_dq;
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//
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//
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// SD Card
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// SD Card
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output wire o_sd_sck;
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output wire o_sd_sck;
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inout io_sd_cmd;
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inout io_sd_cmd;
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inout [3:0] io_sd;
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inout [3:0] io_sd;
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input i_sd_cs;
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input i_sd_cs;
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input i_sd_wp;
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input i_sd_wp;
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// GPS PMod
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// GPS PMod
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input i_gps_pps, i_gps_3df, i_gps_rx;
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input i_gps_pps, i_gps_3df, i_gps_rx;
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output wire o_gps_tx;
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output wire o_gps_tx;
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// OLEDRGB PMod
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// OLEDRGB PMod
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output wire o_oled_sck, o_oled_cs_n, o_oled_mosi,
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output wire o_oled_sck, o_oled_cs_n, o_oled_mosi,
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o_oled_dcn, o_oled_reset_n, o_oled_vccen,
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o_oled_dcn, o_oled_reset_n, o_oled_vccen,
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o_oled_pmoden;
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o_oled_pmoden;
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// Aux UART
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// Aux UART
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input i_aux_rx, i_aux_rts;
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input i_aux_rx, i_aux_rts;
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output wire o_aux_tx, o_aux_cts;
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output wire o_aux_tx, o_aux_cts;
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wire eth_tx_clk, eth_rx_clk;
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`ifdef VERILATOR
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wire s_clk, s_reset;
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assign s_clk = sys_clk_i;
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assign eth_tx_clk = i_eth_tx_clk;
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assign eth_rx_clk = i_eth_rx_clk;
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`else
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// Build our master clock
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// Build our master clock
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wire s_clk, sys_clk, mem_clk_200mhz,
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wire s_clk, sys_clk, mem_clk_200mhz,
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clk1_unused, clk2_unused, enet_clk, clk4_unnused,
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clk1_unused, clk2_unused, enet_clk, clk4_unnused,
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clk5_unused, clk_feedback, clk_locked, mem_clk_200mhz_nobuf;
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clk5_unused, clk_feedback, clk_locked, mem_clk_200mhz_nobuf;
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PLLE2_BASE #(
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PLLE2_BASE #(
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.BANDWIDTH("OPTIMIZED"), // OPTIMIZED, HIGH, LOW
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.BANDWIDTH("OPTIMIZED"), // OPTIMIZED, HIGH, LOW
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.CLKFBOUT_PHASE(0.0), // Phase offset in degrees of CLKFB, (-360-360)
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.CLKFBOUT_PHASE(0.0), // Phase offset in degrees of CLKFB, (-360-360)
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.CLKIN1_PERIOD(10.0), // Input clock period in ns resolution
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.CLKIN1_PERIOD(10.0), // Input clock period in ns resolution
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// CLKOUT0_DIVIDE - CLKOUT5_DIVIDE: divide amount for each CLKOUT(1-128)
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// CLKOUT0_DIVIDE - CLKOUT5_DIVIDE: divide amount for each CLKOUT(1-128)
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.CLKFBOUT_MULT(8), // Multiply value for all CLKOUT (2-64)
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.CLKFBOUT_MULT(8), // Multiply value for all CLKOUT (2-64)
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.CLKOUT0_DIVIDE(8), // 100 MHz (Clock for MIG)
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.CLKOUT0_DIVIDE(8), // 100 MHz (Clock for MIG)
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.CLKOUT1_DIVIDE(4), // 200 MHz (MIG Reference clock)
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.CLKOUT1_DIVIDE(4), // 200 MHz (MIG Reference clock)
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.CLKOUT2_DIVIDE(32), // 50 MHz (Unused)
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.CLKOUT2_DIVIDE(16), // 50 MHz (Unused)
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.CLKOUT3_DIVIDE(64), // 25 MHz (Unused/Ethernet clock)
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.CLKOUT3_DIVIDE(32), // 25 MHz (Ethernet reference clk)
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.CLKOUT4_DIVIDE(32), // 50 MHz (Unused clock?)
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.CLKOUT4_DIVIDE(32), // 50 MHz (Unused clock?)
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.CLKOUT5_DIVIDE(24), // 66 MHz
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.CLKOUT5_DIVIDE(24), // 66 MHz
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// CLKOUT0_DUTY_CYCLE -- Duty cycle for each CLKOUT
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// CLKOUT0_DUTY_CYCLE -- Duty cycle for each CLKOUT
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.CLKOUT0_DUTY_CYCLE(0.5),
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.CLKOUT0_DUTY_CYCLE(0.5),
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.CLKOUT1_DUTY_CYCLE(0.5),
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.CLKOUT1_DUTY_CYCLE(0.5),
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.CLKOUT2_DUTY_CYCLE(0.5),
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.CLKOUT2_DUTY_CYCLE(0.5),
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.CLKOUT3_DUTY_CYCLE(0.5),
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.CLKOUT3_DUTY_CYCLE(0.5),
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.CLKOUT4_DUTY_CYCLE(0.5),
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.CLKOUT4_DUTY_CYCLE(0.5),
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.CLKOUT5_DUTY_CYCLE(0.5),
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.CLKOUT5_DUTY_CYCLE(0.5),
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// CLKOUT0_PHASE -- phase offset for each CLKOUT
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// CLKOUT0_PHASE -- phase offset for each CLKOUT
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.CLKOUT0_PHASE(0.0),
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.CLKOUT0_PHASE(0.0),
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.CLKOUT1_PHASE(0.0),
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.CLKOUT1_PHASE(0.0),
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.CLKOUT2_PHASE(0.0),
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.CLKOUT2_PHASE(0.0),
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.CLKOUT3_PHASE(0.0),
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.CLKOUT3_PHASE(0.0),
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.CLKOUT4_PHASE(0.0),
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.CLKOUT4_PHASE(0.0),
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.CLKOUT5_PHASE(0.0),
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.CLKOUT5_PHASE(0.0),
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.DIVCLK_DIVIDE(1), // Master division value , (1-56)
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.DIVCLK_DIVIDE(1), // Master division value , (1-56)
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.REF_JITTER1(0.0), // Ref. input jitter in UI (0.000-0.999)
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.REF_JITTER1(0.0), // Ref. input jitter in UI (0.000-0.999)
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.STARTUP_WAIT("TRUE") // Delay DONE until PLL Locks, ("TRUE"/"FALSE")
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.STARTUP_WAIT("TRUE") // Delay DONE until PLL Locks, ("TRUE"/"FALSE")
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) genclock(
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) genclock(
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// Clock outputs: 1-bit (each) output
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// Clock outputs: 1-bit (each) output
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.CLKOUT0(mem_clk_nobuf),
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.CLKOUT0(mem_clk_nobuf),
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.CLKOUT1(mem_clk_200mhz_nobuf),
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.CLKOUT1(mem_clk_200mhz_nobuf),
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.CLKOUT2(clk2_unused),
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.CLKOUT2(clk2_unused),
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.CLKOUT3(enet_clk),
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.CLKOUT3(enet_clk),
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.CLKOUT4(clk4_unused),
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.CLKOUT4(clk4_unused),
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.CLKOUT5(clk5_unused),
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.CLKOUT5(clk5_unused),
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.CLKFBOUT(clk_feedback), // 1-bit output, feedback clock
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.CLKFBOUT(clk_feedback), // 1-bit output, feedback clock
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.LOCKED(clk_locked),
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.LOCKED(clk_locked),
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.CLKIN1(sys_clk),
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.CLKIN1(sys_clk),
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.PWRDWN(1'b0),
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.PWRDWN(1'b0),
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.RST(1'b0),
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.RST(1'b0),
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.CLKFBIN(clk_feedback_bufd) // 1-bit input, feedback clock
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.CLKFBIN(clk_feedback_bufd) // 1-bit input, feedback clock
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);
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);
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BUFH feedback_buffer(.I(clk_feedback),.O(clk_feedback_bufd));
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BUFH feedback_buffer(.I(clk_feedback),.O(clk_feedback_bufd));
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// BUFG memref_buffer(.I(mem_clk_200mhz_nobuf),.O(mem_clk_200mhz));
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// BUFG memref_buffer(.I(mem_clk_200mhz_nobuf),.O(mem_clk_200mhz));
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IBUF sysclk_buf(.I(sys_clk_i[0]), .O(sys_clk));
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IBUF sysclk_buf(.I(sys_clk_i[0]), .O(sys_clk));
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BUFG eth_rx(.I(i_eth_rx_clk), .O(eth_rx_clk));
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// assign eth_rx_clk = i_eth_rx_clk;
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BUFG eth_tx(.I(i_eth_tx_clk), .O(eth_tx_clk));
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// assign eth_tx_clk = i_eth_tx_clk;
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`endif
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//
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//
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//
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//
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// UART interface
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// UART interface
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//
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//
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//
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//
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wire [29:0] bus_uart_setup;
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wire [29:0] bus_uart_setup;
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// assign bus_uart_setup = 30'h10000014; // ~4MBaud, 7 bits
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// assign bus_uart_setup = 30'h10000014; // ~4MBaud, 7 bits
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assign bus_uart_setup = 30'h10000051; // ~1MBaud, 7 bits
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assign bus_uart_setup = 30'h10000051; // ~1MBaud, 7 bits
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wire [7:0] rx_data, tx_data;
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wire [7:0] rx_data, tx_data;
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wire rx_break, rx_parity_err, rx_frame_err, rx_stb;
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wire rx_break, rx_parity_err, rx_frame_err, rx_stb;
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wire tx_stb, tx_busy;
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wire tx_stb, tx_busy;
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|
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//
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//
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// RESET LOGIC
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// RESET LOGIC
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//
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//
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// Okay, so this looks bad at a first read--but it's not really that
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// Okay, so this looks bad at a first read--but it's not really that
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// bad. If you look close, there are two parts to the reset logic.
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// bad. If you look close, there are two parts to the reset logic.
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// The first is the "PRE"-reset. This is a wire, set from the external
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// The first is the "PRE"-reset. This is a wire, set from the external
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// reset button. In good old-fashioned asynch-logic to synchronous
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// reset button. In good old-fashioned asynch-logic to synchronous
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// logic fashion, we synchronize this wire by registering it first
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// logic fashion, we synchronize this wire by registering it first
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// to pre_reset, and then to pwr_reset (the actual reset wire).
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// to pre_reset, and then to pwr_reset (the actual reset wire).
|
//
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//
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|
wire s_reset; // Ultimate system reset wire
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reg [7:0] pre_reset;
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reg [7:0] pre_reset;
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reg pwr_reset;
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reg pwr_reset;
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// Since all our stuff is synchronous to the clock that comes out of
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// Since all our stuff is synchronous to the clock that comes out of
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// the memory controller, sys_reset must needs come out of the memory
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// the memory controller, sys_reset must needs come out of the memory
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// controller.
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// controller.
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//
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//
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// Logic description starts with the PRE-reset, so as to make certain
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// Logic description starts with the PRE-reset, so as to make certain
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// we include the reset button. The memory controller wants an active
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// we include the reset button. The memory controller wants an active
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// low reset here, so we provide such.
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// low reset here, so we provide such.
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initial pre_reset = 1'b0;
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initial pre_reset = 1'b0;
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always @(posedge sys_clk)
|
always @(posedge sys_clk)
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pre_reset <= ((!i_reset_btn)||(!clk_locked))
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pre_reset <= ((!i_reset_btn)||(!clk_locked))
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? 8'h00 : {pre_reset[6:0], 1'b1};
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? 8'h00 : {pre_reset[6:0], 1'b1};
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//
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//
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// and then continues with the actual reset, now that we've
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// and then continues with the actual reset, now that we've
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// synchronized our reset button wire. This is an active LOW reset.
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// synchronized our reset button wire. This is an active LOW reset.
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initial pwr_reset = 1'b0;
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initial pwr_reset = 1'b0;
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always @(posedge sys_clk)
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always @(posedge sys_clk)
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pwr_reset <= pre_reset[7];
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pwr_reset <= pre_reset[7];
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|
`ifdef VERILATOR
|
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assign s_reset = pwr_reset;
|
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`else
|
//
|
//
|
// Of course, this only goes into the memory controller. The true
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// Of course, this only goes into the memory controller. The true
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// device reset comes out of that memory controller, synchronized to
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// device reset comes out of that memory controller, synchronized to
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// our memory generator provided clock(s)
|
// our memory generator provided clock(s)
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`endif
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|
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wire w_ck_uart, w_uart_tx;
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wire w_ck_uart, w_uart_tx;
|
rxuart rcv(s_clk, s_reset, bus_uart_setup, i_uart_rx,
|
rxuart rcv(s_clk, s_reset, bus_uart_setup, i_uart_rx,
|
rx_stb, rx_data, rx_break,
|
rx_stb, rx_data, rx_break,
|
rx_parity_err, rx_frame_err, w_ck_uart);
|
rx_parity_err, rx_frame_err, w_ck_uart);
|
txuart txv(s_clk, s_reset, bus_uart_setup|30'h8000000, 1'b0,
|
txuart txv(s_clk, s_reset, bus_uart_setup|30'h8000000, 1'b0,
|
tx_stb, tx_data, o_uart_tx, tx_busy);
|
tx_stb, tx_data, o_uart_tx, tx_busy);
|
|
|
|
|
wire [3:0] w_led;
|
wire [3:0] w_led;
|
reg [24:0] dbg_counter;
|
reg [24:0] dbg_counter;
|
always @(posedge sys_clk)
|
always @(posedge sys_clk)
|
dbg_counter <= dbg_counter + 25'h01;
|
dbg_counter <= dbg_counter + 25'h01;
|
assign o_led = { w_led[3:2],
|
assign o_led = { w_led[3:2],
|
((!pwr_reset)&(dbg_counter[24]))
|
((!pwr_reset)&(dbg_counter[24]))
|
||((pwr_reset)&&(w_led[1])),
|
||((pwr_reset)&&(w_led[1])),
|
(s_reset & dbg_counter[23])
|
(s_reset & dbg_counter[23])
|
||((!s_reset)&&(w_led[0])) };
|
||((!s_reset)&&(w_led[0])) };
|
|
|
|
|
|
|
//////
|
//////
|
//
|
//
|
//
|
//
|
// The WB bus interconnect, herein called busmaster, which handles
|
// The WB bus interconnect, herein called busmaster, which handles
|
// just about ... everything. It is in contrast to the other WB bus
|
// just about ... everything. It is in contrast to the other WB bus
|
// interconnect, fastmaster, in that the busmaster build permits
|
// interconnect, fastmaster, in that the busmaster build permits
|
// peripherals that can *only* operate at 80MHz, no faster, no slower.
|
// peripherals that can *only* operate at 80MHz, no faster, no slower.
|
//
|
//
|
//
|
//
|
//////
|
//////
|
wire w_qspi_sck, w_qspi_cs_n;
|
wire w_qspi_sck, w_qspi_cs_n;
|
wire [1:0] qspi_bmod;
|
wire [1:0] qspi_bmod;
|
wire [3:0] qspi_dat;
|
wire [3:0] qspi_dat;
|
wire [3:0] i_qspi_dat;
|
wire [3:0] i_qspi_dat;
|
|
|
//
|
//
|
// The SDRAM interface wires
|
// The SDRAM interface wires
|
//
|
//
|
wire ram_cyc, ram_stb, ram_we;
|
wire ram_cyc, ram_stb, ram_we;
|
wire [25:0] ram_addr;
|
wire [25:0] ram_addr;
|
wire [31:0] ram_rdata, ram_wdata;
|
wire [31:0] ram_rdata, ram_wdata;
|
wire ram_ack, ram_stall, ram_err;
|
wire ram_ack, ram_stall, ram_err;
|
wire [31:0] ram_dbg;
|
wire [31:0] ram_dbg;
|
//
|
//
|
wire w_mdio, w_mdwe;
|
wire w_mdio, w_mdwe;
|
//
|
//
|
wire w_sd_cmd;
|
wire w_sd_cmd;
|
wire [3:0] w_sd_data;
|
wire [3:0] w_sd_data;
|
busmaster wbbus(s_clk, s_reset,
|
busmaster wbbus(s_clk, s_reset,
|
// External USB-UART bus control
|
// External USB-UART bus control
|
rx_stb, rx_data, tx_stb, tx_data, tx_busy,
|
rx_stb, rx_data, tx_stb, tx_data, tx_busy,
|
// Board lights and switches
|
// Board lights and switches
|
i_sw, i_btn, w_led,
|
i_sw, i_btn, w_led,
|
o_clr_led0, o_clr_led1, o_clr_led2, o_clr_led3,
|
o_clr_led0, o_clr_led1, o_clr_led2, o_clr_led3,
|
// Board level PMod I/O
|
// Board level PMod I/O
|
i_aux_rx, o_aux_tx, o_aux_cts, i_gps_rx, o_gps_tx,
|
i_aux_rx, o_aux_tx, o_aux_cts, i_gps_rx, o_gps_tx,
|
// Quad SPI flash
|
// Quad SPI flash
|
w_qspi_cs_n, w_qspi_sck, qspi_dat, i_qspi_dat, qspi_bmod,
|
w_qspi_cs_n, w_qspi_sck, qspi_dat, i_qspi_dat, qspi_bmod,
|
// DDR3 SDRAM
|
// DDR3 SDRAM
|
// o_ddr_reset_n, o_ddr_cke, o_ddr_ck_p, o_ddr_ck_n,
|
// o_ddr_reset_n, o_ddr_cke, o_ddr_ck_p, o_ddr_ck_n,
|
// o_ddr_cs_n, o_ddr_ras_n, o_ddr_cas_n, o_ddr_we_n,
|
// o_ddr_cs_n, o_ddr_ras_n, o_ddr_cas_n, o_ddr_we_n,
|
// o_ddr_ba, o_ddr_addr, o_ddr_odt, o_ddr_dm,
|
// o_ddr_ba, o_ddr_addr, o_ddr_odt, o_ddr_dm,
|
// io_ddr_dqs_p, io_ddr_dqs_n, io_ddr_data,
|
// io_ddr_dqs_p, io_ddr_dqs_n, io_ddr_data,
|
ram_cyc, ram_stb, ram_we, ram_addr, ram_wdata,
|
ram_cyc, ram_stb, ram_we, ram_addr, ram_wdata,
|
ram_ack, ram_stall, ram_rdata, ram_err,
|
ram_ack, ram_stall, ram_rdata, ram_err,
|
ram_dbg,
|
ram_dbg,
|
// SD Card
|
// SD Card
|
o_sd_sck, w_sd_cmd, w_sd_data, io_sd_cmd, io_sd, i_sd_cs,
|
o_sd_sck, w_sd_cmd, w_sd_data, io_sd_cmd, io_sd, i_sd_cs,
|
|
// Ethernet
|
|
o_eth_rstn,
|
|
eth_rx_clk, i_eth_col, i_eth_crs, i_eth_rx_dv,
|
|
i_eth_rxd, i_eth_rxerr,
|
|
eth_tx_clk, o_eth_tx_en, o_eth_txd,
|
// Ethernet control (MDIO) lines
|
// Ethernet control (MDIO) lines
|
o_eth_mdclk, w_mdio, w_mdwe, io_eth_mdio,
|
o_eth_mdclk, w_mdio, w_mdwe, io_eth_mdio,
|
// OLEDRGB PMod wires
|
// OLEDRGB PMod wires
|
o_oled_sck, o_oled_cs_n, o_oled_mosi, o_oled_dcn,
|
o_oled_sck, o_oled_cs_n, o_oled_mosi, o_oled_dcn,
|
o_oled_reset_n, o_oled_vccen, o_oled_pmoden,
|
o_oled_reset_n, o_oled_vccen, o_oled_pmoden,
|
// GPS PMod
|
// GPS PMod
|
i_gps_pps, i_gps_3df
|
i_gps_pps, i_gps_3df
|
);
|
);
|
|
|
//////
|
//////
|
//
|
//
|
//
|
//
|
// The rest of this file *should* be identical to fasttop.v. Any
|
// The rest of this file *should* be identical to fasttop.v. Any
|
// differences should be worked out with meld or some such program
|
// differences should be worked out with meld or some such program
|
// to keep them to a minimum.
|
// to keep them to a minimum.
|
//
|
//
|
//
|
//
|
// Some wires need special treatment, and so are not quite completely
|
// Some wires need special treatment, and so are not quite completely
|
// handled by the bus master. These are handled below.
|
// handled by the bus master. These are handled below.
|
//
|
//
|
//
|
//
|
//////
|
//////
|
|
|
//
|
//
|
//
|
//
|
// QSPI)BMOD, Quad SPI bus mode, Bus modes are:
|
// QSPI)BMOD, Quad SPI bus mode, Bus modes are:
|
// 0? Normal serial mode, one bit in one bit out
|
// 0? Normal serial mode, one bit in one bit out
|
// 10 Quad SPI mode, going out
|
// 10 Quad SPI mode, going out
|
// 11 Quad SPI mode coming from the device (read mode)
|
// 11 Quad SPI mode coming from the device (read mode)
|
//
|
//
|
// ?? Dual mode in (not yet)
|
// ?? Dual mode in (not yet)
|
// ?? Dual mode out (not yet)
|
// ?? Dual mode out (not yet)
|
//
|
//
|
//
|
//
|
wire [3:0] i_qspi_pedge, i_qspi_nedge;
|
wire [3:0] i_qspi_pedge, i_qspi_nedge;
|
|
|
|
`ifdef VERILATOR
|
|
assign o_qspi_sck = w_qspi_sck;
|
|
assign o_qspi_cs_n = w_qspi_cs_n;
|
|
;
|
|
();
|
|
[*];
|
|
`else
|
xoddr xqspi_sck( s_clk, { w_qspi_sck, w_qspi_sck }, o_qspi_sck);
|
xoddr xqspi_sck( s_clk, { w_qspi_sck, w_qspi_sck }, o_qspi_sck);
|
xoddr xqspi_csn( s_clk, { w_qspi_cs_n, w_qspi_cs_n },o_qspi_cs_n);
|
xoddr xqspi_csn( s_clk, { w_qspi_cs_n, w_qspi_cs_n },o_qspi_cs_n);
|
//
|
//
|
xioddr xqspi_d0( s_clk, (qspi_bmod != 2'b11),
|
xioddr xqspi_d0( s_clk, (qspi_bmod != 2'b11),
|
{ qspi_dat[0], qspi_dat[0] },
|
{ qspi_dat[0], qspi_dat[0] },
|
{ i_qspi_pedge[0], i_qspi_nedge[0] }, io_qspi_dat[0]);
|
{ i_qspi_pedge[0], i_qspi_nedge[0] }, io_qspi_dat[0]);
|
xioddr xqspi_d1( s_clk, (qspi_bmod==2'b10),
|
xioddr xqspi_d1( s_clk, (qspi_bmod==2'b10),
|
{ qspi_dat[1], qspi_dat[1] },
|
{ qspi_dat[1], qspi_dat[1] },
|
{ i_qspi_pedge[1], i_qspi_nedge[1] }, io_qspi_dat[1]);
|
{ i_qspi_pedge[1], i_qspi_nedge[1] }, io_qspi_dat[1]);
|
xioddr xqspi_d2( s_clk, (qspi_bmod!=2'b11),
|
xioddr xqspi_d2( s_clk, (qspi_bmod!=2'b11),
|
(qspi_bmod[1])?{ qspi_dat[2], qspi_dat[2] }:2'b11,
|
(qspi_bmod[1])?{ qspi_dat[2], qspi_dat[2] }:2'b11,
|
{ i_qspi_pedge[2], i_qspi_nedge[2] }, io_qspi_dat[2]);
|
{ i_qspi_pedge[2], i_qspi_nedge[2] }, io_qspi_dat[2]);
|
xioddr xqspi_d3( s_clk, (qspi_bmod!=2'b11),
|
xioddr xqspi_d3( s_clk, (qspi_bmod!=2'b11),
|
(qspi_bmod[1])?{ qspi_dat[3], qspi_dat[3] }:2'b11,
|
(qspi_bmod[1])?{ qspi_dat[3], qspi_dat[3] }:2'b11,
|
{ i_qspi_pedge[3], i_qspi_nedge[3] }, io_qspi_dat[3]);
|
{ i_qspi_pedge[3], i_qspi_nedge[3] }, io_qspi_dat[3]);
|
|
`endif
|
|
reg [3:0] r_qspi_dat;
|
|
always @(posedge s_clk)
|
|
r_qspi_dat <= i_qspi_pedge;
|
|
assign i_qspi_dat = r_qspi_dat;
|
|
|
assign i_qspi_dat = i_qspi_pedge;
|
|
//
|
//
|
// Proposed QSPI mode select, to allow dual I/O mode
|
// Proposed QSPI mode select, to allow dual I/O mode
|
// 000 Normal SPI mode
|
// 000 Normal SPI mode
|
// 001 Dual mode input
|
// 001 Dual mode input
|
// 010 Dual mode, output
|
// 010 Dual mode, output
|
// 101 Quad I/O mode input
|
// 101 Quad I/O mode input
|
// 110 Quad I/O mode output
|
// 110 Quad I/O mode output
|
//
|
//
|
//
|
//
|
|
|
|
|
//
|
//
|
//
|
//
|
|
// Generate a reference clock for the network
|
|
//
|
|
//
|
|
`ifdef VERILATOR
|
|
assign o_eth_ref_clk = i_eth_tx_clk;
|
|
`else
|
|
xoddr e_ref_clk( enet_clk, { 1'b1, 1'b0 }, o_eth_ref_clk );
|
|
`endif
|
|
|
|
//
|
|
//
|
// Wires for setting up the SD Card Controller
|
// Wires for setting up the SD Card Controller
|
//
|
//
|
//
|
//
|
assign io_sd_cmd = w_sd_cmd ? 1'bz:1'b0;
|
assign io_sd_cmd = w_sd_cmd ? 1'bz:1'b0;
|
assign io_sd[0] = w_sd_data[0]? 1'bz:1'b0;
|
assign io_sd[0] = w_sd_data[0]? 1'bz:1'b0;
|
assign io_sd[1] = w_sd_data[1]? 1'bz:1'b0;
|
assign io_sd[1] = w_sd_data[1]? 1'bz:1'b0;
|
assign io_sd[2] = w_sd_data[2]? 1'bz:1'b0;
|
assign io_sd[2] = w_sd_data[2]? 1'bz:1'b0;
|
assign io_sd[3] = w_sd_data[3]? 1'bz:1'b0;
|
assign io_sd[3] = w_sd_data[3]? 1'bz:1'b0;
|
|
|
|
|
//
|
//
|
//
|
//
|
// Wire(s) for setting up the MDIO ethernet control structure
|
// Wire(s) for setting up the MDIO ethernet control structure
|
//
|
//
|
//
|
//
|
assign io_eth_mdio = (w_mdwe)?w_mdio : 1'bz;
|
assign io_eth_mdio = (w_mdwe)?w_mdio : 1'bz;
|
|
|
|
|
//
|
//
|
//
|
//
|
// Now, to set up our memory ...
|
// Now, to set up our memory ...
|
//
|
//
|
//
|
//
|
migsdram rami(
|
migsdram #(.AXIDWIDTH(5)) rami(
|
.i_clk(mem_clk_nobuf), .i_clk_200mhz(mem_clk_200mhz_nobuf),
|
.i_clk(mem_clk_nobuf), .i_clk_200mhz(mem_clk_200mhz_nobuf),
|
.o_sys_clk(s_clk), .i_rst(pwr_reset), .o_sys_reset(s_reset),
|
.o_sys_clk(s_clk), .i_rst(pwr_reset), .o_sys_reset(s_reset),
|
.i_wb_cyc(ram_cyc), .i_wb_stb(ram_stb), .i_wb_we(ram_we),
|
.i_wb_cyc(ram_cyc), .i_wb_stb(ram_stb), .i_wb_we(ram_we),
|
.i_wb_addr(ram_addr), .i_wb_data(ram_wdata),
|
.i_wb_addr(ram_addr), .i_wb_data(ram_wdata),
|
.i_wb_sel(4'hf),
|
.i_wb_sel(4'hf),
|
.o_wb_ack(ram_ack), .o_wb_stall(ram_stall),
|
.o_wb_ack(ram_ack), .o_wb_stall(ram_stall),
|
.o_wb_data(ram_rdata), .o_wb_err(ram_err),
|
.o_wb_data(ram_rdata), .o_wb_err(ram_err),
|
.o_ddr_ck_p(ddr3_ck_p), .o_ddr_ck_n(ddr3_ck_n),
|
.o_ddr_ck_p(ddr3_ck_p), .o_ddr_ck_n(ddr3_ck_n),
|
.o_ddr_reset_n(ddr3_reset_n), .o_ddr_cke(ddr3_cke),
|
.o_ddr_reset_n(ddr3_reset_n), .o_ddr_cke(ddr3_cke),
|
.o_ddr_cs_n(ddr3_cs_n), .o_ddr_ras_n(ddr3_ras_n),
|
.o_ddr_cs_n(ddr3_cs_n), .o_ddr_ras_n(ddr3_ras_n),
|
.o_ddr_cas_n(ddr3_cas_n), .o_ddr_we_n(ddr3_we_n),
|
.o_ddr_cas_n(ddr3_cas_n), .o_ddr_we_n(ddr3_we_n),
|
.o_ddr_ba(ddr3_ba), .o_ddr_addr(ddr3_addr),
|
.o_ddr_ba(ddr3_ba), .o_ddr_addr(ddr3_addr),
|
.o_ddr_odt(ddr3_odt), .o_ddr_dm(ddr3_dm),
|
.o_ddr_odt(ddr3_odt), .o_ddr_dm(ddr3_dm),
|
.io_ddr_dqs_p(ddr3_dqs_p), .io_ddr_dqs_n(ddr3_dqs_n),
|
.io_ddr_dqs_p(ddr3_dqs_p), .io_ddr_dqs_n(ddr3_dqs_n),
|
.io_ddr_data(ddr3_dq),
|
.io_ddr_data(ddr3_dq),
|
//
|
//
|
.o_ram_dbg(ram_dbg)
|
.o_ram_dbg(ram_dbg)
|
);
|
);
|
|
|
endmodule
|
endmodule
|
|
|
|
|
