///////////////////////////////////////////////////////////////////////////
|
///////////////////////////////////////////////////////////////////////////
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//
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//
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// Filename: wbicapetwo.v
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// Filename: wbicapetwo.v
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//
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//
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// Project: Wishbone to ICAPE2 interface conversion
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// Project: Wishbone to ICAPE2 interface conversion
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//
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//
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// Purpose: This routine maps the configuration registers of a 7-series
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// Purpose: This routine maps the configuration registers of a 7-series
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// Xilinx part onto register addresses on a wishbone bus interface
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// Xilinx part onto register addresses on a wishbone bus interface
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// via the ICAPE2 access port to those parts. The big thing this
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// via the ICAPE2 access port to those parts. The big thing this
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// captures is the timing and handshaking required to read and
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// captures is the timing and handshaking required to read and
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// write registers from the configuration interface.
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// write registers from the configuration interface.
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//
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//
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// As an example of what can be done, writing a 32'h00f to
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// As an example of what can be done, writing a 32'h00f to
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// local address 5'h4 sends the IPROG command to the FPGA, causing
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// local address 5'h4 sends the IPROG command to the FPGA, causing
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// it to immediately reconfigure itself.
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// it to immediately reconfigure itself.
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//
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//
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// As another example, the warm boot start address is located
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// As another example, the warm boot start address is located
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// in register 5'h10. Writing to this address, followed by
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// in register 5'h10. Writing to this address, followed by
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// issuing the IPROG command just mentioned will cause the
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// issuing the IPROG command just mentioned will cause the
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// FPGA to configure from that warm boot start address.
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// FPGA to configure from that warm boot start address.
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//
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//
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// For more details on the configuration interface, the registers
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// For more details on the configuration interface, the registers
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// in question, their meanings and what they do, please see
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// in question, their meanings and what they do, please see
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// User's Guide 470, the "7 Series FPGAs Configuration" User
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// User's Guide 470, the "7 Series FPGAs Configuration" User
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// Guide.
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// Guide.
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//
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//
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// Notes: This module supports both reads and writes from the ICAPE2
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// Notes: This module supports both reads and writes from the ICAPE2
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// interface. These follow the following pattern.
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// interface. These follow the following pattern.
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//
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//
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// For writes:
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// For writes:
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// (Idle) 0xffffffff (Dummy)
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// (Idle) 0xffffffff (Dummy)
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// (CS/W) 0x20000000 NOOP
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// (CS/W) 0x20000000 NOOP
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// (CS/W) 0xaa995566 SYNC WORD
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// (CS/W) 0xaa995566 SYNC WORD
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// (CS/W) 0x20000000 NOOP
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// (CS/W) 0x20000000 NOOP
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// (CS/W) 0x20000000 NOOP
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// (CS/W) 0x20000000 NOOP
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// (CS/W) ... Write command
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// (CS/W) ... Write command
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// (CS/W) ... Write value, from Wishbone bus
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// (CS/W) ... Write value, from Wishbone bus
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// (CS/W) 0x20000000 NOOP
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// (CS/W) 0x20000000 NOOP
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// (CS/W) 0x20000000 NOOP
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// (CS/W) 0x20000000 NOOP
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// (CS/W) 0x30008001 Write to CMD register (address 4)
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// (CS/W) 0x30008001 Write to CMD register (address 4)
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// (CS/W) 0x0000000d DESYNC command
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// (CS/W) 0x0000000d DESYNC command
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// (CS/W) 0x20000000 NOOP
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// (CS/W) 0x20000000 NOOP
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// (CS/W) 0x20000000 NOOP
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// (CS/W) 0x20000000 NOOP
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// (Idle)
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// (Idle)
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//
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//
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// and for reads:
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// and for reads:
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// (Idle) 0xffffffff (Dummy)
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// (Idle) 0xffffffff (Dummy)
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// (CS/W) 0x20000000 NOOP
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// (CS/W) 0x20000000 NOOP
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// (CS/W) 0xaa995566 SYNC WORD
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// (CS/W) 0xaa995566 SYNC WORD
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// (CS/W) 0x20000000 NOOP
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// (CS/W) 0x20000000 NOOP
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// (CS/W) 0x20000000 NOOP
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// (CS/W) 0x20000000 NOOP
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// (CS/W) ... Read command
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// (CS/W) ... Read command
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// (CS/W) 0x20000000 NOOP
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// (CS/W) 0x20000000 NOOP
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// (CS/W) 0x20000000 NOOP
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// (CS/W) 0x20000000 NOOP
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// (Idle) 0x20000000 (Idle the interface again, so we can rd)
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// (Idle) 0x20000000 (Idle the interface again, so we can rd)
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// (CS/R) 0x20000000 (Wait)
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// (CS/R) 0x20000000 (Wait)
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// (CS/R) 0x20000000 (Wait)
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// (CS/R) 0x20000000 (Wait)
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// (CS/R) 0x20000000 (Wait)
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// (CS/R) 0x20000000 (Wait)
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// (CS/R) 0x20000000 (Wait)
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// (CS/R) 0x20000000 (Wait)
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// (Idle) 0x20000000 (Idle the interface before writing)
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// (Idle) 0x20000000 (Idle the interface before writing)
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// (CS/W) 0x20000000 NOOP
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// (CS/W) 0x20000000 NOOP
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// (CS/W) 0x20000000 NOOP
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// (CS/W) 0x20000000 NOOP
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// (CS/W) 0x30008001 Write to CMD register (address 4)
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// (CS/W) 0x30008001 Write to CMD register (address 4)
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// (CS/W) 0x0000000d DESYNC command
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// (CS/W) 0x0000000d DESYNC command
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// (CS/W) 0x20000000 NOOP
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// (CS/W) 0x20000000 NOOP
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// (CS/W) 0x20000000 NOOP
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// (CS/W) 0x20000000 NOOP
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// (Idle)
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// (Idle)
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// Creator: Dan Gisselquist, Ph.D.
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// Creator: Dan Gisselquist, Ph.D.
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// Gisselquist Technology, LLC
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// Gisselquist Technology, LLC
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//
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//
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///////////////////////////////////////////////////////////////////////////
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///////////////////////////////////////////////////////////////////////////
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//
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//
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// Copyright (C) 2015, Gisselquist Technology, LLC
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// Copyright (C) 2015, Gisselquist Technology, LLC
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//
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//
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// This program is free software (firmware): you can redistribute it and/or
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of the GNU General Public License as published
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// modify it under the terms of the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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// your option) any later version.
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//
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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// for more details.
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//
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//
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// License: GPL, v3, as defined and found on www.gnu.org,
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// License: GPL, v3, as defined and found on www.gnu.org,
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// http://www.gnu.org/licenses/gpl.html
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// http://www.gnu.org/licenses/gpl.html
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//
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//
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//
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//
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///////////////////////////////////////////////////////////////////////////
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///////////////////////////////////////////////////////////////////////////
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//
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//
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`define MBOOT_IDLE 5'h00
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`define MBOOT_IDLE 5'h00
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`define MBOOT_START 5'h01
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`define MBOOT_START 5'h01
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`define MBOOT_READ 5'h06
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`define MBOOT_READ 5'h06
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`define MBOOT_WRITE 5'h0f
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`define MBOOT_WRITE 5'h0f
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`define MBOOT_DESYNC 5'h11
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`define MBOOT_DESYNC 5'h11
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module wbicapetwo(i_clk,
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module wbicapetwo(i_clk,
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i_wb_cyc, i_wb_stb, i_wb_we, i_wb_addr, i_wb_data,
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i_wb_cyc, i_wb_stb, i_wb_we, i_wb_addr, i_wb_data,
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o_wb_ack, o_wb_stall, o_wb_data);
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o_wb_ack, o_wb_stall, o_wb_data, o_dbg);
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input i_clk;
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input i_clk;
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// Wishbone inputs
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// Wishbone inputs
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input i_wb_cyc, i_wb_stb, i_wb_we;
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input i_wb_cyc, i_wb_stb, i_wb_we;
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input [4:0] i_wb_addr;
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input [4:0] i_wb_addr;
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input [31:0] i_wb_data;
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input [31:0] i_wb_data;
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// Wishbone outputs
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// Wishbone outputs
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output reg o_wb_ack, o_wb_stall;
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output reg o_wb_ack, o_wb_stall;
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output reg [31:0] o_wb_data;
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output reg [31:0] o_wb_data;
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// Debugging output
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output wire [31:0] o_dbg;
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// ICAPE2 interface signals
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// ICAPE2 interface signals
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// These are kept internal to this block ...
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// These are kept internal to this block ...
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reg wb_req, r_we;
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reg wb_req, r_we;
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reg [31:0] r_data;
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reg [31:0] r_data;
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reg [4:0] r_addr;
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reg [4:0] r_addr;
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reg slow_clk;
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`ifdef DIVIDE_BY_FOUR
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reg [1:0] slow_clk_counter;
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reg clk_stb, clk_stall;
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wire slow_clk;
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always @(posedge i_clk)
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begin
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slow_clk <= slow_clk + 2'b01;
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// We'll move on the positive edge of the clock, so therefore
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// clk_stb must be true one clock before that, so we test for
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// it one clock before that.
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clk_stb <= (slow_clk_counter == 2'b10);
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// CLK_STALL is set to true two clocks before any cycle that
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// will, by necessity, stall.
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clk_stall <= (slow_clk_counter != 2'b01);
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end
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assign slow_clk = slow_clk_counter[1];
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`else
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reg slow_clk, clk_stb, clk_stall;
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always @(posedge i_clk)
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begin
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slow_clk <= (slow_clk + 1'b1);
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// We'll move on the positive edge of the clock, so therefore
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// clk_stb must be true one clock before that, so we test for
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// it one clock before that.
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clk_stb <= (slow_clk == 1'b1);
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// CLK_STALL is set to true two clocks before any cycle that
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// will, by necessity, stall.
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clk_stall <= (slow_clk != 1'b0); //True all but one clock
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end
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`endif
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reg [31:0] cfg_in;
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reg [31:0] cfg_in;
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reg cfg_cs_n, cfg_rdwrn;
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reg cfg_cs_n, cfg_rdwrn;
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wire [31:0] cfg_out;
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wire [31:0] cfg_out;
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reg [4:0] state;
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reg [4:0] state;
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initial state = `MBOOT_IDLE;
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initial state = `MBOOT_IDLE;
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initial cfg_cs_n = 1'b1;
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initial cfg_cs_n = 1'b1;
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always @(posedge i_clk)
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always @(posedge i_clk)
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begin
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begin
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// In general, o_wb_ack is always zero. The exceptions to this
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// will be handled individually below.
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o_wb_ack <= 1'b0;
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o_wb_ack <= 1'b0;
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// We can simplify our logic a touch by always setting
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// o_wb_data. It will only be examined if o_wb_ack
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// is also true, so this is okay.
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o_wb_data <= cfg_out;
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// Turn any request "off", so that it will not be ack'd, if
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// Turn any request "off", so that it will not be ack'd, if
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// the wb_cyc line is ever lowered.
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// the wb_cyc line is ever lowered.
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wb_req <= wb_req & i_wb_cyc;
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wb_req <= wb_req & i_wb_cyc;
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slow_clk <= slow_clk ^ 1'b1;
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o_wb_stall <= (state != `MBOOT_IDLE)||(clk_stall);
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o_wb_stall <= (state != `MBOOT_IDLE)&&(slow_clk);
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if (clk_stb)
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if (~slow_clk)
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begin
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begin
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state <= state + 5'h01;
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state <= state + 5'h01;
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case(state)
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case(state)
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`MBOOT_IDLE: begin
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`MBOOT_IDLE: begin
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cfg_cs_n <= 1'b1;
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cfg_cs_n <= 1'b1;
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cfg_rdwrn <= 1'b1;
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cfg_rdwrn <= 1'b1;
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cfg_in <= 32'hffffffff; // Dummy word
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cfg_in <= 32'hffffffff; // Dummy word
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state <= `MBOOT_IDLE;
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state <= `MBOOT_IDLE;
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o_wb_ack <= 1'b0;
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o_wb_ack <= 1'b0;
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|
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r_addr <= i_wb_addr;
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r_addr <= i_wb_addr;
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r_data <= i_wb_data;
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r_data <= i_wb_data;
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r_we <= i_wb_we;
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r_we <= i_wb_we;
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if(i_wb_stb)
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if(i_wb_stb) // &&(!o_wb_stall)
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begin
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begin
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state <= `MBOOT_START;
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state <= `MBOOT_START;
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wb_req <= 1'b1;
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wb_req <= 1'b1;
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//
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//
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o_wb_ack <= 1'b0;
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o_wb_ack <= 1'b0;
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end end
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end end
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`MBOOT_START: cfg_in <= 32'hffffffff; // NOOP
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`MBOOT_START: begin
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cfg_in <= 32'hffffffff; // NOOP
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cfg_cs_n <= 1'b1;
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end
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5'h02: begin
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5'h02: begin
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cfg_cs_n <= 1'b0; // Activate interface
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cfg_cs_n <= 1'b0; // Activate interface
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cfg_rdwrn <= 1'b0;
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cfg_rdwrn <= 1'b0;
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cfg_in <= 32'h20000000; // NOOP
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cfg_in <= 32'h20000000; // NOOP
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end
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end
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5'h03: cfg_in <= 32'haa995566; // Sync word
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5'h03: begin
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5'h04: cfg_in <= 32'h20000000; // NOOP
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cfg_in <= 32'haa995566; // Sync word
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cfg_cs_n <= 1'b0;
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end
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5'h04: begin
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cfg_in <= 32'h20000000; // NOOP
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cfg_cs_n <= 1'b0;
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|
end
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5'h05: begin
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5'h05: begin
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cfg_in <= 32'h20000000; // NOOP
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cfg_in <= 32'h20000000; // NOOP
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state <= (r_we) ? `MBOOT_WRITE : `MBOOT_READ;
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state <= (r_we) ? `MBOOT_WRITE : `MBOOT_READ;
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cfg_cs_n <= 1'b0;
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end
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`MBOOT_READ: begin
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cfg_cs_n <= 1'b0;
|
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cfg_in <= { 8'h28, 6'h0, r_addr, 13'h001 };
|
|
end
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5'h07: begin
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cfg_cs_n <= 1'b0;
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cfg_in <= 32'h20000000; // NOOP
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|
end
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5'h08: begin
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cfg_cs_n <= 1'b0;
|
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cfg_in <= 32'h20000000; // NOOP
|
end
|
end
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`MBOOT_READ: cfg_in <= { 8'h28, 6'h0, r_addr, 13'h001 };
|
|
5'h07: cfg_in <= 32'h20000000; // NOOP
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5'h08: cfg_in <= 32'h20000000; // NOOP
|
|
5'h09: begin // Idle the interface before the read cycle
|
5'h09: begin // Idle the interface before the read cycle
|
cfg_cs_n <= 1'b1;
|
cfg_cs_n <= 1'b1;
|
cfg_rdwrn <= 1'b1;
|
cfg_rdwrn <= 1'b1;
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cfg_in <= 32'h20000000; // NOOP
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cfg_in <= 32'h20000000; // NOOP
|
end
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end
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5'h0a: begin // Re-activate the interface and wait 3 cycles
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5'h0a: begin // Re-activate the interface and wait 3 cycles
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cfg_cs_n <= 1'b0;
|
cfg_cs_n <= 1'b0;
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cfg_rdwrn <= 1'b1;
|
cfg_rdwrn <= 1'b1;
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cfg_in <= 32'h20000000; // NOOP
|
cfg_in <= 32'h20000000; // NOOP
|
end
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end
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5'h0b: // ... still waiting, cycle two
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5'h0b: begin // ... still waiting, cycle two
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cfg_in <= 32'h20000000; // NOOP
|
cfg_in <= 32'h20000000; // NOOP
|
5'h0c: // ... still waiting, cycle three
|
cfg_cs_n <= 1'b0;
|
|
end
|
|
5'h0c: begin // ... still waiting, cycle three
|
cfg_in <= 32'h20000000; // NOOP
|
cfg_in <= 32'h20000000; // NOOP
|
5'h0d: // ... still waiting, cycle four
|
cfg_cs_n <= 1'b0;
|
|
end
|
|
5'h0d: begin // ... still waiting, cycle four
|
cfg_in <= 32'h20000000; // NOOP
|
cfg_in <= 32'h20000000; // NOOP
|
|
cfg_cs_n <= 1'b0;
|
|
end
|
5'h0e: begin // and now our answer is there
|
5'h0e: begin // and now our answer is there
|
cfg_cs_n <= 1'b1;
|
cfg_cs_n <= 1'b1;
|
cfg_rdwrn <= 1'b1;
|
cfg_rdwrn <= 1'b1;
|
cfg_in <= 32'h20000000; // NOOP
|
cfg_in <= 32'h20000000; // NOOP
|
//
|
//
|
// Wishbone return
|
// Wishbone return
|
o_wb_ack <= wb_req;
|
o_wb_ack <= wb_req;
|
o_wb_data <= cfg_out;
|
// o_wb_data <= cfg_out; // Independent of state
|
wb_req <= 1'b0;
|
wb_req <= 1'b0;
|
//
|
//
|
state <= `MBOOT_DESYNC;
|
state <= `MBOOT_DESYNC;
|
end
|
end
|
`MBOOT_WRITE: // Issue a write command to the given address
|
`MBOOT_WRITE: begin
|
|
// Issue a write command to the given address
|
cfg_in <= { 8'h30, 6'h0, r_addr, 13'h001 };
|
cfg_in <= { 8'h30, 6'h0, r_addr, 13'h001 };
|
5'h10: cfg_in <= r_data; // Write the value
|
cfg_cs_n <= 1'b0;
|
|
end
|
|
5'h10: begin
|
|
cfg_in <= r_data; // Write the value
|
|
cfg_cs_n <= 1'b0;
|
|
end
|
`MBOOT_DESYNC: begin
|
`MBOOT_DESYNC: begin
|
cfg_cs_n <= 1'b0;
|
cfg_cs_n <= 1'b0;
|
cfg_rdwrn <= 1'b0;
|
cfg_rdwrn <= 1'b0;
|
cfg_in <= 32'h20000000; // 1st NOOP
|
cfg_in <= 32'h20000000; // 1st NOOP
|
end
|
end
|
5'h12: cfg_in <= 32'h20000000; // 2nd NOOP
|
5'h12: begin
|
5'h13: cfg_in <= 32'h30008001; // Write to CMD register
|
cfg_cs_n <= 1'b0;
|
5'h14: cfg_in <= 32'h0000000d; // DESYNC command
|
cfg_in <= 32'h20000000; // 2nd NOOP
|
5'h15: cfg_in <= 32'h20000000; // NOOP
|
end
|
5'h16: cfg_in <= 32'h20000000; // NOOP
|
5'h13: begin
|
|
cfg_cs_n <= 1'b0;
|
|
cfg_in <= 32'h30008001; // Write to CMD register
|
|
end
|
|
5'h14: begin
|
|
cfg_cs_n <= 1'b0;
|
|
cfg_in <= 32'h0000000d; // DESYNC command
|
|
end
|
|
5'h15: begin
|
|
cfg_cs_n <= 1'b0;
|
|
cfg_in <= 32'h20000000; // NOOP
|
|
end
|
|
5'h16: begin
|
|
cfg_cs_n <= 1'b0;
|
|
cfg_in <= 32'h20000000; // NOOP
|
|
end
|
5'h17: begin
|
5'h17: begin
|
// Acknowledge the bus transaction, it is now complete
|
// Acknowledge the bus transaction, it is now complete
|
o_wb_ack <= wb_req;
|
o_wb_ack <= wb_req;
|
wb_req <= 1'b0;
|
wb_req <= 1'b0;
|
//
|
//
|
cfg_cs_n <= 1'b1;
|
cfg_cs_n <= 1'b1;
|
cfg_rdwrn <= 1'b0;
|
cfg_rdwrn <= 1'b0;
|
cfg_in <= 32'hffffffff; // DUMMY
|
cfg_in <= 32'hffffffff; // DUMMY
|
//
|
//
|
state <= `MBOOT_IDLE;
|
state <= `MBOOT_IDLE;
|
end
|
end
|
default: begin
|
default: begin
|
o_wb_ack <= 1'b0;
|
wb_req <= 1'b0;
|
cfg_cs_n <= 1'b1;
|
cfg_cs_n <= 1'b1;
|
cfg_rdwrn <= 1'b0;
|
cfg_rdwrn <= 1'b0;
|
state <= `MBOOT_IDLE;
|
state <= `MBOOT_IDLE;
|
cfg_in <= 32'hffffffff; // DUMMY WORD
|
cfg_in <= 32'hffffffff; // DUMMY WORD
|
end
|
end
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endcase
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endcase
|
end else begin
|
|
o_wb_ack <= 1'b0;
|
|
end
|
end
|
end
|
end
|
|
|
genvar k;
|
genvar k;
|
//
|
//
|
// The data registers to the ICAPE2 interface are bit swapped within
|
// The data registers to the ICAPE2 interface are bit swapped within
|
// each byte. Thus, in order to read from or write to the interface,
|
// each byte. Thus, in order to read from or write to the interface,
|
// we need to bit swap the bits in each byte. These next lines
|
// we need to bit swap the bits in each byte. These next lines
|
// accomplish that for both the input and output ports.
|
// accomplish that for both the input and output ports.
|
//
|
//
|
wire [31:0] bit_swapped_cfg_in;
|
wire [31:0] bit_swapped_cfg_in;
|
generate
|
generate
|
for(k=0; k<8; k=k+1)
|
for(k=0; k<8; k=k+1)
|
begin
|
begin
|
assign bit_swapped_cfg_in[ k] = cfg_in[ 7-k];
|
assign bit_swapped_cfg_in[ k] = cfg_in[ 7-k];
|
assign bit_swapped_cfg_in[ 8+k] = cfg_in[ 8+7-k];
|
assign bit_swapped_cfg_in[ 8+k] = cfg_in[ 8+7-k];
|
assign bit_swapped_cfg_in[16+k] = cfg_in[16+7-k];
|
assign bit_swapped_cfg_in[16+k] = cfg_in[16+7-k];
|
assign bit_swapped_cfg_in[24+k] = cfg_in[24+7-k];
|
assign bit_swapped_cfg_in[24+k] = cfg_in[24+7-k];
|
end endgenerate
|
end endgenerate
|
|
|
wire [31:0] bit_swapped_cfg_out;
|
wire [31:0] bit_swapped_cfg_out;
|
generate
|
generate
|
for(k=0; k<8; k=k+1)
|
for(k=0; k<8; k=k+1)
|
begin
|
begin
|
assign cfg_out[ k] = bit_swapped_cfg_out[ 7-k];
|
assign cfg_out[ k] = bit_swapped_cfg_out[ 7-k];
|
assign cfg_out[ 8+k] = bit_swapped_cfg_out[ 8+7-k];
|
assign cfg_out[ 8+k] = bit_swapped_cfg_out[ 8+7-k];
|
assign cfg_out[16+k] = bit_swapped_cfg_out[16+7-k];
|
assign cfg_out[16+k] = bit_swapped_cfg_out[16+7-k];
|
assign cfg_out[24+k] = bit_swapped_cfg_out[24+7-k];
|
assign cfg_out[24+k] = bit_swapped_cfg_out[24+7-k];
|
end endgenerate
|
end endgenerate
|
|
|
ICAPE2 #(.ICAP_WIDTH("X32")) reconfig(.CLK(slow_clk),
|
ICAPE2 #(.ICAP_WIDTH("X32")) reconfig(.CLK(slow_clk),
|
.CSIB(cfg_cs_n), .RDWRB(cfg_rdwrn),
|
.CSIB(cfg_cs_n), .RDWRB(cfg_rdwrn),
|
.I(bit_swapped_cfg_in), .O(bit_swapped_cfg_out));
|
.I(bit_swapped_cfg_in), .O(bit_swapped_cfg_out));
|
|
|
|
assign o_dbg = {
|
|
`ifdef DIVIDE_BY_FOUR
|
|
slow_clk_counter, clk_stb, clk_stall,
|
|
`else
|
|
1'b0, slow_clk, clk_stb, clk_stall,
|
|
`endif
|
|
i_wb_stb, o_wb_ack, cfg_cs_n, cfg_rdwrn,
|
|
o_wb_stall, state, 2'h0,
|
|
cfg_in[7:0],
|
|
cfg_out[7:0] };
|
|
|
endmodule
|
endmodule
|
|
|
