////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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// Filename: regdefs.h
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// Filename: regdefs.h
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//
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//
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// Project: OpenArty, an entirely open SoC based upon the Arty platform
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// Project: OpenArty, an entirely open SoC based upon the Arty platform
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//
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//
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// Purpose:
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// Purpose:
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//
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//
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// Creator: Dan Gisselquist, Ph.D.
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// Creator: Dan Gisselquist, Ph.D.
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// Gisselquist Technology, LLC
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// Gisselquist Technology, LLC
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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// Copyright (C) 2015-2016, Gisselquist Technology, LLC
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// Copyright (C) 2015-2016, Gisselquist Technology, LLC
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//
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//
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// This program is free software (firmware): you can redistribute it and/or
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of the GNU General Public License as published
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// modify it under the terms of the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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// your option) any later version.
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//
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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// for more details.
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//
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//
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// You should have received a copy of the GNU General Public License along
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// You should have received a copy of the GNU General Public License along
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// with this program. (It's in the $(ROOT)/doc directory, run make with no
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// with this program. (It's in the $(ROOT)/doc directory, run make with no
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// target there if the PDF file isn't present.) If not, see
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// target there if the PDF file isn't present.) If not, see
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// <http://www.gnu.org/licenses/> for a copy.
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// <http://www.gnu.org/licenses/> for a copy.
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//
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//
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// License: GPL, v3, as defined and found on www.gnu.org,
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// License: GPL, v3, as defined and found on www.gnu.org,
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// http://www.gnu.org/licenses/gpl.html
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// http://www.gnu.org/licenses/gpl.html
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//
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//
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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//
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//
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#ifndef REGDEFS_H
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#ifndef REGDEFS_H
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#define REGDEFS_H
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#define REGDEFS_H
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#define R_VERSION 0x00000100
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#define R_VERSION 0x00000100
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#define R_ICONTROL 0x00000101
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#define R_ICONTROL 0x00000101
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#define R_BUSERR 0x00000102
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#define R_BUSERR 0x00000102
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#define R_PWCOUNT 0x00000103
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#define R_PWCOUNT 0x00000103
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#define R_BTNSW 0x00000104
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#define R_BTNSW 0x00000104
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#define R_LEDS 0x00000105
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#define R_LEDS 0x00000105
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#define R_UART_SETUP 0x00000106
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#define R_UART_SETUP 0x00000106
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#define R_GPS_SETUP 0x00000107
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#define R_GPS_SETUP 0x00000107
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#define R_CLR0 0x00000108
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#define R_CLR0 0x00000108
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#define R_CLR1 0x00000109
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#define R_CLR1 0x00000109
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#define R_CLR2 0x0000010a
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#define R_CLR2 0x0000010a
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#define R_CLR3 0x0000010b
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#define R_CLR3 0x0000010b
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#define R_DATE 0x0000010c
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#define R_DATE 0x0000010c
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#define R_GPIO 0x0000010d // No GPIO device exists ... yet
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#define R_GPIO 0x0000010d // No GPIO device exists ... yet
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#define R_UARTRX 0x0000010e
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#define R_UARTRX 0x0000010e
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#define R_UARTTX 0x0000010f
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#define R_UARTTX 0x0000010f
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#define R_GPSRX 0x00000110
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#define R_GPSRX 0x00000110
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#define R_GPSTX 0x00000111
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#define R_GPSTX 0x00000111
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// WB Scope registers
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// WB Scope registers
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#define R_QSCOPE 0x00000120 // Quad SPI scope ctrl
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#define R_QSCOPE 0x00000120 // Scope #0: Quad SPI scope ctrl
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#define R_QSCOPED 0x00000121 // and data
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#define R_QSCOPED 0x00000121 // and data
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#define R_GPSCOPE 0x00000122 // GPS configuration scope control
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#define R_CPUSCOPE 0x00000120 // CPU scope (if so configured)
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#define R_CPUSCOPED 0x00000121 // and data
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#define R_GPSCOPE 0x00000122 // Scope #1: GPS config scope control
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#define R_GPSCOPED 0x00000123 // and data
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#define R_GPSCOPED 0x00000123 // and data
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#define R_CFGSCOPE 0x00000122 // ICAPE2 configuration scop control
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#define R_CFGSCOPE 0x00000122 // ICAPE2 configuration scop control
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#define R_CFGSCOPED 0x00000123 // and data
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#define R_CFGSCOPED 0x00000123 // and data
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#define R_RAMSCOPE 0x00000124 // DDR3 SDRAM Scope
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#define R_BUSSCOPE 0x00000122 // WBUBUS scope control
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#define R_BUSSCOPED 0x00000123 // and data
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#define R_RAMSCOPE 0x00000124 // Scope #2: DDR3 SDRAM Scope
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#define R_RAMSCOPED 0x00000125 //
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#define R_RAMSCOPED 0x00000125 //
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#define R_NETSCOPE 0x00000126 // Ethernet debug scope
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#define R_NETSCOPE 0x00000126 // Scope #3: Ethernet debug scope
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#define R_NETSCOPED 0x00000127 //
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#define R_NETSCOPED 0x00000127 //
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// RTC Clock Registers
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// RTC Clock Registers
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#define R_CLOCK 0x00000128
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#define R_CLOCK 0x00000128
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#define R_TIMER 0x00000129
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#define R_TIMER 0x00000129
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#define R_STOPWATCH 0x0000012a
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#define R_STOPWATCH 0x0000012a
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#define R_CKALARM 0x0000012b
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#define R_CKALARM 0x0000012b
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// SD Card Control
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// SD Card Control
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#define R_SDCARD_CTRL 0x0000012c
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#define R_SDCARD_CTRL 0x0000012c
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#define R_SDCARD_DATA 0x0000012d
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#define R_SDCARD_DATA 0x0000012d
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#define R_SDCARD_FIFOA 0x0000012e
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#define R_SDCARD_FIFOA 0x0000012e
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#define R_SDCARD_FIFOB 0x0000012f
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#define R_SDCARD_FIFOB 0x0000012f
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// GPS Loop control, 0x0130
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// GPS Loop control, 0x0130
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#define R_GPS_ALPHA 0x00000130
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#define R_GPS_ALPHA 0x00000130
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#define R_GPS_BETA 0x00000131
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#define R_GPS_BETA 0x00000131
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#define R_GPS_GAMMA 0x00000132
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#define R_GPS_GAMMA 0x00000132
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#define R_GPS_STEP 0x00000133
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#define R_GPS_STEP 0x00000133
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// Network packet interface, 0x0134
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// OLED
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// OLED
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#define R_OLED_CMD 0x00000138
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#define R_OLED_CMD 0x00000134
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#define R_OLED_CDATA 0x00000139
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#define R_OLED_CDATA 0x00000135
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#define R_OLED_CDATB 0x0000013a
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#define R_OLED_CDATB 0x00000136
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#define R_OLED_DATA 0x0000013b
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#define R_OLED_DATA 0x00000137
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// Network packet interface, 0x0184
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#define R_NET_RXCMD 0x00000138
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#define R_NET_TXCMD 0x00000139
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#define R_NET_MACHI 0x0000013a
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#define R_NET_MACLO 0x0000013b
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#define R_NET_RXMISS 0x0000013c
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#define R_NET_RXERR 0x0000013d
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#define R_NET_RXCRC 0x0000013e
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#define R_NET_TXCOL 0x0000013f
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// Unused: 0x13c-0x13f
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// Unused: 0x13c-0x13f
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// GPS Testbench: 0x140-0x147
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// GPS Testbench: 0x140-0x147
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#define R_GPSTB_FREQ 0x00000140
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#define R_GPSTB_FREQ 0x00000140
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#define R_GPSTB_JUMP 0x00000141
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#define R_GPSTB_JUMP 0x00000141
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#define R_GPSTB_ERRHI 0x00000142
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#define R_GPSTB_ERRHI 0x00000142
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#define R_GPSTB_ERRLO 0x00000143
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#define R_GPSTB_ERRLO 0x00000143
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#define R_GPSTB_COUNTHI 0x00000144
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#define R_GPSTB_COUNTHI 0x00000144
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#define R_GPSTB_COUNTLO 0x00000145
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#define R_GPSTB_COUNTLO 0x00000145
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#define R_GPSTB_STEPHI 0x00000146
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#define R_GPSTB_STEPHI 0x00000146
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#define R_GPSTB_STEPLO 0x00000147
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#define R_GPSTB_STEPLO 0x00000147
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// Unused: 0x148-0x19f
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// Unused: 0x148-0x19f
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// Ethernet configuration (MDIO) port: 0x1a0-0x1bf
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// Ethernet configuration (MDIO) port: 0x1a0-0x1bf
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#define R_MDIO_BMCR 0x000001a0
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#define R_MDIO_BMCR 0x000001a0
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#define R_MDIO_BMSR 0x000001a1
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#define R_MDIO_BMSR 0x000001a1
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#define R_MDIO_PHYIDR1 0x000001a2
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#define R_MDIO_PHYIDR1 0x000001a2
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#define R_MDIO_PHYIDR2 0x000001a3
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#define R_MDIO_PHYIDR2 0x000001a3
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#define R_MDIO_ANAR 0x000001a4
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#define R_MDIO_ANAR 0x000001a4
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#define R_MDIO_ANLPAR 0x000001a5
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#define R_MDIO_ANLPAR 0x000001a5
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// #define R_MDIO_ANLPARNP 0x000001a5
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// #define R_MDIO_ANLPARNP 0x000001a5
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#define R_MDIO_ANER 0x000001a6
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#define R_MDIO_ANER 0x000001a6
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#define R_MDIO_ANNPTR 0x000001a7
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#define R_MDIO_ANNPTR 0x000001a7
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#define R_MDIO_PHYSTS 0x000001b0
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#define R_MDIO_PHYSTS 0x000001b0
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#define R_MDIO_FCSCR 0x000001b4
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#define R_MDIO_FCSCR 0x000001b4
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#define R_MDIO_RECR 0x000001b5
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#define R_MDIO_RECR 0x000001b5
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#define R_MDIO_PCSR 0x000001b6
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#define R_MDIO_PCSR 0x000001b6
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#define R_MDIO_RBR 0x000001b7
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#define R_MDIO_RBR 0x000001b7
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#define R_MDIO_LEDCR 0x000001b8
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#define R_MDIO_LEDCR 0x000001b8
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#define R_MDIO_PHYCR 0x000001b9
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#define R_MDIO_PHYCR 0x000001b9
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#define R_MDIO_BTSCR 0x000001ba
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#define R_MDIO_BTSCR 0x000001ba
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#define R_MDIO_CDCTRL 0x000001bb
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#define R_MDIO_CDCTRL 0x000001bb
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#define R_MDIO_EDCR 0x000001bd
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#define R_MDIO_EDCR 0x000001bd
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// Flash: 0x1c0-0x1df
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// Flash: 0x1c0-0x1df
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#define R_QSPI_EREG 0x000001c0
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#define R_QSPI_EREG 0x000001c0
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#define R_QSPI_STAT 0x000001c1
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#define R_QSPI_STAT 0x000001c1
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#define R_QSPI_NVCONF 0x000001c2
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#define R_QSPI_NVCONF 0x000001c2
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#define R_QSPI_VCONF 0x000001c3
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#define R_QSPI_VCONF 0x000001c3
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#define R_QSPI_EVCONF 0x000001c4
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#define R_QSPI_EVCONF 0x000001c4
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#define R_QSPI_LOCK 0x000001c5
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#define R_QSPI_LOCK 0x000001c5
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#define R_QSPI_FLAG 0x000001c6
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#define R_QSPI_FLAG 0x000001c6
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// #define R_QSPI_ASYNC 0x000001c7
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// #define R_QSPI_ASYNC 0x000001c7
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#define R_QSPI_ID 0x000001c8
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#define R_QSPI_ID 0x000001c8
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#define R_QSPI_IDA 0x000001c9
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#define R_QSPI_IDA 0x000001c9
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#define R_QSPI_IDB 0x000001ca
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#define R_QSPI_IDB 0x000001ca
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#define R_QSPI_IDC 0x000001cb
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#define R_QSPI_IDC 0x000001cb
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#define R_QSPI_IDD 0x000001cc
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#define R_QSPI_IDD 0x000001cc
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//
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//
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#define R_QSPI_OTPWP 0x000001cf
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#define R_QSPI_OTPWP 0x000001cf
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#define R_QSPI_OTP 0x000001d0
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#define R_QSPI_OTP 0x000001d0
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// FPGA CONFIG REGISTERS: 0x1e0-0x1ff
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// FPGA CONFIG REGISTERS: 0x1e0-0x1ff
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#define R_CFG_CRC 0x000001e0
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#define R_CFG_CRC 0x000001e0
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#define R_CFG_FAR 0x000001e1
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#define R_CFG_FAR 0x000001e1
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#define R_CFG_FDRI 0x000001e2
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#define R_CFG_FDRI 0x000001e2
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#define R_CFG_FDRO 0x000001e3
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#define R_CFG_FDRO 0x000001e3
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#define R_CFG_CMD 0x000001e4
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#define R_CFG_CMD 0x000001e4
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#define R_CFG_CTL0 0x000001e5
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#define R_CFG_CTL0 0x000001e5
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#define R_CFG_MASK 0x000001e6
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#define R_CFG_MASK 0x000001e6
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#define R_CFG_STAT 0x000001e7
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#define R_CFG_STAT 0x000001e7
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#define R_CFG_LOUT 0x000001e8
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#define R_CFG_LOUT 0x000001e8
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#define R_CFG_COR0 0x000001e9
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#define R_CFG_COR0 0x000001e9
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#define R_CFG_MFWR 0x000001ea
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#define R_CFG_MFWR 0x000001ea
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#define R_CFG_CBC 0x000001eb
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#define R_CFG_CBC 0x000001eb
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#define R_CFG_IDCODE 0x000001ec
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#define R_CFG_IDCODE 0x000001ec
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#define R_CFG_AXSS 0x000001ed
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#define R_CFG_AXSS 0x000001ed
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#define R_CFG_COR1 0x000001ee
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#define R_CFG_COR1 0x000001ee
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#define R_CFG_WBSTAR 0x000001f0
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#define R_CFG_WBSTAR 0x000001f0
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#define R_CFG_TIMER 0x000001f1
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#define R_CFG_TIMER 0x000001f1
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#define R_CFG_BOOTSTS 0x000001f6
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#define R_CFG_BOOTSTS 0x000001f6
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#define R_CFG_CTL1 0x000001f8
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#define R_CFG_CTL1 0x000001f8
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#define R_CFG_BSPI 0x000001ff
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#define R_CFG_BSPI 0x000001ff
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// Network buffer space
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#define R_NET_RXBUF 0x00000800
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#define R_NET_TXBUF 0x00000c00
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// Block RAM memory space
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// Block RAM memory space
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#define MEMBASE 0x00008000
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#define MEMBASE 0x00008000
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#define MEMWORDS 0x00008000
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#define MEMWORDS 0x00008000
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// Flash memory space
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// Flash memory space
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#define EQSPIFLASH 0x00400000
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#define EQSPIFLASH 0x00400000
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#define RESET_ADDRESS 0x004e0000
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#define FLASHWORDS (1<<22)
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#define FLASHWORDS (1<<22)
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// DDR3 SDRAM memory space
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// DDR3 SDRAM memory space
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#define RAMBASE 0x04000000
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#define RAMBASE 0x04000000
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#define SDRAMBASE RAMBASE
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#define SDRAMBASE RAMBASE
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#define RAMWORDS (1<<26)
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#define RAMWORDS (1<<26)
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// Zip CPU Control and Debug registers
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// Zip CPU Control and Debug registers
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#define R_ZIPCTRL 0x01000000
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#define R_ZIPCTRL 0x08000000
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#define R_ZIPDATA 0x01000001
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#define R_ZIPDATA 0x08000001
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// Interrupt control constants
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// Interrupt control constants
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#define GIE 0x80000000 // Enable all interrupts
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#define GIE 0x80000000 // Enable all interrupts
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#define ISPIF_EN 0x82000200 // Enable all, enable QSPI, clear QSPI
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#define ISPIF_EN 0x82000200 // Enable all, enable QSPI, clear QSPI
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#define ISPIF_DIS 0x02000200 // Disable all, disable QSPI
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#define ISPIF_DIS 0x02000200 // Disable all, disable QSPI
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#define ISPIF_CLR 0x00000200 // Clear QSPI interrupt
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#define ISPIF_CLR 0x00000200 // Clear QSPI interrupt
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#define SCOPEN 0x84000400 // Enable WBSCOPE interrupts
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#define SCOPEN 0x84000400 // Enable WBSCOPE interrupts
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// Flash control constants
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// Flash control constants
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#define ERASEFLAG 0xc00001be
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#define ERASEFLAG 0xc00001be
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#define DISABLEWP 0x40000000
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#define DISABLEWP 0x40000000
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#define ENABLEWP 0x00000000
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#define ENABLEWP 0x00000000
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#define SZPAGEB 256
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#define SZPAGEB 256
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#define PGLENB 256
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#define PGLENB 256
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#define SZPAGEW 64
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#define SZPAGEW 64
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#define PGLENW 64
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#define PGLENW 64
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#define NPAGES 256
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#define NPAGES 256
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#define SECTORSZB (NPAGES * SZPAGEB) // In bytes, not words!!
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#define SECTORSZB (NPAGES * SZPAGEB) // In bytes, not words!!
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#define SECTORSZW (NPAGES * SZPAGEW) // In words
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#define SECTORSZW (NPAGES * SZPAGEW) // In words
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#define NSECTORS 64
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#define NSECTORS 64
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#define SECTOROF(A) ((A) & (-1<<14))
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#define SECTOROF(A) ((A) & (-1<<14))
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#define SUBSECTOROF(A) ((A) & (-1<<10))
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#define SUBSECTOROF(A) ((A) & (-1<<10))
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#define PAGEOF(A) ((A) & (-1<<6))
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#define PAGEOF(A) ((A) & (-1<<6))
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#define CPU_GO 0x0000
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#define CPU_GO 0x0000
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#define CPU_RESET 0x0040
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#define CPU_RESET 0x0040
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#define CPU_INT 0x0080
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#define CPU_INT 0x0080
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#define CPU_STEP 0x0100
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#define CPU_STEP 0x0100
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#define CPU_STALL 0x0200
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#define CPU_STALL 0x0200
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#define CPU_HALT 0x0400
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#define CPU_HALT 0x0400
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#define CPU_CLRCACHE 0x0800
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#define CPU_CLRCACHE 0x0800
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#define CPU_sR0 (0x0000|CPU_HALT)
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#define CPU_sR0 0x0000
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#define CPU_sSP (0x000d|CPU_HALT)
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#define CPU_sSP 0x000d
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#define CPU_sCC (0x000e|CPU_HALT)
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#define CPU_sCC 0x000e
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#define CPU_sPC (0x000f|CPU_HALT)
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#define CPU_sPC 0x000f
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#define CPU_uR0 (0x0010|CPU_HALT)
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#define CPU_uR0 0x0010
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#define CPU_uSP (0x001d|CPU_HALT)
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#define CPU_uSP 0x001d
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#define CPU_uCC (0x001e|CPU_HALT)
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#define CPU_uCC 0x001e
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#define CPU_uPC (0x001f|CPU_HALT)
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#define CPU_uPC 0x001f
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#define SCOPE_NO_RESET 0x80000000
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#define SCOPE_NO_RESET 0x80000000
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#define SCOPE_TRIGGER (0x08000000|SCOPE_NO_RESET)
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#define SCOPE_TRIGGER (0x08000000|SCOPE_NO_RESET)
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#define SCOPE_MANUAL SCOPE_TRIGGER
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#define SCOPE_DISABLE (0x04000000)
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#define SCOPE_DISABLE (0x04000000)
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typedef struct {
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typedef struct {
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unsigned m_addr;
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unsigned m_addr;
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const char *m_name;
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const char *m_name;
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} REGNAME;
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} REGNAME;
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extern const REGNAME *bregs;
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extern const REGNAME *bregs;
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extern const int NREGS;
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extern const int NREGS;
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// #define NREGS (sizeof(bregs)/sizeof(bregs[0]))
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// #define NREGS (sizeof(bregs)/sizeof(bregs[0]))
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extern unsigned addrdecode(const char *v);
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extern unsigned addrdecode(const char *v);
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extern const char *addrname(const unsigned v);
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extern const char *addrname(const unsigned v);
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#include "ttybus.h"
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#include "ttybus.h"
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// #include "portbus.h"
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// #include "portbus.h"
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typedef TTYBUS FPGA;
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typedef TTYBUS FPGA;
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#endif
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#endif
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