////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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// Filename: wbregs.cpp
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// Filename: wbregs.cpp
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//
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//
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// Project: OpenArty, an entirely open SoC based upon the Arty platform
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// Project: OpenArty, an entirely open SoC based upon the Arty platform
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//
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//
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// Purpose: To give a user access, via a command line program, to read
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// Purpose: To give a user access, via a command line program, to read
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// and write wishbone registers one at a time. Thus this program
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// and write wishbone registers one at a time. Thus this program
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// implements readio() and writeio() but nothing more.
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// implements readio() and writeio() but nothing more.
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//
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//
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//
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//
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// Creator: Dan Gisselquist, Ph.D.
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// Creator: Dan Gisselquist, Ph.D.
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// Gisselquist Technology, LLC
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// Gisselquist Technology, LLC
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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// Copyright (C) 2015-2016, Gisselquist Technology, LLC
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// Copyright (C) 2015-2017, Gisselquist Technology, LLC
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//
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//
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// This program is free software (firmware): you can redistribute it and/or
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of the GNU General Public License as published
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// modify it under the terms of the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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// your option) any later version.
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//
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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// for more details.
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//
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//
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// You should have received a copy of the GNU General Public License along
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// You should have received a copy of the GNU General Public License along
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// with this program. (It's in the $(ROOT)/doc directory, run make with no
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// with this program. (It's in the $(ROOT)/doc directory. Run make with no
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// target there if the PDF file isn't present.) If not, see
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// target there if the PDF file isn't present.) If not, see
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// <http://www.gnu.org/licenses/> for a copy.
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// <http://www.gnu.org/licenses/> for a copy.
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//
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//
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// License: GPL, v3, as defined and found on www.gnu.org,
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// License: GPL, v3, as defined and found on www.gnu.org,
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// http://www.gnu.org/licenses/gpl.html
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// http://www.gnu.org/licenses/gpl.html
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//
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//
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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//
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//
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#include <stdio.h>
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#include <stdio.h>
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#include <stdlib.h>
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#include <stdlib.h>
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#include <unistd.h>
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#include <unistd.h>
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#include <strings.h>
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#include <strings.h>
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#include <ctype.h>
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#include <ctype.h>
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#include <string.h>
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#include <string.h>
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#include <signal.h>
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#include <signal.h>
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#include <assert.h>
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#include <assert.h>
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#include "port.h"
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#include "port.h"
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#include "regdefs.h"
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#include "regdefs.h"
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FPGA *m_fpga;
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FPGA *m_fpga;
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void closeup(int v) {
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void closeup(int v) {
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m_fpga->kill();
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m_fpga->kill();
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exit(0);
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exit(0);
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}
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}
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void usage(void) {
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void usage(void) {
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printf("USAGE: wbregs address [value]\n"
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printf("USAGE: wbregs address [value]\n"
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"\n"
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"\n"
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"\tWBREGS stands for Wishbone registers. It is designed to allow a\n"
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"\tWBREGS stands for Wishbone registers. It is designed to allow a\n"
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"\tuser to peek and poke at registers within a given FPGA design, so\n"
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"\tuser to peek and poke at registers within a given FPGA design, so\n"
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"\tlong as those registers have addresses on the wishbone bus. The\n"
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"\tlong as those registers have addresses on the wishbone bus. The\n"
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"\taddress may reference peripherals or memory, depending upon how the\n"
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"\taddress may reference peripherals or memory, depending upon how the\n"
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"\tbus is configured.\n"
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"\tbus is configured.\n"
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"\n"
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"\n"
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"\tAddress is either a 32-bit value with the syntax of strtoul, or a\n"
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"\tAddress is either a 32-bit value with the syntax of strtoul, or a\n"
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"\tregister name. Register names can be found in regdefs.cpp\n"
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"\tregister name. Register names can be found in regdefs.cpp\n"
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"\n"
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"\n"
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"\tIf a value is given, that value will be written to the indicated\n"
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"\tIf a value is given, that value will be written to the indicated\n"
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"\taddress, otherwise the result from reading the address will be \n"
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"\taddress, otherwise the result from reading the address will be \n"
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"\twritten to the screen.\n");
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"\twritten to the screen.\n");
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}
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}
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int main(int argc, char **argv) {
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int main(int argc, char **argv) {
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int skp=0, port = FPGAPORT;
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int skp=0;
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bool use_usb = true, use_decimal = false;
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bool use_decimal = false;
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skp=1;
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skp=1;
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for(int argn=0; argn<argc-skp; argn++) {
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for(int argn=0; argn<argc-skp; argn++) {
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if (argv[argn+skp][0] == '-') {
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if (argv[argn+skp][0] == '-') {
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if (argv[argn+skp][1] == 'd') {
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if (argv[argn+skp][1] == 'd') {
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use_decimal = true;
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use_decimal = true;
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} else {
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} else {
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usage();
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usage();
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exit(EXIT_SUCCESS);
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exit(EXIT_SUCCESS);
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}
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}
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skp++; argn--;
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skp++; argn--;
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} else
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} else
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argv[argn] = argv[argn+skp];
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argv[argn] = argv[argn+skp];
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} argc -= skp;
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} argc -= skp;
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FPGAOPEN(m_fpga);
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FPGAOPEN(m_fpga);
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signal(SIGSTOP, closeup);
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signal(SIGSTOP, closeup);
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signal(SIGHUP, closeup);
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signal(SIGHUP, closeup);
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if ((argc < 1)||(argc > 2)) {
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if ((argc < 1)||(argc > 2)) {
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// usage();
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// usage();
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printf("USAGE: wbregs address [value]\n");
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printf("USAGE: wbregs address [value]\n");
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exit(-1);
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exit(-1);
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}
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}
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const char *nm;
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const char *nm;
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unsigned address = addrdecode(argv[0]), value;
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unsigned address = addrdecode(argv[0]), value;
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nm = addrname(address);
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nm = addrname(address);
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if (nm == NULL)
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if (nm == NULL)
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nm = "no name";
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nm = "no name";
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if (argc < 2) {
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if (argc < 2) {
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FPGA::BUSW v;
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FPGA::BUSW v;
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try {
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try {
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unsigned char a, b, c, d;
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unsigned char a, b, c, d;
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v = m_fpga->readio(address);
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v = m_fpga->readio(address);
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a = (v>>24)&0x0ff;
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a = (v>>24)&0x0ff;
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b = (v>>16)&0x0ff;
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b = (v>>16)&0x0ff;
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c = (v>> 8)&0x0ff;
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c = (v>> 8)&0x0ff;
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d = (v )&0x0ff;
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d = (v )&0x0ff;
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if (use_decimal)
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if (use_decimal)
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printf("%d\n", v);
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printf("%d\n", v);
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else
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else
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printf("%08x (%8s) : [%c%c%c%c] %08x\n", address, nm,
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printf("%08x (%8s) : [%c%c%c%c] %08x\n", address, nm,
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isgraph(a)?a:'.', isgraph(b)?b:'.',
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isgraph(a)?a:'.', isgraph(b)?b:'.',
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isgraph(c)?c:'.', isgraph(d)?d:'.', v);
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isgraph(c)?c:'.', isgraph(d)?d:'.', v);
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} catch(BUSERR b) {
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} catch(BUSERR b) {
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printf("%08x (%8s) : BUS-ERROR\n", address, nm);
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printf("%08x (%8s) : BUS-ERROR\n", address, nm);
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}
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}
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} else {
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} else {
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value = strtoul(argv[1], NULL, 0);
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value = strtoul(argv[1], NULL, 0);
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m_fpga->writeio(address, value);
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m_fpga->writeio(address, value);
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printf("%08x (%8s)-> %08x\n", address, nm, value);
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printf("%08x (%8s)-> %08x\n", address, nm, value);
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}
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}
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if (m_fpga->poll())
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if (m_fpga->poll())
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printf("FPGA was interrupted\n");
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printf("FPGA was interrupted\n");
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delete m_fpga;
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delete m_fpga;
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}
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}
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