--! @file
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--! @file
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--! @brief ControlUnit http://en.wikipedia.org/wiki/Control_unit
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--! @brief ControlUnit http://en.wikipedia.org/wiki/Control_unit
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--! Use standard library and import the packages (std_logic_1164,std_logic_unsigned,std_logic_arith)
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--! Use standard library and import the packages (std_logic_1164,std_logic_unsigned,std_logic_arith)
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library IEEE;
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library IEEE;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_arith.all;
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--! Use CPU Definitions package
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--! Use CPU Definitions package
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use work.pkgOpenCPU32.all;
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use work.pkgOpenCPU32.all;
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--! The control unit coordinates the input and output devices of a computer system. It fetches the code of all of the instructions \n
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--! The control unit coordinates the input and output devices of a computer system. It fetches the code of all of the instructions \n
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--! in the microprograms. It directs the operation of the other units by providing timing and control signals. \n
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--! in the microprograms. It directs the operation of the other units by providing timing and control signals. \n
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--! all computer resources are managed by the Control Unit.It directs the flow of data between the cpu and the other devices.\n
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--! all computer resources are managed by the Control Unit.It directs the flow of data between the cpu and the other devices.\n
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--! The outputs of the control unit control the activity of the rest of the device. A control unit can be thought of as a finite-state machine.
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--! The outputs of the control unit control the activity of the rest of the device. A control unit can be thought of as a finite-state machine.
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--! The purpose of datapaths is to provide routes for data to travel between functional units.
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--! The purpose of datapaths is to provide routes for data to travel between functional units.
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entity ControlUnit is
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entity ControlUnit is
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generic (n : integer := nBits - 1); --! Generic value (Used to easily change the size of the Alu on the package)
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generic (n : integer := nBits - 1); --! Generic value (Used to easily change the size of the Alu on the package)
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Port ( reset : in STD_LOGIC;
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Port ( reset : in STD_LOGIC;
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clk : in STD_LOGIC;
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clk : in STD_LOGIC;
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FlagsDp : in STD_LOGIC_VECTOR (n downto 0);
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FlagsDp : in STD_LOGIC_VECTOR (n downto 0);
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DataDp : in STD_LOGIC_VECTOR (n downto 0);
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DataDp : in STD_LOGIC_VECTOR (n downto 0);
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MuxDp : out STD_LOGIC_VECTOR (2 downto 0);
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MuxDp : out STD_LOGIC_VECTOR (2 downto 0);
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ImmDp : out STD_LOGIC_VECTOR (n downto 0);
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ImmDp : out STD_LOGIC_VECTOR (n downto 0);
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DpRegFileWriteAddr : out STD_LOGIC;
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DpRegFileWriteAddr : out STD_LOGIC;
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DpRegFileWriteEn : out STD_LOGIC;
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DpRegFileWriteEn : out STD_LOGIC;
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DpRegFileReadAddrA : out STD_LOGIC;
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DpRegFileReadAddrA : out STD_LOGIC;
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DpRegFileReadAddrB : out STD_LOGIC;
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DpRegFileReadAddrB : out STD_LOGIC;
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DpRegFileReadEnA : out STD_LOGIC;
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DpRegFileReadEnA : out STD_LOGIC;
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DpRegFileReadEnB : out STD_LOGIC;
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DpRegFileReadEnB : out STD_LOGIC;
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MemoryDataRead : out std_logic;
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MemoryDataRead : out std_logic;
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MemoryDataWrite : out std_logic;
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MemoryDataWrite : out std_logic;
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MemoryDataInput : in STD_LOGIC_VECTOR (n downto 0);
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MemoryDataInput : in STD_LOGIC_VECTOR (n downto 0);
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MemoryDataAddr : out STD_LOGIC_VECTOR (n downto 0);
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MemoryDataAddr : out STD_LOGIC_VECTOR (n downto 0);
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MemoryDataOut : out STD_LOGIC_VECTOR (n downto 0));
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MemoryDataOut : out STD_LOGIC_VECTOR (n downto 0));
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end ControlUnit;
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end ControlUnit;
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--! @brief ControlUnit http://en.wikipedia.org/wiki/Control_unit
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--! @brief ControlUnit http://en.wikipedia.org/wiki/Control_unit
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--! @details The control unit receives external instructions or commands which it converts into a sequence of control signals that the control \n
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--! @details The control unit receives external instructions or commands which it converts into a sequence of control signals that the control \n
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--! unit applies to data path to implement a sequence of register-transfer level operations.
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--! unit applies to data path to implement a sequence of register-transfer level operations.
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architecture Behavioral of ControlUnit is
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architecture Behavioral of ControlUnit is
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signal currentCpuState : controlUnitStates;
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signal currentCpuState : controlUnitStates; -- CPU states
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signal nextCpuState : controlUnitStates;
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signal nextCpuState : controlUnitStates; -- CPU states
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signal PC : std_logic_vector(n downto 0);
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signal PC : std_logic_vector(n downto 0); -- Program Counter
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signal IR : std_logic_vector(n downto 0);
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signal IR : std_logic_vector(n downto 0); -- Intruction register
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signal currInstruction : std_logic_vector(n downto 0); -- Current Intruction
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begin
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begin
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-- Next state logic
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-- Next state logic
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process (clk, reset)
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process (clk, reset)
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begin
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begin
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if (reset = '1') then
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if (reset = '1') then
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currentCpuState <= initial;
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currentCpuState <= initial;
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MemoryDataAddr <= (others => '0');
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MemoryDataAddr <= (others => '0');
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elsif rising_edge(clk) then
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elsif rising_edge(clk) then
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currentCpuState <= nextCpuState;
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currentCpuState <= nextCpuState;
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end if;
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end if;
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end process;
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end process;
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-- assd
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-- States Fetch, decode, execute from the processor
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process (currentCpuState)
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process (currentCpuState)
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variable cyclesExecute : integer range 0 to 20; -- Cycles to wait while executing instruction
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begin
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begin
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case currentCpuState is
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case currentCpuState is
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-- Initial state left from reset ...
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-- Initial state left from reset ...
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when initial =>
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when initial =>
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cyclesExecute := 0;
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PC <= (others => '0');
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PC <= (others => '0');
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IR <= (others => '0');
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MemoryDataRead <= (others => '0');
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MemoryDataRead <= (others => '0');
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MemoryDataWrite <= (others => '0');
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MemoryDataWrite <= (others => '0');
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MemoryDataAddr <= (others => '0');
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MemoryDataAddr <= (others => '0');
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nextCpuState <= fetch;
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nextCpuState <= fetch;
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-- Fetch state (Go to memory and get a instruction)
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-- Fetch state (Go to memory and get a instruction)
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when fetch =>
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when fetch =>
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-- Increment program counter (Remember that PC will be update only on the next cycle...
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-- Increment program counter (Remember that PC will be update only on the next cycle...
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PC <= PC + conv_std_logic_vector(1, nBits);
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PC <= PC + conv_std_logic_vector(1, nBits);
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MemoryDataAddr <= PC; -- Warning PC is not 1 yet...
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MemoryDataAddr <= PC; -- Warning PC is not 1 yet...
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IR <= MemoryDataInput;
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IR <= MemoryDataInput;
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MemoryDataRead <= '1';
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MemoryDataRead <= '1';
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nextCpuState <= decode;
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nextCpuState <= decode;
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-- Detect with instruction came from memory...
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-- Detect with instruction came from memory, set the number of cycles to execute...
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when decode =>
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when decode =>
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MemoryDataRead <= '0';
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MemoryDataRead <= '0';
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MemoryDataWrite <= '0';
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-- The high attribute points to the highes bit position
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case IR((IR'HIGH) downto (IR'HIGH - 5)) is
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when mov_reg =>
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nextCpuState <= execute;
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cyclesExecute := 2;
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currInstruction <= IR;
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-- Invalid instruction (Now will be ignored, but latter shoud rais a trap
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when others =>
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end case;
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-- Wait while the process that handles the execution works..
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when execute =>
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if cyclesExecute > 1 then
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cyclesExecute := cyclesExecute - 1;
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else
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nextCpuState <= fetch;
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end if;
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when others =>
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when others =>
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null;
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null;
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end case;
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end case;
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end process;
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end process;
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-- Process that handles the execution of each instruction
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process (currInstruction)
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begin
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end process;
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end Behavioral;
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end Behavioral;
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