--! @file
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--! @file
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--! @brief ControlUnit http://en.wikipedia.org/wiki/Control_unit
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--! @brief ControlUnit http://en.wikipedia.org/wiki/Control_unit
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--! Use standard library and import the packages (std_logic_1164,std_logic_unsigned,std_logic_arith)
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--! Use standard library and import the packages (std_logic_1164,std_logic_unsigned,std_logic_arith)
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library IEEE;
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library IEEE;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_arith.all;
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--! Use CPU Definitions package
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--! Use CPU Definitions package
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use work.pkgOpenCPU32.all;
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use work.pkgOpenCPU32.all;
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--! The control unit coordinates the input and output devices of a computer system. It fetches the code of all of the instructions \n
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--! The control unit coordinates the input and output devices of a computer system. It fetches the code of all of the instructions \n
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--! in the microprograms. It directs the operation of the other units by providing timing and control signals. \n
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--! in the microprograms. It directs the operation of the other units by providing timing and control signals. \n
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--! all computer resources are managed by the Control Unit.It directs the flow of data between the cpu and the other devices.\n
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--! all computer resources are managed by the Control Unit.It directs the flow of data between the cpu and the other devices.\n
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--! The outputs of the control unit control the activity of the rest of the device. A control unit can be thought of as a finite-state machine.
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--! The outputs of the control unit control the activity of the rest of the device. A control unit can be thought of as a finite-state machine.
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--! The purpose of datapaths is to provide routes for data to travel between functional units.
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--! The purpose of datapaths is to provide routes for data to travel between functional units.
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entity ControlUnit is
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entity ControlUnit is
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generic (n : integer := nBits - 1); --! Generic value (Used to easily change the size of the Alu on the package)
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generic (n : integer := nBits - 1); --! Generic value (Used to easily change the size of the Alu on the package)
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Port ( reset : in STD_LOGIC;
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Port ( reset : in STD_LOGIC;
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clk : in STD_LOGIC; --! Main system clock
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clk : in STD_LOGIC; --! Main system clock
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FlagsDp : in STD_LOGIC_VECTOR (2 downto 0); --! Flags comming from the Datapath
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FlagsDp : in STD_LOGIC_VECTOR (2 downto 0); --! Flags comming from the Datapath
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DataDp : in STD_LOGIC_VECTOR (n downto 0); --! Data comming from the Datapath
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DataDp : in STD_LOGIC_VECTOR (n downto 0); --! Data comming from the Datapath
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outEnDp : out typeEnDis; --! Enable/Disable datapath output
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outEnDp : out typeEnDis; --! Enable/Disable datapath output
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MuxDp : out dpMuxInputs; --! Select on datapath data from (Memory, Imediate, RegFileA, RegFileB, AluOut)
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MuxDp : out dpMuxInputs; --! Select on datapath data from (Memory, Imediate, RegFileA, RegFileB, AluOut)
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MuxRegDp : out dpMuxAluIn; --! Select Alu InputA (Memory,Imediate,RegFileA)
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MuxRegDp : out dpMuxAluIn; --! Select Alu InputA (Memory,Imediate,RegFileA)
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ImmDp : out STD_LOGIC_VECTOR (n downto 0); --! Imediate value passed to the Datapath
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ImmDp : out STD_LOGIC_VECTOR (n downto 0); --! Imediate value passed to the Datapath
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DpAluOp : out aluOps; --! Alu operations
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DpAluOp : out aluOps; --! Alu operations
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DpRegFileWriteAddr : out generalRegisters; --! General register address to write
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DpRegFileWriteAddr : out generalRegisters; --! General register address to write
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DpRegFileWriteEn : out STD_LOGIC; --! Enable register write
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DpRegFileWriteEn : out STD_LOGIC; --! Enable register write
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DpRegFileReadAddrA : out generalRegisters; --! General register address to read
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DpRegFileReadAddrA : out generalRegisters; --! General register address to read
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DpRegFileReadAddrB : out generalRegisters; --! General register address to read
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DpRegFileReadAddrB : out generalRegisters; --! General register address to read
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DpRegFileReadEnA : out STD_LOGIC; --! Enable register read (PortA)
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DpRegFileReadEnA : out STD_LOGIC; --! Enable register read (PortA)
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DpRegFileReadEnB : out STD_LOGIC; --! Enable register read (PortB)
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DpRegFileReadEnB : out STD_LOGIC; --! Enable register read (PortB)
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MemoryDataReadEn : out std_logic; --! Enable Main memory read
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MemoryDataReadEn : out std_logic; --! Enable Main memory read
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MemoryDataWriteEn: out std_logic; --! Enable Main memory write
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MemoryDataWriteEn: out std_logic; --! Enable Main memory write
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MemoryDataInput : in STD_LOGIC_VECTOR (n downto 0); --! Incoming data from main memory
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MemoryDataInput : in STD_LOGIC_VECTOR (n downto 0); --! Incoming data from main memory
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MemoryDataRdAddr : out STD_LOGIC_VECTOR (n downto 0); --! Main memory Read address
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MemoryDataRdAddr : out STD_LOGIC_VECTOR (n downto 0); --! Main memory Read address
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MemoryDataWrAddr : out STD_LOGIC_VECTOR (n downto 0); --! Main memory Write address
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MemoryDataWrAddr : out STD_LOGIC_VECTOR (n downto 0); --! Main memory Write address
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MemoryDataOut : out STD_LOGIC_VECTOR (n downto 0)); --! Data to write on main memory
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MemoryDataOut : out STD_LOGIC_VECTOR (n downto 0)); --! Data to write on main memory
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end ControlUnit;
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end ControlUnit;
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--! @brief ControlUnit http://en.wikipedia.org/wiki/Control_unit
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--! @brief ControlUnit http://en.wikipedia.org/wiki/Control_unit
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--! @details The control unit receives external instructions or commands which it converts into a sequence of control signals that the control \n
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--! @details The control unit receives external instructions or commands which it converts into a sequence of control signals that the control \n
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--! unit applies to data path to implement a sequence of register-transfer level operations.
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--! unit applies to data path to implement a sequence of register-transfer level operations.
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architecture Behavioral of ControlUnit is
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architecture Behavioral of ControlUnit is
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signal currentCpuState : controlUnitStates; -- CPU states
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signal currentCpuState : controlUnitStates; -- CPU states
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signal nextCpuState : controlUnitStates; -- CPU states
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signal nextCpuState : controlUnitStates; -- CPU states
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signal currentExState : executionStates; -- Execution states
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signal currentExState : executionStates; -- Execution states
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signal nextExState : executionStates; -- Execution states
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signal nextExState : executionStates; -- Execution states
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signal PC : std_logic_vector(n downto 0); -- Program Counter
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signal PC : std_logic_vector(n downto 0); -- Program Counter
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signal IR : std_logic_vector(n downto 0); -- Intruction register
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signal IR : std_logic_vector(n downto 0); -- Intruction register
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signal currInstruction : std_logic_vector(n downto 0); -- Current Intruction
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signal currInstruction : std_logic_vector(n downto 0); -- Current Intruction
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begin
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begin
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-- Next state logic (CPU, fetch, decode, execute states)
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-- Next state logic (CPU, fetch, decode, execute states)
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process (clk, reset)
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process (clk, reset)
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begin
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begin
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if (reset = '1') then
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if (reset = '1') then
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currentCpuState <= initial;
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currentCpuState <= initial;
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elsif rising_edge(clk) then
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elsif rising_edge(clk) then
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currentCpuState <= nextCpuState;
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currentCpuState <= nextCpuState;
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end if;
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end if;
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end process;
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end process;
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-- Next state logic (Execution states)
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-- Next state logic (Execution states)
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process (clk, currentCpuState)
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process (clk, currentCpuState)
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begin
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begin
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if (reset = '1') then
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if (reset = '1') then
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currentExState <= initInstructionExecution;
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currentExState <= initInstructionExecution;
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elsif rising_edge(clk) then
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elsif rising_edge(clk) then
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currentExState <= nextExState;
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currentExState <= nextExState;
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end if;
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end if;
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end process;
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end process;
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-- States Fetch, decode, execute from the processor (Also handles the execution of jump instructions)
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-- States Fetch, decode, execute from the processor (Also handles the execution of jump instructions)
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process (currentCpuState)
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process (currentCpuState)
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variable cyclesExecute : integer range 0 to 20; -- Cycles to wait while executing instruction
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variable cyclesExecute : integer range 0 to 20; -- Cycles to wait while executing instruction
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variable opcodeIR : std_logic_vector(5 downto 0);
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variable opcodeIR : std_logic_vector(5 downto 0);
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variable operand_reg1 : std_logic_vector(3 downto 0);
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variable operand_reg1 : std_logic_vector(3 downto 0);
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variable operand_imm : std_logic_vector(21 downto 0);
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variable operand_imm : std_logic_vector(21 downto 0);
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variable accDp : std_logic_vector(n downto 0); -- Value stored from DataPath
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variable accDp : std_logic_vector(n downto 0); -- Value stored from DataPath
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begin
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begin
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opcodeIR := IR((IR'HIGH) downto (IR'HIGH - 5));
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opcodeIR := IR((IR'HIGH) downto (IR'HIGH - 5));
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operand_reg1 := IR((IR'HIGH - 6) downto (IR'HIGH - 9)); -- 4 bits register operand1 (Max 16 registers)
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operand_reg1 := IR((IR'HIGH - 6) downto (IR'HIGH - 9)); -- 4 bits register operand1 (Max 16 registers)
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operand_imm := IR((IR'HIGH - 10) downto (IR'LOW)); -- 22 bits imediate value (Max value 4194304)
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operand_imm := IR((IR'HIGH - 10) downto (IR'LOW)); -- 22 bits imediate value (Max value 4194304)
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case currentCpuState is
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case currentCpuState is
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-- Initial state left from reset ...
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-- Initial state left from reset ...
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when initial =>
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when initial =>
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cyclesExecute := 0;
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cyclesExecute := 0;
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PC <= (others => '0');
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PC <= (others => '0');
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IR <= (others => '0');
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IR <= (others => '0');
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MemoryDataRdAddr <= (others => '0');
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MemoryDataRdAddr <= (others => '0');
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MemoryDataReadEn <= '0';
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MemoryDataReadEn <= '0';
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MemoryDataWriteEn <= '0';
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MemoryDataWriteEn <= '0';
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nextCpuState <= fetch;
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nextCpuState <= fetch;
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-- Fetch state (Go to memory and get a instruction)
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-- Fetch state (Go to memory and get a instruction)
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when fetch =>
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when fetch =>
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-- Increment program counter (Remember that PC will be update only on the next cycle...
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-- Increment program counter (Remember that PC will be update only on the next cycle...
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PC <= PC + conv_std_logic_vector(1, nBits);
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PC <= PC + conv_std_logic_vector(1, nBits);
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MemoryDataRdAddr <= PC; -- Warning PC is not 1 yet...
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MemoryDataRdAddr <= PC; -- Warning PC is not 1 yet...
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IR <= MemoryDataInput;
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IR <= MemoryDataInput;
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MemoryDataReadEn <= '1';
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MemoryDataReadEn <= '1';
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MemoryDataWriteEn <= '0';
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MemoryDataWriteEn <= '0';
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nextCpuState <= decode;
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nextCpuState <= decode;
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-- Detect with instruction came from memory, set the number of cycles to execute...
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-- Detect with instruction came from memory, set the number of cycles to execute...
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when decode =>
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when decode =>
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MemoryDataReadEn <= '0';
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MemoryDataReadEn <= '0';
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MemoryDataWriteEn <= '0';
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MemoryDataWriteEn <= '0';
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-- The high attribute points to the highes bit position
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-- The high attribute points to the highes bit position
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case opcodeIR is
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case opcodeIR is
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when mov_reg | mov_val | add_reg | add_val | sub_reg | and_reg | or_reg | xor_reg =>
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when mov_reg | mov_val | add_reg | add_val | sub_reg | and_reg | or_reg | xor_reg =>
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nextCpuState <= execute;
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nextCpuState <= execute;
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cyclesExecute := 1; -- Wait 1 cycles
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cyclesExecute := 1; -- Wait 1 cycles
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currInstruction <= IR;
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currInstruction <= IR;
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when ld_reg | ld_val | stom_reg | stom_val =>
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when ld_reg | ld_val | stom_reg | stom_val =>
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nextCpuState <= execute;
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nextCpuState <= execute;
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cyclesExecute := 2; -- Wait 2 cycles
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cyclesExecute := 2; -- Wait 2 cycles
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currInstruction <= IR;
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currInstruction <= IR;
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when jmp_val | jmpr_val =>
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when jmp_val | jmpr_val =>
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nextCpuState <= execute;
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nextCpuState <= execute;
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cyclesExecute := 0; -- No Wait cycle
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cyclesExecute := 0; -- No Wait cycle
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-- Invalid instruction (Now will be ignored, but latter should raise a trap
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-- Invalid instruction (Now will be ignored, but latter should raise a trap
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when others =>
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when others =>
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null;
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null;
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end case;
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end case;
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-- Wait while the process that handles the execution works..
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-- Wait while the process that handles the execution works..
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when execute =>
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when execute =>
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-- On the case of jump instructions, it's execution will be handled on this process
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-- On the case of jump instructions, it's execution will be handled on this process
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case opcodeIR is
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case opcodeIR is
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when jmp_val =>
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when jmp_val =>
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PC <= "0000000000" & operand_imm;
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PC <= "0000000000" & operand_imm;
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nextCpuState <= fetch;
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when jmpr_val =>
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when jmpr_val =>
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PC <= PC + ("0000000000" & operand_imm);
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PC <= PC + ("0000000000" & operand_imm);
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nextCpuState <= fetch;
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-- ld r5,20 (Load into r5 register the content of the memory at address 20)
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-- ld r5,20 (Load into r5 register the content of the memory at address 20)
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when ld_val =>
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when ld_val =>
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MemoryDataRdAddr <= "0000000000" & operand_imm;
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MemoryDataRdAddr <= "0000000000" & operand_imm;
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MemoryDataReadEn <= '1';
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MemoryDataReadEn <= '1';
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if cyclesExecute = 0 then
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if cyclesExecute = 0 then
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MemoryDataReadEn <= '0';
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MemoryDataReadEn <= '0';
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end if;
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end if;
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-- STORE r1,10 (Store the value 10 on memory address pointed by r1)
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-- STORE r1,10 (Store the value 10 on memory address pointed by r1)
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when stom_val =>
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when stom_val =>
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-- And put the imediate value ...
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-- And put the imediate value ...
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MemoryDataOut <= "0000000000" & operand_imm;
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MemoryDataOut <= "0000000000" & operand_imm;
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if cyclesExecute = 1 then
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if cyclesExecute = 1 then
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-- After the register data is avaible in DataDp we put it's address and
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-- After the register data is avaible in DataDp we put it's address and
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accDp := DataDp;
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accDp := DataDp;
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MemoryDataWrAddr <= accDp;
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MemoryDataWrAddr <= accDp;
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elsif cyclesExecute = 0 then
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elsif cyclesExecute = 0 then
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-- strobe in to enter the data
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-- strobe in to enter the data
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MemoryDataWriteEn <= '1';
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MemoryDataWriteEn <= '1';
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end if;
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end if;
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when others =>
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when others =>
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null;
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null;
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end case;
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end case;
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if cyclesExecute = 0 then
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if cyclesExecute = 0 then
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-- Finish the instruction execution get next
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-- Finish the instruction execution get next
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nextCpuState <= fetch;
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nextCpuState <= fetch;
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else
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else
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nextCpuState <= executing;
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nextCpuState <= executing;
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end if;
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end if;
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-- Just wait a cycle and back again to execute state which verify if still need to wait some cycles
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-- Just wait a cycle and back again to execute state which verify if still need to wait some cycles
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when executing =>
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when executing =>
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cyclesExecute := cyclesExecute - 1;
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cyclesExecute := cyclesExecute - 1;
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nextCpuState <= execute;
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nextCpuState <= execute;
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when others =>
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when others =>
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null;
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null;
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end case;
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end case;
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end process;
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end process;
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-- Process that handles the execution of each instruction (Excluding the call,jump,load,store instructions)
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-- Process that handles the execution of each instruction (Excluding the call,jump,load,store instructions)
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process (currentExState)
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process (currentExState)
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--variable operando1_reg : std_logic_vector(generalRegisters'range);
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--variable operando1_reg : std_logic_vector(generalRegisters'range);
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variable opcodeIR : std_logic_vector(5 downto 0);
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variable opcodeIR : std_logic_vector(5 downto 0);
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variable operand_reg1 : std_logic_vector(3 downto 0);
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variable operand_reg1 : std_logic_vector(3 downto 0);
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variable operand_reg2 : std_logic_vector(3 downto 0);
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variable operand_reg2 : std_logic_vector(3 downto 0);
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variable operand_imm : std_logic_vector(21 downto 0);
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variable operand_imm : std_logic_vector(21 downto 0);
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begin
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begin
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-- Parse the common operands
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-- Parse the common operands
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opcodeIR := IR((IR'HIGH) downto (IR'HIGH - 5)); -- 6 Bits opcode (Max 64 instructions)
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opcodeIR := IR((IR'HIGH) downto (IR'HIGH - 5)); -- 6 Bits opcode (Max 64 instructions)
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operand_reg1 := IR((IR'HIGH - 6) downto (IR'HIGH - 9)); -- 4 bits register operand1 (Max 16 registers)
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operand_reg1 := IR((IR'HIGH - 6) downto (IR'HIGH - 9)); -- 4 bits register operand1 (Max 16 registers)
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operand_reg2 := IR((IR'HIGH - 10) downto (IR'HIGH - 13)); -- 4 bits register operand2 (Max 16 registers
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operand_reg2 := IR((IR'HIGH - 10) downto (IR'HIGH - 13)); -- 4 bits register operand2 (Max 16 registers
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operand_imm := IR((IR'HIGH - 10) downto (IR'LOW)); -- 22 bits imediate value (Max value 4194304)
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operand_imm := IR((IR'HIGH - 10) downto (IR'LOW)); -- 22 bits imediate value (Max value 4194304)
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-- Select the instruction and init it's execution
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-- Select the instruction and init it's execution
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case currentExState is
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case currentExState is
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when initInstructionExecution =>
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when initInstructionExecution =>
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nextExState <= waitToExecute;
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nextExState <= waitToExecute;
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when waitToExecute =>
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when waitToExecute =>
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if ( (currentCpuState /= execute) and (currentCpuState /= executing) ) then
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if ( (currentCpuState /= execute) and (currentCpuState /= executing) ) then
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nextExState <= initInstructionExecution;
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nextExState <= initInstructionExecution;
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else
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else
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case opcodeIR is
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case opcodeIR is
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-- MOV r2,r1 (See the testDatapath to see how to drive the datapath for this function)
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-- MOV r2,r1 (See the testDatapath to see how to drive the datapath for this function)
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when mov_reg =>
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when mov_reg =>
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MuxDp <= fromRegFileB;
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MuxDp <= fromRegFileB;
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DpRegFileReadAddrB <= Num2reg(conv_integer(UNSIGNED(operand_reg2)));
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DpRegFileReadAddrB <= Num2reg(conv_integer(UNSIGNED(operand_reg2)));
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DpRegFileWriteAddr <= Num2reg(conv_integer(UNSIGNED(operand_reg1)));
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DpRegFileWriteAddr <= Num2reg(conv_integer(UNSIGNED(operand_reg1)));
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DpRegFileReadEnB <= '1';
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DpRegFileReadEnB <= '1';
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nextExState <= writeRegister;
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nextExState <= writeRegister;
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-- LOAD r1,10 (Load into r1, the value in the main memory located at address 10)
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-- LOAD r1,10 (Load into r1, the value in the main memory located at address 10)
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when ld_val =>
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when ld_val =>
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MuxDp <= fromMemory;
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MuxDp <= fromMemory;
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DpRegFileWriteAddr <= Num2reg(conv_integer(UNSIGNED(operand_reg1)));
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DpRegFileWriteAddr <= Num2reg(conv_integer(UNSIGNED(operand_reg1)));
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-- The part that interface with the memory is located on the first process
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-- The part that interface with the memory is located on the first process
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nextExState <= writeRegister;
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nextExState <= writeRegister;
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-- STORE r1,10 (Store the value 10 on the main memory pointed by r1)
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-- STORE r1,10 (Store the value 10 on the main memory pointed by r1)
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when stom_val =>
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when stom_val =>
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MuxDp <= fromRegFileB;
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MuxDp <= fromRegFileB;
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DpRegFileReadAddrB <= Num2reg(conv_integer(UNSIGNED(operand_reg1)));
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DpRegFileReadAddrB <= Num2reg(conv_integer(UNSIGNED(operand_reg1)));
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DpRegFileReadEnB <= '1';
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DpRegFileReadEnB <= '1';
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-- The part that interface with the memory is located on the first process
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-- The part that interface with the memory is located on the first process
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nextExState <= readRegisterB;
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nextExState <= readRegisterB;
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-- ADD r2,r0 (See the testDatapath to see how to drive the datapath for this function)
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-- ADD r2,r0 (See the testDatapath to see how to drive the datapath for this function)
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when add_reg | sub_reg | and_reg | or_reg | xor_reg =>
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when add_reg | sub_reg | and_reg | or_reg | xor_reg =>
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MuxDp <= fromAlu;
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MuxDp <= fromAlu;
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MuxRegDp <= fromRegFileA;
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MuxRegDp <= fromRegFileA;
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DpRegFileReadAddrA <= Num2reg(conv_integer(UNSIGNED(operand_reg1))); -- Read first operand
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DpRegFileReadAddrA <= Num2reg(conv_integer(UNSIGNED(operand_reg1))); -- Read first operand
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DpRegFileReadAddrB <= Num2reg(conv_integer(UNSIGNED(operand_reg2))); -- Read second operand
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DpRegFileReadAddrB <= Num2reg(conv_integer(UNSIGNED(operand_reg2))); -- Read second operand
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DpRegFileReadEnA <= '1';
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DpRegFileReadEnA <= '1';
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DpRegFileReadEnB <= '1';
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DpRegFileReadEnB <= '1';
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DpRegFileWriteAddr <= Num2reg(conv_integer(UNSIGNED(operand_reg1))); -- Point to write in first operand (pointing to register)
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DpRegFileWriteAddr <= Num2reg(conv_integer(UNSIGNED(operand_reg1))); -- Point to write in first operand (pointing to register)
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DpAluOp <= opcode2AluOp(opcodeIR); -- Select the alu operation from the operand
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DpAluOp <= opcode2AluOp(opcodeIR); -- Select the alu operation from the operand
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nextExState <= writeRegister;
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nextExState <= writeRegister;
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-- MOV r0,10d (See the testDatapath to see how to drive the datapath for this function)
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-- MOV r0,10d (See the testDatapath to see how to drive the datapath for this function)
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when mov_val =>
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when mov_val =>
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MuxDp <= fromImediate;
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MuxDp <= fromImediate;
|
DpRegFileWriteAddr <= Num2reg(conv_integer(UNSIGNED(operand_reg1)));
|
DpRegFileWriteAddr <= Num2reg(conv_integer(UNSIGNED(operand_reg1)));
|
ImmDp <= "0000000000" & operand_imm; -- & is used to concatenate signals
|
ImmDp <= "0000000000" & operand_imm; -- & is used to concatenate signals
|
nextExState <= writeRegister;
|
nextExState <= writeRegister;
|
|
|
-- ADD r3,2 (r2 <= r2+2) (See the testDatapath to see how to drive the datapath for this function)
|
-- ADD r3,2 (r2 <= r2+2) (See the testDatapath to see how to drive the datapath for this function)
|
when add_val | sub_val | and_val | or_val | xor_val =>
|
when add_val | sub_val | and_val | or_val | xor_val =>
|
MuxDp <= fromAlu;
|
MuxDp <= fromAlu;
|
MuxRegDp <= fromImediate;
|
MuxRegDp <= fromImediate;
|
DpRegFileWriteAddr <= Num2reg(conv_integer(UNSIGNED(operand_reg1)));
|
DpRegFileWriteAddr <= Num2reg(conv_integer(UNSIGNED(operand_reg1)));
|
DpRegFileReadAddrB <= Num2reg(conv_integer(UNSIGNED(operand_reg1))); -- Read first operand
|
DpRegFileReadAddrB <= Num2reg(conv_integer(UNSIGNED(operand_reg1))); -- Read first operand
|
DpRegFileReadEnB <= '1';
|
DpRegFileReadEnB <= '1';
|
ImmDp <= "0000000000" & operand_imm; -- & is used to concatenate signals
|
ImmDp <= "0000000000" & operand_imm; -- & is used to concatenate signals
|
DpAluOp <= opcode2AluOp(opcodeIR); -- Select the alu operation from the operand
|
DpAluOp <= opcode2AluOp(opcodeIR); -- Select the alu operation from the operand
|
nextExState <= writeRegister;
|
nextExState <= writeRegister;
|
|
|
when others =>
|
when others =>
|
null;
|
null;
|
end case;
|
end case;
|
end if;
|
end if;
|
|
|
-- Write something on the register files
|
-- Write something on the register files
|
when writeRegister =>
|
when writeRegister =>
|
DpRegFileWriteEn <= '1';
|
DpRegFileWriteEn <= '1';
|
nextExState <= releaseWriteRead;
|
nextExState <= releaseWriteRead;
|
|
|
when readRegisterB =>
|
when readRegisterB =>
|
DpRegFileReadEnB <= '1';
|
DpRegFileReadEnB <= '1';
|
outEnDp <= enable;
|
outEnDp <= enable;
|
nextExState <= releaseWriteRead;
|
nextExState <= releaseWriteRead;
|
|
|
when readRegisterA =>
|
when readRegisterA =>
|
DpRegFileReadEnA <= '1';
|
DpRegFileReadEnA <= '1';
|
outEnDp <= enable;
|
outEnDp <= enable;
|
nextExState <= releaseWriteRead;
|
nextExState <= releaseWriteRead;
|
|
|
-- Release lines (Reset Datapath lines to something that does nothing...)
|
-- Release lines (Reset Datapath lines to something that does nothing...)
|
when releaseWriteRead =>
|
when releaseWriteRead =>
|
DpRegFileReadEnB <= '0';
|
DpRegFileReadEnB <= '0';
|
DpRegFileReadEnA <= '0';
|
DpRegFileReadEnA <= '0';
|
DpRegFileWriteEn <= '0';
|
DpRegFileWriteEn <= '0';
|
outEnDp <= disable;
|
outEnDp <= disable;
|
-- Come back to waiting state
|
-- Come back to waiting state
|
nextExState <= waitToExecute;
|
nextExState <= waitToExecute;
|
|
|
when others =>
|
when others =>
|
null;
|
null;
|
end case;
|
end case;
|
end process;
|
end process;
|
|
|
end Behavioral;
|
end Behavioral;
|
|
|
|
|
